ITEC 1000 Introduction to Information Technology

Lecture 6

The CPU and Memory

Pitxot, Antoni Figures of the Allegory of Memory 1981 Oil on canvas 180.30 x 90.40 cm. TEATRE-MUSEU DALI

http://www.salvador-dali.org/dali/coleccio

[Prof. Peter Khaiter]

Lecture Template:
CPU  Registers  Register operations  Memory implementation  Computer Buses  Instructions  Using the Stacks  Multiple Data Instructions


Computer unit

CPU
ALU Input/output interface

Highest Address

Memory

Control unit Program counter

Lowest Address

Memory is separated from the CPU

Components of the CPU (1 of 2)



ALU (arithmetic logic unit)

Performs arithmetic and logic operations (data changed) Arithmetic: add, subtract, multiply, divide, etc. Logic: AND, OR, NOT, Shift, etc. Data held temporary

CU (control unit): functions

performs fetch/execute cycle Accesses and retrieves program instructions from the memory and issues commands to the ALU Moves data to and from CPU registers and other hardware components (no change in data)

Registers
Example: Program counter (PC) or instruction pointer determines next instruction for execution
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Components of the CU (2 of 2)
Program counter (instruction pointer)
Contains the address of the current or next instruction Normally instructions are executed sequentially

Memory management unit

Supervises fetching of instructions and data from memory

I/O Interface
Provides mechanism for input/output of data sometimes combined with memory management unit in a single Bus Interface Unit
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Concept of Registers

   

 

Single storage locations within the CPU used for a particular purpose Used to hold a binary value temporarily Manipulated directly by the Control Unit Each register is wired within the CPU directly (no address needed) for specific function Size in bits or bytes (not MB like memory) Can hold data, an address or an instruction
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Registers: what they do

Hold data being processed  Hold instruction being executed  Memory or I/O address being accessed  Keep status of the computer  Conditional branch instructions


GeneralGeneral-Purpose Registers
User-visible registers Part of ALU Accumulators Typically several dozen in modern CPUs (R0, R1,) Hold data of arithmetic operations Hold intermediate results or data values, e.g., loop counters To transfer data between different memory locations and between I/0 and memory 8

      

Special-Purpose Registers Special    

Part of CU Program Counter Register (PC) (instruction pointer) Holds address of the currently executed instruction Instruction Register (IR) Holds the actual instruction being executed Memory Address Register (MAR) Holds the address of a memory location Memory Data Register (MDR) Holds the actual data value from location specified in MAR Flags (one-bit register) to track special conditions like arithmetic carry and overflow, power failure, internal computer error Status Registers Several flag registers grouped together 9

Register Operations
Load values from other locations (registers and memory)
Destroys (erases) previous value in destination Source register (or memory location) unchangeable

  

Addition and subtraction

Result stored in the register

Shift or rotate (left or right) data Test contents for conditions

zero Positive/negative To large

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Program Counter ( PC )

A dedicated register in the CPU Contains the address in memory of the current instruction being executed. Incremented automatically after each instruction. May be forced to change: e.g. jump instruction. Usually initialized to zero when machine starts, or is reset.
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Instruction Register ( IR )

A dedicated register in the CP which contains the actual current instruction.

Op Code What To Do
Simple 16-bit example:

Address ocation of Data

1101 101101100100
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Accumulator

A dedicated register (or set of registers) in the CP used for the actual manipulation of data Default source (or destination) register sually contains results of arithmetic or logical operations

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Operation of Memory Each memory location has a unique address  Address from an instruction is copied to the MAR which finds the location in memory  CPU determines if it is a store or retrieval  Transfer takes place between the MDR and memory  MDR is a two way register 14


MAR and MDR

Memory Address Register (MAR)

Contains Address in memory to find or place data

Memory Data Register (MDR)

Contains Actual Data to be placed in location given in MAR, or which has been retrieved from location given in MAR
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Generic CPU With Registers

Program Counter ( PC ) Instruction Register ( IR ) Memory Address Register ( MAR ) Memory Data Register ( MDR ) Accumulator ( A or Acc ) Memory

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MAR, MDR and Memory

Address

Data

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MARMAR-MDR: Example

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Individual Memory Cell

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Memory Capacity


Determined by two factors

1. Number of bits in the MAR
2K where K = width of the MAR register in bits 4 bits allow 16 locations 8 bits allow 256 locations 32 bits allow 4,294,967,296 or 4 GB

2. Size of each memory location, m

 

Memory capacity is the product:

m x 2K

Typical values:
k: 16, 17, 18, 19, 20, 21, 22, etc. m: 8, 16, 32, 64
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Memory Implementation Magnetic core (1949/51 late 1960s/early 1970s  Random Access Memory (RAM)  Read Only Memory (ROM)  EEPROM  Flash ROM  Volatile  Nonvolatile

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RAM: Random Access Memory



 

Random any piece of data can be accessed in a constant time regardless of physical location (unlike tapes, magnetic or optical discs) Difference in technical design DRAM (Dynamic RAM)
Most common, cheap Volatile: must be refreshed (recharged with power) 1000s of times each second

SRAM (static RAM)

Faster to access than DRAM and more expensive than DRAM Volatile small amount used in cache memory for high-speed access 22

RAM: Sample

DRAM modules used as primary memory in PCs, workstations, servers. 23

ROM - Read Only Memory

   

Implemented in early stored-program computers (e.g., ENIAC, after 1948) If write protected, becomes read-only memory Non-volatile memory to hold built-in software that is not expected to change over the life of the computer (e.g., initial program that runs computer)
BIOS: initial boot instructions and diagnostics

 

Data are physically encoded into chips EEPROM

Electrically Erasable Programmable ROM Can be erased and reprogrammed, 1 byte at a time (up to 1000 times) Slower and less flexible than Flash ROM

Flash ROM
Modern type of EEPROM (invented in 1984), faster (erase and write in blocks of bytes) Higher endurance (up to 1,000,000 cycles) E.g., USB Flash Drives

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ROM: Sample

First erasable ROM, Intel 1702; erase window in the middle

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Memory Maps The usage of memory space on a system is commonly depicted in a memory map  The height of the map is determined by the number of addresses  The width of the map is usually 8 bits  E.g.,


a system with a capacity of 216 bytes

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Memory Map: Sample 1

7 6 5 4 3 2 1 0 FFFF

Data bit position

Hexadecimal address

0002 0001 0000

The bottom of memory 27

Use of Memory Maps

  

Memory maps are usually drawn to show what is where on a system what can be:
RAM, ROM, I/O, empty space

Where:
Determined by the starting/ending addresses for each block of RAM, ROM, I/O,,

E.g.,
a memory map for a system with a capacity of 224 bytes with two 1 MB RAM modules residing consecutively at the bottom of memory.
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Memory Map: Sample 2

FFFFFF

14 MB 224 bytes = 16 MB capacity

200000 1FFFFF 100000 0FFFFF 000000

empty

1 MB RAM 1 MB RAM
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Memory Space: Exercise 1 Q: A system with a memory capacity of 128 GB has four 32 MB memory modules installed. The rest of the memory is unused. How much memory space is available for future expansion? (Give your answer in decimal in megabytes.) A: ?
Skip answer Answer
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Memory Space: Exercise 1

Answer

Q: A system with a memory capacity of 128 GB has four 32 MB memory modules installed. The rest of the memory is unused. How much memory space is available for future expansion? (Give your answer in decimal in megabytes.) A: 128 GB 4 x 32 MB = 27 x 210 MB - 22 x 25 MB = (217 27) MB = (131,072 128) MB = 130,944 MB 210

= 127.875 GB
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Memory Space: Exercise 2



Draw a memory map for a system with a capacity of 2 GB. Assume the system has three 32 MB memory modules residing consecutively at the bottom of memory. Illustrate the size of each block in MB and the starting and ending address of each block of memory in hexadecimal.
Skip answer Answer
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Memory Space: Exercise 2

Answer

7FFFFFFF

1,952 MB empty 231 bytes = 2 GB capacity

Note: 2 GB = 2,048 MB 06000000 05FFFFFF 04000000 03FFFFFF 02000000 01FFFFFF 00000000
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32 MB RAM 32 MB RAM 32 MB RAM

FetchFetch-Execute Cycle

Two-step process because both instructions and data are in memory  Fetch


Decode or find instruction, load the code of the instruction from memory


Execute
Performs operation that instruction requires Move/transform data
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FetchFetch-part of the Cycle

The value in the PC (program counter) register is the address of the memory location that holds instruction to be executed First step is always: transfer (copy) the value in the PC to the MAR Then computer can retrieve the instruction located at that address and place it in the MDR PC MAR (step 1) Memory MDR Next step: transfer instruction to the IR MDR IR (step 2) Remaining steps instruction dependent
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Load Instruction
       

Next step: the address part of the instruction located in the IR is copied and placed in the MAR Computer retrieves actual data located at the address in memory and places it in the MDR IR [address] MAR (step 3) Memory MDR Next step: MDR copies data to the accumulator register MDR A (step 4) Last step: PC is incremented PC + 1 PC (step 5)

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Load Accumulator: Sample (1 of 12)

Task:

Simple Eight bit system. Thirty-two memory locations (0 to 31). oad instruction is 010. Value in location 15 is ten (i.e.: binary 00001010) PC is at 5, about to increment. The instruction, 01001111, is in location 6.

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Load Accumulator: Sample (2 of 12)

CP Before PC increments Memory
Location 31

PC: IR:

00101 (previous)
15: 00001010

MAR: (previous) MDR: (previous) A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (3 of 12)

Increment PC: PC = PC + 1 Memory
Location 31

PC: IR:

00110 (previous)
15: 00001010

MAR: (previous) MDR: (previous) A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (4 of 12)

MAR loaded with PC: PC -> MAR Memory
Location 31

PC: IR:

00110 (previous)
15: 00001010

MAR: 00110 MDR: (previous) A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (5 of 12)

Memory Location 00110 Accessed and Contents Placed in MDR:

Memory
Location 31

PC: IR:

00110 (previous)
15: 00001010

MAR: 00110 MDR: (previous) A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (6 of 12)

Memory ocation 00110 Accessed and Contents Placed in MDR:

Memory
Location 31

PC: IR:

00110 (previous)
15: 00001010

MAR: 00110 MDR: 01001111 A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (7 of 12)

MDR copied to IR: MDR -> IR

Memory
Location 31

PC: IR:

00110 01001111
15: 00001010

MAR: 00110 MDR: 01001111 A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (8 of 12)

IR [ address part ] -> MAR

Memory
Location 31

PC: IR:

00110 01001111
15: 00001010

MAR: 01111 MDR: 01001111 A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (9 of 12)

Location in MAR (01111) Accessed

Memory
Location 31

PC: IR:

00110 01001111
15: 00001010

MAR: 01111 MDR: 01001111 A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (10 of 12)

Contents of 01111 loaded into MDR

Memory
Location 31

PC: IR:

00110 01001111
15: 00001010

MAR: 01111 MDR: 00001010 A: (previous)

06: 01001111 Location 0

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Load Accumulator: Sample (11 of 12)

IR [op code] executed: MDR -> A

Memory
Location 31

PC: IR:

00110 01001111
15: 00001010

MAR: 01111 MDR: 00001010 A: 00001010

06: 01001111 Location 0

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Load Accumulator: Sample (12 of 12)

Finished !
Memory
Location 31

PC: IR:

00110 01001111
15: 00001010

MAR: 01111 MDR: 00001010 A: 00001010

06: 01001111 Location 0

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Load Fetch/Execute Cycle

1.

PC -> MAR MDR -> IR

Transfer the address from the PC to the MAR

2.

3.

Transfer the instruction to the IR IR(address) -> MAR Address portion of the instruction loaded in MAR MDR -> A PC + 1 -> PC Actual data copied into the accumulator Program Counter incremented
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4.

5.

Store Fetch/Execute Cycle (1 of 2)

PC -> MAR MDR -> IR Transfer the address from the PC to the MAR

1.

2.

3.

Transfer the instruction to the IR IR(address) -> MAR Address portion of the instruction loaded in MAR A -> MDR* PC + 1 -> PC Accumulator copies data into MDR Program Counter incremented
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4.

5.

*Notice how Step #4 differs for LOAD and STORE

Store Fetch/Execute Cycle (2 of 2)

Fetch

PC MDR

MAR IR MAR time

IR[address] Execute A MDR PC

PC + 1

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ADD Fetch/Execute Cycle (1 of 2)

1.

PC -> MAR MDR -> IR

Transfer the address from the PC to the MAR

2.

3.

Transfer the instruction to the IR IR(address) -> MAR Address portion of the instruction loaded in MAR A + MDR -> A PC + 1 -> PC Contents of MDR added to contents of accumulator Program Counter incremented
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4.

5.

ADD Fetch/Execute Cycle (2 of 2)

Fetch

PC MDR

MAR IR MAR time

IR[address] Execute A + MDR PC + 1 A PC

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Add Instruction: Sample (1 of 10)

New: Task: Value in location 7 is 10110010. Add instruction is 101. Value in location 18 is seventy-one (i.e.: binary 01000111) Everything else is as we left it!

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Add Instruction: Sample (2 of 10)

PC = PC + 1

Memory
Location 31

PC: IR:

00111 01001111
18: 01000111 15: 00001010

MAR: 01111 MDR: 00001010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (3 of 10)

PC -> MAR

Memory
Location 31

PC: IR:

00111 01001111
18: 01000111 15: 00001010

MAR: 00111 MDR: 00001010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (4 of 10)

MAR Accesses ocation 00111

Memory
Location 31

PC: IR:

00111 01001111
18: 01000111 15: 00001010

MAR: 00111 MDR: 00001010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (5 of 10)

Contents of 00111 -> MDR

Memory
Location 31

PC: IR:

00111 01001111
18: 01000111 15: 00001010

MAR: 00111 MDR: 10110010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (6 of 10)

MDR -> IR

Memory
Location 31

PC: IR:

00111 10110010
18: 01000111 15: 00001010

MAR: 00111 MDR: 10110010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (7 of 10)

IR [address] -> MAR

Memory
Location 31

PC: IR:

00111 10110010
18: 01000111 15: 00001010

MAR: 10010 MDR: 10110010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (8 of 10)

ocation 10010 [MAR] Accessed

Memory
Location 31

PC: IR:

00111 10110010
18: 01000111 15: 00001010

MAR: 10010 MDR: 10110010 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (9 of 10)

Contents of [10010] -> MDR

Memory
Location 31

PC: IR:

00111 10110010
18: 01000111 15: 00001010

MAR: 10010 MDR: 01000111 A: 00001010

07: 10110010 06: 01001111 Location 0

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Add Instruction: Sample (10 of 10)

IR [opcode] executed: A = A + MDR

Memory
Location 31

PC: IR:

00111 10110010
18: 01000111 15: 00001010

MAR: 10010 MDR: 01000111 A: 01010001

07: 10110010 06: 01001111 Location 0

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Computer Buses

PCI Express BUS Card Slots (from top to bottom: x4, x16, x1, 64 x16) compared to a traditional 32-bit PCI bus card slot.

Buses (1 of 3)
 Group

of electrical conductors (wires) for carrying signals from one location to another
Line: each conductor (or wire) in the bus

 The

physical connection that makes it possible to transfer data from one location in the computer system to another  4 kinds of signals
Data (alphanumeric, numerical, instructions) Addresses Control signals Power (sometimes)
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Buses (2 of 3)

bus Printer Mouse Keyboard Modem CP RAM Network card

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Ports

Disk controller Graphics card Sound card Monitor

Speakers

Buses (3 of 3) Connect CPU and Memory  I/O peripherals: on same bus as CPU/memory or separate bus  If connect CPU, Memory and I/O modules in the same Physical package, called backplane


Also called system bus or external bus Example of broadcast bus Common method of connecting CPU, Memory and I/O modules: to a printed circuit board called motherboard
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Motherboard

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Types of Buses (1 of 2)

Point-toPoint-to-point  When connect plug-in devices, called ports



Serial port

Modem

Control unit

ALU
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Types of Buses (2 of 2) Multipoint: Multipoint to connect several points together

Computer Computer

Computer

Computer

CPU Disk controller

Memory Video controller

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Point-to-point vs. Multipoint Point-to-

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Bus Interface
Bus interface bridges provide bridges: communication between different buses Special buses provide interconnections within the CPU chip Buses that form the backplane External CPU bus Peripheral control interface (PCI) bus Accelerated graphic processor (AGP) Industrial standard architecture (ISA)
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Typical bus and port connections

Bus interface bridges connect different bus types 73

Bus Characteristics


Protocol
Documented agreement for communication Specification that spells out the meaning of each line and each signal on each line

     

Throughput, Throughput i.e., data transfer rate in bits per second Data width in bits carried simultaneously Distance between two end points Type of signals unique/specialized or signals: shared Addressing capacity Etc. 74

Buses Inside a Computer

Data bus Address bus Control bus CPU I/O Module Memory
Motherboard
Many configurations possible

I/O Device

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Data Bus Carries data between the CPU and memory or I/O devices  Bi-directional


Data transferred out of the CPU for write operations Data transferred into the CPU for read operations

Typical sizes: 8, 16, 32, 64 lines  Signal names:



D0, D1, D2, D3, etc.

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Address Bus Carries an address from the CPU to Memory or I/O devices  Unidirectional


The address is always supplied by the CPU

(There is one exception to this, which well discuss later.)

Typical sizes: 16, 20, 24 lines  Signal names:



A0, A1, A2, A3, etc.

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Control Bus
    

Collection of signals for coordinating CPU activities Each signal has a unique purpose Typical sizes: 10-20 lines Signals are output, input, or bi-directional Typical signals
/RD (read) /WR (write CLK (clock) /IRQ (interrupt request) etc.

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PCI Bus Connections

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PCI Bus 32- or 64-bit backplane  Interconnects:



CPU Plug-in I/O (serial and parallel ports, sound cards, disc drives

Lines are non-specialized: carry addresses and data, labeled AD00 to AD31 (or AD63)  Additional lines: control and power lines 80


Instructions


Instruction
Direction given to a computer Causes electrical signals to be sent through specific circuits for processing

Instruction set
Design defines functions performed by the processor Differentiates computer architecture by the
Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes)

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Instruction Elements OPCODE: task  Source OPERAND(s)  Result OPERAND



Location of data (register, memory)

Explicit: included in instruction Implicit: default assumed
OPCODE Source OPERAND Result OPERAND
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Instruction Format
MachineMachine-specific template that specifies
  

Length of the op code Number of operands Length of operands

28 = 256 different instructions

Simple 32-bit Instruction Format

224 = 16 million memory addresses 83

Instruction Format: IBM Mainframe

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Instruction Types (1 of 2)


Data Transfer (load, store)

Most common, greatest flexibility Involve memory and registers Whats a word ? 16? 32? 64 bits?

Arithmetic
Operators + - / * ^ Integers and floating point

Logical or Boolean
Relational operators: > < = Boolean operators AND, OR, XOR, NOR, and NOT

Single operand manipulation instructions

Negating, decrementing, incrementing
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Instruction Types (2 of 2)


Privileged
Security Access control Not available to the application programs

     

Bit manipulation instructions

Flags to test for conditions

Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control

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Register Shifts and Rotates

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Program Control Instructions

Program control
Jump and branch Subroutine call and return

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Stack Instructions
St
IF It t

i
t r r

tr

ti
f r r i t i i i f r r r r ti r fr t ti i

Push

Pop
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Fixed Location Subroutine Return Address Storage

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Stack Subroutine Return Address Storage

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Multiple Data Instructions



Perform a single operation on multiple pieces of data simultaneously

SIMD: Single Instruction, Multiple Data Intel MMX: 57 multimedia instructions Commonly used in vector and array processing applications

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Thank you!
Reading: Lecture slides and notes, Chapter 7

http://www.visualjokes.com

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