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Table Of Contents

Computer unit Computer unit
Components of the CPU (1 of 2) Components of the CPU (1 of 2)
Components of the CU (2 of 2) Components of the CU (2 of 2)
Concept of Registers Concept of Registers
Registers: what they do Registers: what they do
Register Operations Register Operations
Program Counter ( PC ) Program Counter ( PC )
Instruction Register ( IR ) Instruction Register ( IR )
Accumulator Accumulator
Operation of Memory Operation of Memory
MAR and MDR MAR and MDR
Generic CPU With Registers Generic CPU With Registers
MAR MAR--MDR: Example MDR: Example
Individual Memory Cell Individual Memory Cell
Memory Capacity Memory Capacity
Memory Implementation Memory Implementation
RAM: Random Access Memory RAM: Random Access Memory
RAM: Sample RAM: Sample
ROM ROM --Read Only Memory Read Only Memory
ROM: Sample ROM: Sample
Memory Maps Memory Maps
Memory Map: Sample 1 Memory Map: Sample 1
Use of Memory Maps Use of Memory Maps
Memory Map: Sample 2 Memory Map: Sample 2
Memory Space: Exercise 1 Memory Space: Exercise 1
Memory Space: Exercise 2 Memory Space: Exercise 2
Fetch Fetch--Execute Cycle Execute Cycle
Fetch Fetch--part of the Cycle part of the Cycle
Load Instruction Load Instruction
Load Accumulator: Sample (1 of 12) Load Accumulator: Sample (1 of 12)
Load Accumulator: Sample (2 of 12) Load Accumulator: Sample (2 of 12)
Load Accumulator: Sample (3 of 12) Load Accumulator: Sample (3 of 12)
Load Accumulator: Sample (4 of 12) Load Accumulator: Sample (4 of 12)
Load Accumulator: Sample (7 of 12) Load Accumulator: Sample (7 of 12)
Load Accumulator: Sample (8 of 12) Load Accumulator: Sample (8 of 12)
Load Accumulator: Sample (9 of 12) Load Accumulator: Sample (9 of 12)
Load Accumulator: Sample (10 of 12) Load Accumulator: Sample (10 of 12)
Load Accumulator: Sample (11 of 12) Load Accumulator: Sample (11 of 12)
Load Accumulator: Sample (12 of 12) Load Accumulator: Sample (12 of 12)
Load Fetch/Execute Cycle Load Fetch/Execute Cycle
Store Fetch/Execute Cycle (1 of 2) Store Fetch/Execute Cycle (1 of 2)
Store Fetch/Execute Cycle (2 of 2) Store Fetch/Execute Cycle (2 of 2)
ADD Fetch/Execute Cycle ADD Fetch/Execute Cycle(1 of 2) (1 of 2)
ADD Fetch/Execute Cycle ADD Fetch/Execute Cycle(2 of 2) (2 of 2)
Add Instruction: Sample (1 of 10) Add Instruction: Sample (1 of 10)
Add Instruction: Sample (2 of 10) Add Instruction: Sample (2 of 10)
Add Instruction: Sample (3 of 10) Add Instruction: Sample (3 of 10)
Add Instruction: Sample (4 of 10) Add Instruction: Sample (4 of 10)
Add Instruction: Sample (5 of 10) Add Instruction: Sample (5 of 10)
Add Instruction: Sample (6 of 10) Add Instruction: Sample (6 of 10)
Add Instruction: Sample (7 of 10) Add Instruction: Sample (7 of 10)
Add Instruction: Sample (8 of 10) Add Instruction: Sample (8 of 10)
Add Instruction: Sample (9 of 10) Add Instruction: Sample (9 of 10)
Add Instruction: Sample (10 of 10) Add Instruction: Sample (10 of 10)
Computer Buses Computer Buses
Buses (1 of 3) Buses (1 of 3)
Buses (2 of 3) Buses (2 of 3)
Buses (3 of 3) Buses (3 of 3)
Motherboard Motherboard
Types of Buses (1 of 2) Types of Buses (1 of 2)
Types of Buses (2 of 2) Types of Buses (2 of 2)
Point Point--to
to--point vs. Multipoint point vs. Multipoint
Bus Interface Bus Interface
Typical bus and port connections Typical bus and port connections
Bus Characteristics Bus Characteristics
Buses Inside a Computer Buses Inside a Computer
Data Bus Data Bus
Address Bus Address Bus
Control Bus Control Bus
PCI Bus Connections PCI Bus Connections
PCI Bus PCI Bus
Instructions Instructions
Instruction InstructionElements Elements
Instruction Format Instruction Format
Instruction Format: IBM Mainframe Instruction Format: IBM Mainframe
Instruction Types (1 of 2) Instruction Types (1 of 2)
Instruction Types (2 of 2) Instruction Types (2 of 2)
Register Shifts and Rotates Register Shifts and Rotates
Program Control Instructions Program Control Instructions
Stack Instructions Stack Instructions
Fixed Location Subroutine Fixed Location Subroutine
Return Address Storage Return Address Storage
Stack Subroutine Return Address Stack Subroutine Return Address
Storage Storage
Multiple Data Instructions Multiple Data Instructions
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Lecture1000-6

Lecture1000-6

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Published by: rinkygoyal on Aug 11, 2011
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