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Table Of Contents

BAB I PENDAHULUAN
1.1 LATAR BELAKANG
1.2 PERUMUSAN MASALAH
1.3 BATASAN MASALAH
1.4 TUJUAN DAN MANFAAT
1.4.1 Tujuan Umum
1.4.2 Tujuan Khusus
1.5 METODOLOGI
1.6 SISTEMATIKA PEMBAHASAN
2.1 UMUM
2.2 DEFINISI-DEFINISI
2.3 OPERASI-OPERASI LOGIKA DASAR
2.3.1 Operasi INVERS
Tabel 2.1 Tabel opersai invers
2.3.2 Operasi AND
Tabel 2.2 Tabel opersai AND
2.3.3 Operasi OR
Tabel 2.3 Tabel opersai OR
2.3.4 Operasi NAND
Tabel 2.4 Tabel opersai NAND
2.3.5 Operasi NOR
2.3.6 Operasi XOR
Tabel 2.6 Tabel opersai XOR
2.3.7 Tabel Kebenaran
Tabel 2.7 Tabel kebenaran fungsi F = AB’C + ABC’
2.3 GERBANG-GERBANG LOGIKA (LOGIC GATES)
Gambar 2.1 Jenis-jenis gerbang logika dasar
Gambar 2.2 Gerbang AND 2 input
Gambar 2.3 Gerbang OR 2 input
Gambar 2.4 Gerbang NOT
Gambar 2.5 Gerbang NAND
Gambar 2.6 Gerbang NOR
Gambar 2.7 Gerbang XOR
2.4 ALJABAR BOOLEAN
Gambar 2.8 Rangkaian logika OR
Gambar 2.9 Rangkaian lengkap
Gambar 2.10 IC SN74LS00
2.6 Penyederhanaan fungsi Logika dengan K-MAP
Gambar 2.11 K-Map 3 variabel
Gambar 2.13 K-Map untuk POS 3 variabel
Tabel 2.8 Tabel kebenaran metode SOP
Tabel 2.9 Tabel kebenaran metode POS
Gambar 2.14 Rangkaian Kombinasionalnya
2.7 Aplikasi Rangkaian Kombinasional
2.7.1 HALF ADDER
Tabel 2.9 Tabel kebenaran Half Adder
Gambar 2.15 Rangkaian Half Adder
2.7.2 FULL ADDER
Tabel 2.10 Tabel kebenaran Full Adder
Tabel 2.11 Tabel K-Map Full Adder
Gambar 2.16 Rangkaian Full Adder
Gambar 2.17 Rangkaian Full Adder dari 2 Half Adder
Gambar 2.18 Blok Diagram Full Adder
2.7.3 MULTIPLEXER
Gambar 2.19 Symbol multiplexer
Gambar 2.20 Rangkaian Multiplexer 4 X 1
Tabel 2.11 Tabel kebenaran SOP
Gambar 2.22 Rangkaian multiplexer
2.7.4 DEMULTIPLEXER
Gambar 2.23 Simbol Demultiplexer
2.7.5 1 TO DEMULTIPLEXER
Gambar 2.24 Rangkaian 1 to 16 demultiplexer
2.7.6 Decoder
Gambar 2.25 Rangkaian 1 to 8 decoder
Tabel 2.12 Tabel kebenaran 1 to 8 decoder
Gambar 2.26 Dekoder 2 ke 4
Tabel 2.13 Tabel kebenaran decoder 2 ke 4
2.8 Aplikasi LanjutLogika Kombinasional
2.8.1 PLA (Programmable Logic Array)
Gambar 2.27 Blok diagram PLA
2.8.2 FPLA (Field Progamable Logic Array)
Gambar 2.28 FPLA yang mempunyai 3 input dan 4 output
2.8.3 PAL (Progammable Array Logic)
Gambar 2.29 PAL yang mempunyai 3 input dan 4 output
2.8.4 PROM (Progammable Read Only Memory)PROM
Gambar 2.30 PROM mempunyai 16 word (4 bit)
3.1 PENDAHULUAN
3.2 Desain pembuatan petunjuk praktikum
Gambar 3.1 Flowchart alur percobaan
Gambar 3.2 Pesan jika terjadi kesalahan
Gambar 3.3 Tampilan masukkan nama User
Gambar 3.4 Course overview
Gambar 3.5 Beberapa percobaan yang tersedia
4.1.1 TTL-AND
Tabel 4.1 Tabel kebenaran TTL-AND
Gambar 4.1 Rangkaian AND
Gambar 4.2 Jawaban dari pertanyaan di dalam Com3Lab
4.1.2 TTL-OR
Gambar 4.3 Rangkaian OR
4.1.3 TTL-NOT
Gambar 4.5 Rangkaian NOT
Gambar 4.6 Jawaban dari pertanyaan di dalam Com3Lab
4.1.4 TTL-XOR
Gambar 4.8 Jawaban dari pertanyaan di dalam Com3Lab
4.2 Logic Operations
Tabel 4.2 Tabel fungsi Q = 0
Tabel 4.3 Tabel fungsi Q = A /\ B
4.2.1 De morgan’s law
Gambar 4.9 Rangkaian De morgan’ law
4.2.2 TTL-NAND
Gambar 4.10 Rangkaian NAND
4.2.3 Assosiative Law
Gambar 4.11 Rangkaian Assosiative Law
4.2.4 Distributive Law
Gambar 4.12 Rangkaian Distributive
4.3 K.V Diagram
4.7 Full Adder
4.8 Multiplexer
4.9 Demultiplexer
5.1 Analisa pada lembar Supervisor
Gambar 4.22 Tampilan grafik Com3Lab Supervisor
Gambar 4.23 Tampilan grafik Com3Lab Supervisor
Gambar 4.24 Tampilan grafik Com3Lab Supervisor
5.2 Analisa
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Published by Nurafiah Noe

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Published by: Nurafiah Noe on Aug 15, 2011
Copyright:Attribution Non-commercial

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