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Table Of Contents

1.1. Product List
1.2. Packaging Information
1.3. PIN DESCRIPTION
1.4. Block Diagram
1.5. Array Organization
1.6. Addressing
1.7. Command Set
1.8. Mode Selection
1.9. Bad Block Management
1.10. Bad Block Replacement
2.1. Valid Blocks
2.2. Absolute Maximum Rating
2.3. DC and Operating Characteristics
2.4. AC Test Conditions
2.5. Pin Capacitance (TA=25°C, F=1.0㎒)
2.6. Program/ Read / Erase Characteristics
2.7. AC Timing Characteristics
2.8. Status Register Coding
2.9. Device Identifier Coding
2.10.1. 3rd
2.10.2. 4th
2.10.3. 5th
2.10.4. 6th
3.1. Command Latch Cycle Timings
3.2. Address Latch Cycle Timings
3.3. Input Data Latch Cycle Timings
3.4. Data Output Cycle Timings (CLE=L, WE#=H, ALE=L, WP#=H)
3.5. Data Output Cycle Timings (EDO type, CLE=L, WE#=H, ALE=L)
3.6. Read Status Cycle Timings
3.7. Multi Plane Read Status Timings
3.8. Page Read Operation Timings (Read One Page)
3.9. Page Read Operation Timings (Intercepted by CE#)
3.10. Page Read Operation Timings with CE# don't care
3.11. Random Data Output Timings
3.13. Cache Read Operation Timings
3.14. Multi Plane Cache Read Operation Timings
3.15. Read ID Operation Timings
3.16. Page Program Operation Timings
3.17. Page Program Operation Timings with CE# don't care
3.18. Random Data Input Timings
3.19. Multi Plane Page Program Operation Timings
3.20. Copy-Back Program Operation Timings with Random Date Input
3.21. Cache Program Operation Timings
3.22. Multi Plane Cache Program Operation Timings
3.23. Block Erase Operation Timings
3.24. Multi Plane Erase Operation Timings
3.25. Reset Timings
4.1. Page Read
4.2. Cache Read (available only within a block)
4.3. Multi Plane Page Read
4.4. Multi Plane Cache Read (available only within a block)
4.5. Read ID
4.6. Read Status Register
4.7. Page Program
4.8. Multi Plane Program
4.9. Cache Program (available only within a block)
4.10. Multi Plane Cache Program (available only within a block)
4.11. Copy-Back Program
4.12. Multi Plane Copy-Back Program
4.13. Block Erase
4.14. Multi Plane Block Erase
4.15. Reset
5.1. Interleaved Page Read
5.2. Interleaved Multi Plane Page Read
5.3. Interleaved Page Program
5.4. Interleaved Multi Plane Page Program
5.5. Interleaved Block Erase
5.6. Interleaved Multi Plane Block Erase
6.1. Data Protection & Power on/off Sequence
6.2. Ready / Busy
6.3. Write Protect Operation
7.1. Paired Page Address Information
7.2. Extra Block Description
7.3. Acceptable Command after 80h
7.4. Acceptable Command between Start command and Confirm command
7.5. Restriction of Read Status Value in Multi Plane Operation
7.6. Page Program Failure
7.7. Restriction Multi Plane Operation
8: Bit Organiztion
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H27UBG8T2A

H27UBG8T2A

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Published by kvladg

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Published by: kvladg on Aug 17, 2011
Copyright:Attribution Non-commercial

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11/05/2012

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