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Table Of Contents

2.2Manufacturer benefits
2.3IC designer benefits
3.2SDA and SCL logic levels
3.4START and STOP conditions
3.6Acknowledge (ACK) and Not Acknowledge (NACK)
3.10The slave address and R/W bit
4.Other uses of the I2
4.2SMBus - System Management Bus
4.2.3Differences between SMBus1.0 and SMBus2.0
4.3PMBus - Power Management Bus
4.4Intelligent Platform Management Interface (IPMI)
4.5Advanced Telecom Computing Architecture (ATCA)
5.3.2Serial data format in Hs-mode
5.3.3Switching from F/S-mode to Hs-mode and back
5.3.4Hs-mode devices at lower speed modes
5.3.5Mixed speed modes on one serial bus system
5.3.6Standard, Fast-mode and Fast-mode Plus transfer in a mixed-speed bus system
5.3.7Hs-mode transfer in a mixed-speed bus system
5.3.8Timing requirements for the bridge in a mixed-speed bus system
6.Electrical specifications and timing for I/O stages and bus lines
6.1Standard-, Fast-, and Fast-mode Plus devices
7.Electrical connections of I2
7.1Pull-up resistor sizing
7.2Operating above the maximum allowable bus capacitance
7.2.1Reduced fSCL
7.2.3Bus buffers, multiplexers and switches
7.2.4Switched pull-up circuit
7.3Series protection resistors
7.5Wiring pattern of the bus lines
10 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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I2C Specification V3.0

I2C Specification V3.0

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Published by: All4Uyen on Aug 17, 2011
Copyright:Attribution Non-commercial


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