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Table Of Contents

Introduction
1. References
2. Scope
3. Definitions and acronyms
4. Introduction to HDL Defined Integrated Circuits
5. ASIC Design Flow
6. Introduction on Safety Requirements and ASIC design
6.1. Introducing discussion
6.2. Generally about failure models
6.2.1. Systematic failures
6.2.2. Random hardware failures
6.2.2.1. Transient hardware faults
6.2.2.2. Intermittent hardware faults
6.2.2.3. Permanent hardware faults
6.3. Brief description of basic principles of redundancy
6.3.1. Hardware redundancy
6.3.2. Software redundancy
6.3.3. Information redundancy
6.3.4. Time redundancy
6.3.5. Diversification
6.4. Diagnostics
7. System design
7.1. Documentation process
7.1.1. Introduction
7.1.2. Design documentation
7.1.2.1. Objectives
7.1.2.2. General
7.1.3. Documentation requirements
7.1.3.1. Definition phase
7.1.3.2. Architectural design
7.1.3.3. Detailed Design
7.1.3.4. Layout
7.1.3.5. Prototype implementation
7.1.3.6. Design validation and release
7.1.4. Management documentation
7.1.4.1. Objectives
7.1.4.2. General
7.1.4.3. Requirements
7.1.5. Management of functional safety
7.2. Design process
7.2.1. Definition Phase
7.2.1.1. General Hardware requirements
7.2.1.2. General ASIC design requirements
7.2.2. Architectural Design
7.2.2.1. Requirements on the architectural design
7.2.2.2. Requirements on the probability of hardware failures
7.2.2.3. Requirements on verification and validation planning and initiation
7.2.2.4. Requirements on the architectural HDL modeling and test bench design
7.2.3. Detailed Design
7.2.4. ASIC Layout design
7.2.5. Implementation
7.2.5.1. ASIC implementation
7.2.5.2. System implementation
8. System Verification and safety validation
8.1. Requirements on system verification
8.1.1. Formal verification methods
8.1.2. Dynamic verification methods
8.1.3. Detailed verification plan
8.2. Requirements on documentation
8.2.1. Architectural design
8.2.2. Detailed design
8.2.3. Layout design
8.3. Requirements on safety validation
8.3.1. Requirements on E/E/PES safety validation
8.3.2. E/E/PES Modification
8.4. Methods for static analysis
8.4.1. FBA (Functional Block Analysis)
8.4.2. DFA (Data flow Analysis)
8.4.3. SSA (Signal Sequence Analysis)
8.4.4. STDA (State transition Diagram Analysis)
8.4.5. FMEA (Failure modes and Effects Analysis)
8.4.5.4. FMEA worksheet
8.5. Methods for dynamic analysis
8.5.1. Simulation/Test benches
8.5.2. ASIC Emulation
8.5.3. Fault injection
8.5.3.1. Design
8.5.3.2. Saboteurs
8.5.3.3. Environmental influences
8.6. Methods for reliability analysis
8.6.1. Reliability Block Diagram (RBD)
8.6.1.1. RBD model evaluation
8.6.2. Fault Tree Analysis
8.6.3. Markov chain modeling
8.6.4. Availability Analysis
8.7. Methods for validation of the design process and the verification process
8.7.1. Design review and inspections
8.7.1.1. Walkthroughs (system design review)
8.7.1.2. Inspection (reviews and analysis)
8.7.1.3. Fagan inspections
8.7.1.4. Checklists
8.7.2. Documentation system
8.7.2.1. Examination of documentation completeness
8.7.2.2. Examination of the system specification
8.8. E/E/PES Hardware Safety Validation performance
9. Conclusion
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50368707 Design Safety Validation With HDL

50368707 Design Safety Validation With HDL

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Published by: 최재호 on Aug 24, 2011
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10/31/2011

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