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. . (
) . ( ) OR,AND,XOR
( : )
. .
.
) (Control Unit
) (Instruction Register
) .(RAM .
Main Memory
Arithmetic and Logic Unit
STATUS REGISTER
1 -4
-:
-1
Floating Point
-2
-3
:
(
( & 2.5516 & 2.336
108
.
.
.
486 ( ) SX486
(
386 Math co-processor
) ( )
.
:
( )
.
.
:
: Carry bit .
: Zero bit .
: Positive bit . - : Negative bit .
:
.
(
)
.
.
( " ")
109
32
.
** Register
-:
- 1 :
-2 :
-3 : Status Register
:
) (registers
.
AX
Accumulator
BX
Base
register
CX
Counting
register
( )
.
(
AX
( )
.
110
DX
Data register
DI
Destiny
Index
register
SI
Source
Index
register
BP
Base
Pointers
register
SP
Battery
pointer
register
( ) :
Overflow
I/O Bus
.
( )
( )
( )
BX
.
( )
.
.
8086
IP
. Flags
.
. .
111
.
.
:
2 -4
Floating Point:
.
mantissa .exponent
:
(
)
( ) 125 :
( ( E
112
M EP
.(Mantissa
Mantissa
)or Fraction
M
Exponent Sign
Exponent
E .
P () ).(Exponent or Characteristic
113
Sign
.
.
( ) 110.110 :
.110110 23
) (Word
.
:
314,600,000 and 0.0000451 : :
3146E5 and 451E-7
3 -4
:
. :
.
.1
.2
.3
.
.5 .
.
.6
.
.7
. .
114
.
.
.4 CPU
.
.
.8 .
"".
1 -3 -4 .
-1 .
-2 .
-3 .
-4 .
-5 .
***
:
.1 Input Mode .
.2 Output Mode .
.3 . Beginning new Operation
.4 .Memory Read
.5 .Memory Write
.6 .Instruction Fetch
.7 .I/O Read
.8 .I/O Write
2-3-4 .
:
115
Operation Code
Operands Address
M = 2
** .. .
:
** .
( - ).
Program Counter
. Instruction Register
.
( ):
( CPU )
.
:
( ) instruction fetch
.1 (
. RAM .CPU
* .
*
. .
.
116
.
* .
*
.
1 .
.2 :
:
*
* .
*
( ).
.
* ( ) : Instruction Decoder
8
256
..
.
( )
.
117
: .
-:
.
( )pointer instruction ( )instruction fetch
( )decoder instruction
( .)
( )ALU
MS
Word
.
MHz - 700 MHz - 600
3- 3- 4 pipelined
.
. ( system
.)clock
.
.
( )
.
()pipelining
118
50
50
50
.
( ) stages
pipelining
( ) MMX 6
14
( ) .
119
.
:
) .
.
:
.
..
!!! pipelining
.
120
.1
.2
.3
.4
.5
.6
.7
.8
.
.
.
-9
()
( )
() 30.85
() 3085E2 3085E-2 308510-2
()
( )
()
( - )
()
( )
-10
() (
() 1
121
()
() ( OR,AND,XOR
(
-11 :
( AX ) (- ( - )CX ) DI
12
- 13
()
()
()
( )
122
).