Array subsystem

Chip Functions

ata path Operators Memory Elements Control Structures

Special Purpose Cells

Trade off factors:

Speed, Density, Programmability,

I/O Power Distributio Clock Generation Analog

Array : Repetition of basic cell in two dimensions . A cell is carefully optimized to provide very high density. Many a times due to high density problems, full o/p voltage swings are not available at various nodes. The periphery circuit is used to restore it to nodes to full logic levels. Types of Arrays: 1 Logic - PLAs 2. Storage Memory. In a CMOS SOC , memory arrays are responsible for majority transistors. Study of memory involves: Issues of cell design, Decoding, Column circuit design etc.

SRAM / DRAM
RW Address M/ RO contains a M R Accesse AM AM data that C d with matches a address. specific MEMORY Has key. latency MROM indepen dent of PROM address. SAM Addressed sequentially. Does EPROM not need any SIPO / PISO EEPROM Shift reg / address. Queues FIFO /LIFO Flash

SRAM
Use flip-flops. Use f/b to maintain their state. Faster and less troublesome.

DRAM
Use charge storage in a parasitic capacitor . Use charge stored on a floating capacitor through an access transistor. Charge leaks thru access transistor even while transistor is off.

Requires more area per bit Hence they need a than DRAMs periodical read and rewritten to refresh their state.

Mask ROM PROM

Hardwired during fabrication. Cannot be changed. Can be programmed once after fabrication by blowing on chip fuses with a special high programming voltage.

EPROM Is programmed by storing charge on a floating gate. It can be erased by exposure to use light for several minutes to knock the charge off the gate. Then EPROM can be reprogrammed. EEPRO Can be erased in microsecond with on chip M circuitry. Flash Variant of EEPROM Erases entire blocks instead of individual bits. Erase circuitry is shared among larger blocks. So, area per bit is reduced. Hence high density and ease of reprogram ability in the system is

Read access time: Time it takes to retrieve from the memory. It is the time difference between read request and the moment at which data is available at the output. Write access time: Time elapsed between a write request and the final writing of the input data into the memory. Read / Write cycle time: Minimum time required between successive reads and writes. This is normally greater than the access time . Read / Write cycles need not have same time. But for simplicity of system design, they are considered to be same.

Timing parameters
READ cycle READ
Read access

Read access

WRITE cycle

WRITE

DATA

Data Valid

Write access

Data written

Typical signals and buses in an RWM chip.

Input data bus
N

Chip select

Address bus
N

MXN Memory M=2k

Read/write

Output data bus

Memory Architecture for N Word Memory (Intuitive)

M bits
S0

Word 0 Word 1 Word 2

One word at a time is selected for reading / writing. Since this is a single port memory, only one signal Si can be high at a time. N select bits are needed. Simple but works for very small memory. For large memory, no. of select lines increases. These select lines are provided on

S1 S2

N words

SN-2 SN-1

Word N-2 Word N-1

I/p - O/p M

No. of select signals are reduced. N = 2k select bits are needed. One of which at a time is active for reading / writing. Decoder is designed to have a size matching to that of a storage cell.. For large memory, no. of select lines decreases and large routing channels are not required. Wiring /packaging problems can be eliminated. Does not address memory aspect ratio problem.(220 /23
A0 A1

(Using M bits Decoder)

S0

Word 0 Word 1

Decoder
(Reduces the no. of Address bits)

Word 2

A k-1

K= log2N

Word N-2 Word N-1

I/p - O/p M

Structured Memory Organizatio n Equal vertical and

horizontal dimensions. Multiple words are stored in a single row and are selected simultaneously. To route correct word, a column decoder is used. Address part is

Bit Line

2L-k

Ak

A k+1

Row Decoder

Word Line

A L-1

M-2k

Sense amp / driver

A0

Column decoder
I/p - O/p M

Ak1

 Word Line: Horizontal select line that enables single row of cells. Bit Line: Wire that connect cells in single column to I/P O/P circuitry. Design metrics: Area, Noise margin, Logic swing, I/p O/p isolation, Fan out and Speed.

Design Techniques
Propagation delay and power consumption can be reduced by reducing voltage swing substantially below supply lines. Within an array, careful control of crosstalk and other disturbances is possible ensuring sufficient noise margin even for small voltage swings. Sense amplifiers amplify the internal swing to full rail to rail swing amplitude so as to communicate with the external world.

Static and Dynamic RAMs

RAMs come in two varieties, static and dynamic. However, the combination of a static RAM cache and a dynamic RAM main memory attempts to combine the good properties of each.

SRAM Cell
A typical SRAM cell uses Six transistors, connected in such a way as to create a regenerative feedback. In comparison with the DRAM, the information held is stable and requires no clocking or refresh cycles to sustain it. Static RAMs are much faster compared to dynamic RAMs. Typical access time is in the order of few nanoseconds. For this reason ,SRAMs are popular as level 2 cache memory.

DRAM Cell
A dynamic RAM is an array of cells, each cell containing one transistor and a tiny capacitor. The capacitors can be charged or discharged, allowing 0s and 1s to be stored. Because the electric charge tends to leak out, each bit in a dynamic RAM must be refreshed every few milliseconds to prevent the data from leaking away. Because external logic must take care of the refreshing, dynamic RAMs require more complex interfacing than static ones. They have larger capacities. Since dynamic RAMs need only one transistor and one capacitor per bit, they can have a very high packing density. For this reason, main memories are nearly always built out of dynamic RAMs. However, DRAMs are generally slow with the delay in the order of tens of nanoseconds.

The memory circuit is said to be static if the stored data can be retained, without any need for periodic refresh operation. The data storage cell is the one bit memory cell in the static RAM arrays. Consists of a simple latch circuit with two stable operating points. Depending on the preserved state of the two inverter latch circuit, the data being held in the memory cell will be interpreted either as logic 0 or as logic1. To access the data contained in the memory cell via a bit line, we need at least one switch( a pass transistor), which is controlled by the corresponding wordline as shown in Figure .

SRAM Cell

BL

The memory cell consist of a simple CMOS inverters connected back to back , and two access transistors . The access transistors are turned on whenever a wordline is activated for read or write operation, connecting the cell to the complementary bitline columns.

Cell uses single wordline and both true and complementary bitlines. Word line decides read or write operation. Compactness is achieved by employing more complex peripheral circuitry for reading and writing. The most important advantage of this circuit topology is that the static power dissipation is very small due to small size and short wires; which lead to small leakage current. Other advantages of this design are high noise immunity due to larger margins, high packaging densities and the ability to operate at lower power supply voltage.

CMOS SRAM cell with precharge Transistor

M2

M4

M5

M6 M1 M3

BIT

We have to take into account , the relatively large parasitic column capacitance Cbit and Cbitbar and column pull up transistors. When none of the word lines is selected, the pass transistors M5, M6 are turned off and the data is retained in all memory cells. The column capacitances are charged by the pull up transistors P1 and P2. The voltages across the column capacitors reach VDD-VT.

 The two basic requirements, which dictate W/L ratios are i) The data read operation should not destroy the stored information in the cell. ii) The cell should allow stored information modification during write operation.

Two phase operation: Phase II- SRAM is precharged. Phase I written or read by raising appropriate wordline and either driving bitlines to the value that is to be written or leaving bitlines floating and observing which one is pulled down. Erroneous triggering can also be prevented by precharging the bitlines to another value like VDD/2. In such case, Q does not reach the switching threshold of inverter. It also limits voltage swing on the bitlines and thus reduces the power dissipation.

 Charge storage in MOSFET parasitic capacitances is used for temporary storage of data in dynamic RAMs. However because of gate leakage currents the charge must be restored at periodic intervals for long time storage. Usually, data refresh is carried out once every 2 ms using support circuitry. Due to inherent discharging, read out may be destructive. Hence every read operation must be followed with a write operation. It offers high density, low power dissipation and reduced complexity. Hence for large sized memories, ( above 1 MB) DRAMs are preferred over SRAMs.

DRAM Cell

4T DRAM cell
Same as generic static RAM cell. Charge is stored at the gate node of Q1 or Q2 during high level of clock. When the clock goes low, the charge leaks through the R. B. drainsubstrate junction. Since the leakage rate is low (discharging current of the order of few pA) logic state of the latch is held for a short time. Activating the clock for a microsecond after approx. every 2ms restores the lost charge.

 If Q1 is ON, V1=VT and Q2 is off, V2=0. As C1 loses charge through Q1, clock is turned high. So, QR1, LX1, QR2 and LX2 are turned ON.Q1 conducts and holds V2=0.V1 is thus restored and V2 remains unchanged. For writing, Databar line is taken to appropriate data, RAS, CAS are high.R/W is taken to high. For reading, R/W is taken low, CAS, RAS are taken high. The voltage across C1 is then available at Dout via LX2, QC2 and Q0. To avoid excessive discharge, C1 is large as compared to data line capacitance.

3T DRAM cell

Offers nondestructive reading by separating read and write operations. To read the cell, Doutbar is made high and read line is also taken high. If C is charged initially, Doutbar will go low, and vice versa. A 0 in Din makes capacitor discharge when Write signal is high. A 1 in Din makes capacitor charge when Write signal is high.

1T DRAM cell

Further reduction in no. of active devices. High packaging density and speed. Parasitic capacitor is accessed via Q for reading and writing. To write the cell, row line is raised while Data line is low or high .Then, C is charged or discharged to the value on the bitline. Stored cell value is transferred to dataline by taking Row line high and floating the Dataline.