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EEE 357 Home Work

# EEE 357 Home Work

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09/01/2011

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1
Prime University
Facul
ty of EngineeringDep
a
rtment of E
l
e
c
tri
cal

a
nd E
l
e
c
troni
c
Engineering
Course Conducted by: Shuvodip Das
Co
u
rse Tit
l
e: Digit
al
E
l
e
c
troni
c
sCo
u
rse Code: EEE 357Seq
u
enti
al
System
Seq
u
enti
al
System:
In digital circuit theory,
seq
u
enti
al

l
ogi
c
is a type of logic circuit whose output depends not only on the present input but also on the history of the input. This is in contrast to
combinational logic
, whose output is a function of, and onlyof, the present input. In other words, sequential logic has
state
(
memory
) while combinational logic does not.Difference between Combinational and Sequential Logic Circuit?Sequential Logic can be divided as ± a)

Synchronous Sequential Logic and b)

Asynchronous Sequential Logic.
Syn
ch
rono
u
s seq
u
enti
al

l
ogi
c

N
early all sequential logic today is 'clocked' or 'synchronous' logic: there is a 'clock' signal, and all internalmemory (the 'internal state') changes only on a clock edge. The basic storage element in sequential logic isthe flip-flop.The main advantage of synchronous logic is its simplicity. Every operation in the circuit must be completedinside a fixed interval of time between two clock pulses, called a 'clock cycle'.
Asyn
ch
rono
u
s seq
u
enti
al

l
ogi
c

Asynchronous sequential logic expresses memorizing effect by fixing moments of time, when digital devicechanges its state. These moments are represented not in explicit form, but taking into account principle³before/after´ in temporal relations of logical values.For asynchronous logic it is sufficient to determine a sequence of switchings irrespective of any connectionsof the corresponding moments with real or virtual time.
Ex
a
mp
l
e of Seq
u
enti
al
Logi
c
Cir
cu
it:
Flip-Flop, Counter, Register etc.
Fl
ip-
Fl
op:
In electronics, a
l
ip-f
l
op
or
la
t
ch
is a circuit that has two stable states and can be used to store stateinformation. The circuit can be made to change state by signals applied to one or more control inputs andwill have one or two outputs. Flip-flops and latches are a fundamental building block of digital electronicssystems used in computers, communications, and many other types of systems.

2
F
lilltttlt

¡
h

i
ma
il
used for s
t
orage e
l
emen
t
s,wh
il
e c
l
ocked dev
i
ces are descr
i
ed as
flip-fl
¢
p
£
.
S
i
le
S_R
(set-reset) ltes:
SR NOR latch
An
¤

l
a
t
ch, cons
t
ruc
t
ed from a pa
i
r of cross-coup
l
ed
¥
O
ga
t
es
When us
i
ng s
t
a
ti
c ga
t
es as bu
il
d
i
ng b
l
ocks,
t
he mos
t
fundamen
t
a
l

l
a
t
ch
i
s
t
he s
i
mp
l
e
SR
¦
§
h
, where S and
s
t
and for
and
. I
t
can be cons
t
ruc
t
ed from a pa
i
r of cross-coup
l
ed O

l
og
i
c ga
t
es. The s
t
ored b
it

i
s presen
t
on
t
he ou
t
pu
t
marked Q.
SR NAND latch
An S

l
a
t
ch, cons
t
ruc
t
ed from a pa
i
r of cross-coup
l
ed

A

D ga
t
es
Th
i
s
i
s an a
lt
erna
t
e mode
l
of
t
he s
i
mp
l
e S

l
a
t
ch bu
ilt
w
it
h A

D
l
og
i
c ga
t
es.
Se
and

ese
now becomeac
ti
ve
l
ow s
i
gna
l
s, deno
t
ed S and
respec
ti
ve
l
. O
t
herw
i
se, opera
ti
on
i
s
i
den
ti
ca
l

t
o
t
ha
t
of
t
he S

l
a
t
ch.
-

lt opert
i
on

R

Ac
t
i
on
0 0
es
t
i
c
t
ed comb
i
na
ti
on0 1 Q=11 0 Q=01 1 o
C
hangeSymbo
l
of
-
R
La
t
ch
S

Q


Q
b
0 0

o
C
hange

o
C
hange0 1 0 11 0 1 01 1 Inva
li
d Inva
li
d

3

Leve
l
Triggered R-S
Fl
ip-
Fl
op/ C
l
o
ck
ed R-S
Fl
ip-
Fl
op:
The clocked RS
N
A
N
D latch is shown below.The clocked RS latch circuit is very similar in operationto the basic. The S and R inputs are normally at logic 0,and must be changed to logic 1 to change the state of thelatch. However, with the third input, a new factor has been added. This input is typically designated
or
CLK
, because it is typically controlled by a clock circuit of some sort, which is used to synchronize several of theslatch circuits with each other. The output can onlychange state while the CLK input is a logic 1. WhenCLK is a logic 0, the S and R inputs will have no effect.
C
l
o
ck
Sign
al
:
In electronics and especially synchronous digital circuits, a
cl
o
ck
sign
al
is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits.Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge.In digital circuit, clock pulse can be expressed as CLK, CK or CP.Clock is of two types. a) Level Triggered Clock Pulse and b) Edge Triggered Clock Pulse.a)

Leve
l
Triggered C
l
o
ck
P
ul
se:

In level triggered clock pulse, for bit 1 and 0 the output of the devicechanges . If the output changes due to bit ³1´ then its called positive triggering or positive clocking. If outputchanges due to ³0´ then its called negative triggering.
b)

Edge Triggering C
l
o
ck
P
ul
se:
Positive Edge Triggering:
This type of triggering is used for flip flops that are to respond during the LOW to HIGH transition state of aclock pulse. It is mainly identified from the clock input lead along with a triangle.Positive Edge Triggering
N
egative Edge Triggering
4.
Neg
a
tive Edge Triggering
This type of triggering is used for flip flops that are to respond during the HIGH to LOW transition state of aclock pulse. It is mainly identified from the clock input lead along with a low-state indicator and a triangle.