Miller Opamp Design

Chris Haji-Michael
www.sunshadow.co.uk/chris.htm
This sheet is used to design a low speed Miller Operational Amplifier, using the technique explained by Willy
Sansen in his book "Analog Design Essentials" chapters 1 and 6, main slide 0629.
PMOS input devices are chosen as these normally have better matching and lower noise. There is a good
explanation of why this is generally better in Analog integrated Circuit Design, Johns, Martin, page 232
Cc in the following schematic is replaced with Cc and Rc in series.
Design Inputs yellow; BSIM inputs blue; outputs green
m
m
10
6
:
kohm 1000 ohm :
q 1.60217733 10
19
coul :
k
b
1.380658 10
23

joule
K
:
T 270K :
e
ox
8.8542 10
12
3.9
F
m
:
The starting point of the analysis
focuses on this graph, which shows the
EKV model and gives i the inversion
coefficient for Vgs-Vt.
The EKV model allows a single equation
to be used for both the striong inversion
and weak inversion operating zones on
the FET.
This model allows Vgs-Vt (Vgt) to be
negative and typically vary from -0.2 to
0.5V. It is unusualy positive, otherwise
the ROUT is too low and we get no gain.
STEP 1. Design requirements in yellow. Blue are the BSIM3 MOS parameters.
CL = a Cc, Cc = Cgs6, F6 = ? GBW
Normally these are 2 3 2
TOX 510
9
m : U0
n
388
cm
2
V s
: UA
n
6.5 10
9

m
V
: UB
n
4.2 10
18

m
2
V
2
:
NFACTOR
n
1.14 : VTH0
n
0.633V : VSAT
n
86301
m
s
:
U0
p
139
cm
2
V s
: UA
p
1.399 10
9

m
V
: UB
p
1.0 10
19

m
2
V
2
:
NFACTOR
p
1.54 :
VTH0
p
0.673V : VSAT
p
103503
m
s
:
STEP 2. From U0 and the other BSIM mobility parameters, calculate the mobility for the NMOS and the PMOS
devices as this changes with Vgt. The equations for this are from W Liu "Mosfet Models for Spice Simulation",
page 249. Assume MOBMOD=1 which is the default.

n
Vgt ( )
U0
n
1 UA
n
Vgt 2 VTH0
n
+
TOX
+ UB
n
Vgt 2 VTH0
n
+
TOX

,
2
+
:

p
Vgt ( )
U0
p
1 UA
p
Vgt 2 VTH0
p
+
TOX
+ UB
p
Vgt 2 VTH0
p
+
TOX

,
2
+
:
0.2 0.1 0 0.1 0.2
80
100
120
140
160

n
Vgt ( )
cm
2
Vs

p
Vgt ( )
cm
2
Vs
Vgt

n
Vgt6 ( ) 118.769
cm
2
V s

This shows how the mobility
changes with Vgt for both the
NMOS and PMOS
It is 50% higher for the NMOS
STEP 3. Calculate FT (frequency at which gain equals 1) for transistor M6 to get the gain-bandwidth. From this
we can calculate L (Gate Length) and we use this same L for most of the transistors. The EKV model is used
here, as this is what Samson uses, refer slides: 0138, 0140, 0165, 0627. The gate length needs to be at least
twice the minimum.
V
GSTtn
2 NFACTOR
n

k
b
T
q
: 0138 0138
i Vgt ( ) ln e
Vgt
V
GSTtn

,
1 +

1
1
]

1
1
]
2
:
GM Vgt ( )
1 e
i Vgt ( )

i Vgt ( )
: 0140 F
T
a ? 1
1

,
GBW : 0627
0165
L
n
Vgt F
T
, ( )

n
Vgt ( )
k
b
T
q

p F
T

i Vgt ( ) 1 e
i Vgt ( )

_
,

1
]
:
V
GSTtn
0.053 V i Vgt6 ( ) 14.386
L
n
Vgt6 F
T
, ( ) 0.824 m F
T
480 MHz
2 10
8
3 10
8
4 10
8
5 10
8
6 10
8
7 10
8
8 10
8

6 10
7

7.333 10
7

8.667 10
7

1 10
6

1.133 10
6

1.267 10
6

1.4 10
6

L
n
0.2V FT , ( )
FT
This graph shows how the length of
the gate influences the FT (the
frequency at which the gain is 1)
0.2 0.1 0 0.1 0.2
0
0.2
0.4
0.6
0.8
1
L
n
Vgt F
T
, ( )
m
Vgt
We also get this strange graph that
shows how the required gate length
changes with Vgt.
STEP 4. Use the following equations to calculate the widths and currents of M6 and M5, which are dependent
on CL.
C
c
C
L
a
: C
gs6
C
L
a
: 0621 C
ox
e
ox
TOX
: W
6
C
gs6
3
2

1
L
n
Vgt6 F
T
, ( ) C
ox

: 0161
I
DSt6

n
Vgt6 ( ) C
ox

W
6
L
n
Vgt6 F
T
, ( )
V
GSTtn
( )
2
: 0138
I
DS6
I
DSt6
ln 1 e
ln e
i Vgt6 ( )
1
( )
+

_
,

_
,
:
I
DSt6
8.199 A C
c
0.333 pF
g
m6
GM Vgt6 ( ) I
DS6
2
V
GSTtn
: 0141
g
m6
0.302
mA
V

I
DS6
31.099 A W
6
29.278 m
STEP 5. We need the Early voltage for M6 so that we can calculate the output resistance to get the voltage
gain. From this we can convert Cc to the equivalent input capacitance from the Miller equation. W Liu "Mosfet
Models for Spice Simulation", equations A-62, A-78. The equivalent Early voltage is VA and this converts to
the ro6 by the slope at the point of operation. The output impedance is halved as M5 needs to be considered and is
assumed to be equal to rout of M6. Also a 1/2 adjustment is made for ro, as we are working near VTH0 and ro is
reduced.
e
sat6
2 VSAT
n

n
Vgt6 ( )
: VA6 e
sat6
L
n
Vgt6 F
T
, ( ) : ro6
1
2
VA6 VTH0
n
+ Vgt6 +
I
DS6

,
: ro5 ro6 :
Vgain6 g
m6
ro6
2
: C
n1
C
gs6
1 Vgain6 + ( ) C
c
+ : ro6 2.06 10
5
ohm VA6 11.979 V
C
n1
10.818 pF Vgain6 31.119
Vgain6_dB 10 log Vgain6 ( ) :
Vgain6_dB 14.93
STEP 6. Now scale M1 and M2. Keep Vgt1 low to minimise noise. B needs to be high to save current, but
recommend this is kept at 1. L needs to be greater than twice the process minimum.
g
m1
2 p C
n1
GBW : 063 I
DS1
I
DS6
2 B
: GM1
g
m1
I
DS1
NFACTOR
p

k
b
T
q
: 0141
i 1 : Given GM1
1 e
i

i
= i Find GM1 ( ) :
0165
and 065 for FT V
GSTtp
2 NFACTOR
p

k
b
T
q
: L
p

p
Vgt1 ( )
k
b
T
q

p
F
T
4

i 1 e
i

_
,

1
]
:
L
p
0.515 m
W
1
I
DS1
i
L
p

p
Vgt1 ( ) C
ox
V
GSTtp
( )
2

1
]

: 0138
W
4
W
6
2
1
B
:
g
m1
1.359
mA
V

W
1
36.276 m
STEP 7. Calculate the voltage gain for stage 1 and then calculate the overall voltage gain. The output
resistance is the Early voltage divided by the current. This is halved because both there are two FETS and the
gain is halved again as we are working near VTH0 and the output resistance is slightly lower at this point.
e
sat1
2 VSAT
p

p
Vgt1 ( )
: VA1 e
sat1
L
p
: ro1
1
2
VA1 VTH0
p
+ Vgt1 +
I
DS1
2

,
:
Vgain1 g
m1
ro1
2
: Gain_dB 20log Vgain1 Vgain6 ( ) : VA1 10.827 V
Vgain1 507.055
Vgain1_dB 10 log Vgain1 ( ) :
ro1 7.46 10
5
ohm Vgain1_dB 27.051
STEP 8. Calculate the compensation components Rc and Cc. This is calculated to 5.74, 5.75, 5.76 according
to Analog integrated Circuit Design, Johns, Martin, page 243. The classic method is Rc1, but because we
know the outpu capacitance the Rc3 is a good choice. I chose just to average these.
Rc1
1
g
m6
: Rc2
1
g
m6
1
C
gs6
C
L
+
C
c
+

,
: Rc3
1
1.2 g
m1

: Rc
Rc1 Rc2 +
2
:
Rc3 0.613kohm
Rc1 3.31kohm
Rc2 14.341kohm
Rc 8.825 kohm
Design Requirements
C
L
1pF GBW 20MHz Vgt6 0.2V a 3 3 ? 2 B 1 Vgt1 0.1V
Summary of circuit values
L
n
Vgt6 F
T
, ( ) 0.824 m L
p
0.515 m C
c
0.333 pF I
DS6
31.099 A
W
6
29.278 m W
1
36.276 m Rc 8.825 kohm Gain_dB 83.962
W
4
14.639 m
Ln is the length of
all devices except
M1 and M2
Lp is the length of
M1 and M2
W1 is the width
of M1 and M2 W6 is the width of
M6, M5 and M7.
W4 is the width
of M3 and M4
Simulation
The amplifier is simulated using ADS with BSIM3 parameters available from the BSIM3 website at Berkeley (and
used in the calculations). The current reference is set to 31uA. The output range goes to within 300mV of the
rails.
This is a very good amplifier for this current and such a large output capacitance
The gain from the first stage is simulated 27.6dB, calculated 27.051dB
The gain from the second stage is simulated 36dB, calculated 14.93dB
The gm6 is simulated 0.254mA/V, calculated 0.302mA/V.
I think there is something wrong with the sims!!! Vgain1_dB 27.051
Vgain6_dB 14.93
g
m6
0.302
mA
V

The unity gain frequency is simulated 100MHz, calculated 20MHz. The top sims are with open loop gain
The plot at the bottom is in unity gain config showing that there is some peaking.