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8051 Instruction Set

8051 Instruction Set

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8051 instunction set
8051 instunction set

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Published by: Shailesh Sankdasariya on Sep 01, 2011
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09/02/2011

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Atmel 8051 Microcontrollers Hardware 1
0509C–8051–07/06
Section 18051 Microcontroller Instruction Set
For interrupt response time information, refer to the hardware description chapter.
Note:1.Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.
Instructions that Affect Flag Settings
Instruction Flag Instruction FlagC OV AC C OV AC
ADDXXXCLR COADDCXXXCPL CXSUBBXXXANL C,bitXMULOXANL C,/bitXDIVOXORL C,bitXDAXORL C,/bitXRRCXMOV C,bitXRLCXCJNEXSETB C1
The Instruction Set and Addressing Modes
R
n
Register R7-R0 of the currently selected Register Bank.
direct
8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/Oport, control register, status register, etc. (128-255)].
@R
i
8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0.
#data
8-bit constant included in instruction.
#data 16
16-bit constant included in instruction.
addr 16
16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte ProgramMemory address space.
addr 11
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page ofprogram memory as the first byte of the following instruction.
rel
Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127bytes relative to first byte of the following instruction.
bit
Direct Addressed bit in Internal Data RAM or Special Function Register.
 
2
0509C–8051–07/06
Table 1-1.
Instruction Set Summary
Note:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle
012345670NOPJBCbit,rel[3B, 2C]JBbit, rel[3B, 2C]JNBbit, rel[3B, 2C]JCrel[2B, 2C]JNCrel[2B, 2C]JZrel[2B, 2C]JNZrel[2B, 2C]1AJMP(P0)[2B, 2C]ACALL(P0)[2B, 2C]AJMP(P1)[2B, 2C]ACALL(P1)[2B, 2C]AJMP(P2)[2B, 2C]ACALL(P2)[2B, 2C]AJMP(P3)[2B, 2C]ACALL(P3)[2B, 2C]2LJMPaddr16[3B, 2C]LCALLaddr16[3B, 2C]RET[2C]RETI[2C]ORLdir, A[2B]ANLdir, A[2B]XRLdir, a[2B]ORLC, bit[2B, 2C]3RRARRCARLARLCAORLdir, #data[3B, 2C]ANLdir, #data[3B, 2C]XRLdir, #data[3B, 2C]JMP@A + DPTR[2C]4INCADECAADDA, #data[2B]ADDCA, #data[2B]ORLA, #data[2B]ANLA, #data[2B]XRLA, #data[2B]MOVA, #data[2B]5INCdir[2B]DECdir[2B]ADDA, dir[2B]ADDCA, dir[2B]ORLA, dir[2B]ANLA, dir[2B]XRLA, dir[2B]MOVdir, #data[3B, 2C]6INC@R0DEC@R0ADDA, @R0ADDCA, @R0ORLA, @R0ANLA, @R0XRLA, @R0MOV@R0, @data[2B]7INC@R1DEC@R1ADDA, @R1ADDCA, @R1ORLA, @R1ANLA, @R1XRLA, @R1MOV@R1, #data[2B]8INCR0DECR0ADDA, R0ADDCA, R0ORLA, R0ANLA, R0XRLA, R0MOVR0, #data[2B]9INCR1DECR1ADDA, R1ADDCA, R1ORLA, R1ANLA, R1XRLA, R1MOVR1, #data[2B]AINCR2DECR2ADDA, R2ADDCA, R2ORLA, R2ANLA, R2XRLA, R2MOVR2, #data[2B]BINCR3DECR3ADDA, R3ADDCA, R3ORLA, R3ANLA, R3XRLA, R3MOVR3, #data[2B]CINCR4DECR4ADDA, R4ADDCA, R4ORLA, R4ANLA, R4XRLA, R4MOVR4, #data[2B]DINCR5DECR5ADDA, R5ADDCA, R5ORLA, R5ANLA, R5XRLA, R5MOVR5, #data[2B]EINCR6DECR6ADDA, R6ADDCA, R6ORLA, R6ANLA, R6XRLA, R6MOVR6, #data[2B]FINCR7DECR7ADDA, R7ADDCA, R7ORLA, R7ANLA, R7XRLA, R7MOVR7, #data[2B]
 
3
0509C–8051–07/06
Table 1-2.
Instruction Set Summary (Continued)
Note:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle
89ABCDEF0SJMPREL[2B, 2C]MOVDPTR,#data 16[3B, 2C]ORLC, /bit[2B, 2C]ANLC, /bit[2B, 2C]PUSHdir[2B, 2C]POPdir[2B, 2C]MOVX A,@DPTR[2C]MOVX@DPTR, A[2C]1AJMP(P4)[2B, 2C]ACALL(P4)[2B, 2C]AJMP(P5)[2B, 2C]ACALL(P5)[2B, 2C]AJMP(P6)[2B, 2C]ACALL(P6)[2B, 2C]AJMP(P7)[2B, 2C]ACALL(P7)[2B, 2C]2ANLC, bit[2B, 2C]MOVbit, C[2B, 2C]MOVC, bit[2B]CPLbit[2B]CLRbit[2B]SETBbit[2B]MOVXA, @R0[2C]MOVXwR0, A[2C]3MOVC A,@A + PC[2C]MOVC A,@A + DPTR[2C]INCDPTR[2C]CPLCCLRCSETBCMOVXA, @RI[2C]MOVX@RI, A[2C]4DIVAB[2B, 4C]SUBBA, #data[2B]MULAB[4C]CJNE A,#data, rel[3B, 2C]SWAPADAACLRACPLA5MOVdir, dir[3B, 2C]SUBBA, dir[2B]CJNEA, dir, rel[3B, 2C]XCHA, dir[2B]DJNZdir, rel[3B, 2C]MOVA, dir[2B]MOVdir, A[2B]6MOVdir, @R0[2B, 2C]SUBBA, @R0MOV@R0, dir[2B, 2C]CJNE@R0, #data, rel[3B, 2C]XCHA, @R0XCHDA, @R0MOVA, @R0MOV@R0, A7MOVdir, @R1[2B, 2C]SUBBA, @R1MOV@R1, dir[2B, 2C]CJNE@R1, #data, rel[3B, 2C]XCHA, @R1XCHDA, @R1MOVA, @R1MOV@R1, A8MOVdir, R0[2B, 2C]SUBBA, R0MOVR0, dir[2B, 2C]CJNER0, #data, rel[3B, 2C]XCHA, R0DJNZR0, rel[2B, 2C]MOVA, R0MOVR0, A9MOVdir, R1[2B, 2C]SUBBA, R1MOVR1, dir[2B, 2C]CJNER1, #data, rel[3B, 2C]XCHA, R1DJNZR1, rel[2B, 2C]MOVA, R1MOVR1, AAMOVdir, R2[2B, 2C]SUBBA, R2MOVR2, dir[2B, 2C]CJNER2, #data, rel[3B, 2C]XCHA, R2DJNZR2, rel[2B, 2C]MOVA, R2MOVR2, ABMOVdir, R3[2B, 2C]SUBBA, R3MOVR3, dir[2B, 2C]CJNER3, #data, rel[3B, 2C]XCHA, R3DJNZR3, rel[2B, 2C]MOVA, R3MOVR3, ACMOVdir, R4[2B, 2C]SUBBA, R4MOVR4, dir[2B, 2C]CJNER4, #data, rel[3B, 2C]XCHA, R4DJNZR4, rel[2B, 2C]MOVA, R4MOVR4, ADMOVdir, R5[2B, 2C]SUBBA, R5MOVR5, dir[2B, 2C]CJNER5, #data, rel[3B, 2C]XCHA, R5DJNZR5, rel[2B, 2C]MOVA, R5MOVR5, AEMOVdir, R6[2B, 2C]SUBBA, R6MOVR6, dir[2B, 2C]CJNER6, #data, rel[3B, 2C]XCHA, R6DJNZR6, rel[2B, 2C]MOVA, R6MOVR6. AFMOVdir, R7[2B, 2C]SUBBA, R7MOVR7, dir[2B, 2C]CJNER7, #data, rel[3B, 2C]XCHA, R7DJNZR7, rel[2B, 2C]MOVA, R7MOVR7, A

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