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Advanced.asic.Chip.synthesis

Advanced.asic.Chip.synthesis

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Published by: pvk7380 on Sep 06, 2011
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10/14/2012

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ADVANCED ASIC CHIP SYNTHESIS
Using Synopsys® Design Compiler™Physical Compiler™ and PrimeTime®
SECON
D
EDITION
 
Trademark Information
UNIX is a registered trademark of UNIX Systems Laboratories, Inc.
Verilo
g
is a registered trademark of Cadence Design Systems, Inc.RSPF and DSPF is a trademark of Cadence Design Systems, Inc.
SDF and SPEF is a trademark of Open Verilog International.
Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! areregistered trademarks of Synopsys, Inc.Design Analyzer, Design Vision, Physical Compiler, Design Compiler, DFTCompiler, VHDL Compiler, HDL Compiler, ECO Compiler, Library Compiler,Synthetic Libraries, DesignTime, Floorplan Manager, characterize, dont_touch,
dont_touch_network and uniquify, are trademarks of Synopsys, Inc.SolvNET is a service mark of Synopsys, Inc.
All other brand or product names mentioned in this document, are trademarks orregistered trademarks of their respective companies or organizations.All ideas and concepts provided in this book are authors own, and are not endorsedby Synopsys, Inc. Synopsys, Inc. is not responsible for information provided in thisbook.

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