JOURNAL OF COMPUTING, VOLUME 3, ISSUE 8, AUGUST 2011, ISSN 2151-9617 HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.

ORG

90

Design and Synthesis of High Performance Adder Circuits

Pankaj Sharma, Rahul Malhotra and Mandeep Kaur

Abstract Data path units cant build without using Adders but drawback of the existing adder architectures is the propagation delay. This propagation delay is due to the carry chain/path from the input to the output. In this paper our main focus is to follow the modularity in the design and focus on optimizing the depth of the addition operation by using different adder architectures. A comparison of the area and delay of the different adder architectures is carried out.

Index Terms- Ripple Carry Adder, Carry Skip/By-pass Adder, Carry Select Adder, Carry Look-ahead Adder, Carry Select Adder with Look-ahead Carry generation, Xilinx Synthesis Tool, MODELSIM XE III 6.3 Simulator architecture permits better design tradeoffs in terms of 1 INTRODUCTION area and delay. DDITION forms the basis for many processing operations from counting to multiplication to filA. Ripple Carry Adder (RCA) tering. Addition is one of the most critical operaRipple Carry Adder for N-bit numbers is implemented tions performed by VLSI processors. Adders are widely used in ALUs, memory addressing, cryptography and by concatenating N full adders as shown in fig.1. This is floating point units etc. As a result, adder circuits that called a RCA, since the carry signal ripple from the add two binary numbers always attracted digital design- least significant bit position to the most significant bit ers. Various adder architectures are available to serve position. The carry of this adder traverses longest path different speed/density requirements. The critical re- called worst case delay path through N stages. quirement of the adder is speed but low power dissipation and area efficiency have become increasingly important in recent years. The key factor in the addition scheme is the introduction of logic blocks i.e. carry generate and propagate blocks which results in reduced logic depth, addition network and hence reduces the area and delay. Different architectures and carry computation methods deeply affect the efficiency of an adder circuit. A full adder has three inputs (two operands A & B and a carry input C in ) and two outputs (SUM and C out ). Boolean equations for basic Full Adder are as follow= .. (1)

and

= . + .

+ .

Where, G is generate (A.B) and P is propagate (A+B). Different adder architectures can be basic Adder Unit, Ripple Carry Adder, Carry Skip Adders, Carry Look Ahead Adder, Carry Select Adder, Pipelined Adder, Manchester carry chain adder, Multi-operand Adders, Pipelined Adder and the Carry Save Adder. The heterogeneous adder

= i.

..

(2)

Figure 1. Block Diagram of Ripple Carry Adder

The propagation time through the ripple carry adder is calculated using following mathematical equation: t adder = ( N-1) t carry + t sum .(3) Where, t carry is time taken for the carry to ripple from C in to C out , t sum is the time taken to produce the sum, N is the total number of bits. Main drawback of RCA is delay. As the N-bit length increases the delay path increases proportionally.

Pankaj Sharma is with the Adesh Institute of Engineering and Technology, Faridkot. Rahul Malhotra. is with the Department of Electronics, Bhai Maha Singh College of Engineering, Muktsar. Mandeep Kaur is with the with the Department of Electronics, Adesh Institute of Engineering and Technology, Faridkot.

B. Carry Skip/By-pass Adder (CSKA)

2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 3, ISSUE 8, AUGUST 2011, ISSN 2151-9617 HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG

91

Since the Cin-to-Cout represents the longest (critical) path in the Ripple Carry Adder. The carry is accelerated by choosing the value of Ai and Bi in such a way that Carry-Propagate i signals within a group of bits is i (i=0, 1, 2, 3) =1. If the entire Pi signals within a group are ones i.e. i = 1, then the condition exists for the carry to skip/bypass the entire group: If
i i i i

(i=0, 1, 2, 3) =1, then C 1 =C in for the 1st stage,

(i=4, 5 , 6 , 7)=1, then C 2 =C 1 for the 2nd stage, (i=8, 9, 10, 11) =1, then C 3 =C 2 for the 3rd stage, (i=12, 13, 14, 15) =1, then C out =C 3 for the 4th stage.

The CSKA divides the words to be added into groups of equal size of M-bits (where M=4). The basic structure of an N-bit Carry Skip Adder is shown in fig.2, where N= 16.

In RCA every full adder has to wait for the incoming carry before an outgoing carry is generated. One way to get around this linear dependency is to anticipate both possible values of the carry input i.e. 0 and 1 and evaluate the result in advance. Once the real value of the carry is known the result can be easily selected with the help of a simple multiplexer stage. A 16-bit CSA is constructed by dividing into 4 stages i.e. N=16 total number of bits, M=4 number of bits per stage (N/M = 4) and chaining such four equal length blocks as shown in fig.3. CSA has less delay as compared to RCA due to the anticipation of both possible values of C in in advance and as the multiplexers are used for the selection of C in so the area increases as compared to RCA. The propagation time through the Carry Select Adder is calculated using following mathematical equation:
= + +( / ) +

Where, t setup is delay of the setup stage to produce propagate and generate signals, t carry is the time taken by the carry to ripple through a length of the stage Mt carry , t mux is the delay of the multiplexer stage and t sum is time taken to produce the sum.

Figure 2. Block Diagram of Carry Skip/By-pass Adder

Within the group, carry propagates in a ripple-carry fashion. The worst case delay path t adder is carry generated at least significant bit position, ripples through the M bit positions, skip over (N/M - 2) bypass stages in the middle generating extra delays due to multiplexers t bypass , and is consumed at the last bit position without generating an output carry Cout through M-1 bit positions of most significant stage. The propagation time through the carry skip/bypass adder is calculated using following mathematical equation: = + + ( / 1) + ( 1) +

Figure 3. Block Diagram of Carry Select Adder

D. Carry Look-Ahead Adder (CLA)

In all the above discussed architectures of adders i.e. RCA, CSKA and CSA rippling effect of the carry is still present. A significant speed improvement in the implementation of a parallel adder was introduced by a CarryLook-Ahead-Adder (CLA) developed by Weinberger. In CLA sum and carry is independent the previous bit. G i = A i .B i ; P i = (A i B i )

Where, t setup is the fixed delay of the setup stage to produce propagate and generate signals, t carry is time taken for the carry to ripple through a full adder, t bypass is delay of the multiplexer in bypass stage, t sum is time taken to produce the sum, M is the number of stages and N/M is number of bits per stage. Thus, CSKA is faster than RCA at the expense of a few relatively simple modifications for N > 8. The delay is still linearly dependent on the size of the adder N.

C 1 = G 0 + P 0 .C 0

C 2 = G 1 +P 1 .C 1 =G 1 +P 1 .G 0 +P 1 .P 0 .C 0 C 3 = G 2 +P 2 .G 1 +P 2 .P 1 .G 0 +P 2 .P 1 .P 0 .C 0 C4 = G 3 +P 3 .G 2 +P 3 .P 2 .G 1 +P 3 P 2 .P 1 .G 0 +P 3 P 2 .P 1 .P 0 .C 0 & so on.

C. Carry Select Adder (CSA)

2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 3, ISSUE 8, AUGUST 2011, ISSN 2151-9617 HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG

92

Si = Ai Bi Ci = Pi Ci

Sum will be calculated as

The rippling effect has been effectively eliminated in CLA as the dependency Cout on previous stages is completely eliminated by expanding the above equation. Thus the addition time is independent of number of bits in CLA.

The block diagram of 16-bit CLA is shown in fig.4. Where N is the total number of bits, M is the number of bits per stage. 16-bit Carry Look-ahead Adder is divided into 4 stages, carry of each stage is generated by group carry look-ahead generator block. Setup stages generate P and G signals for all the stages. Carry for individual stage is generated by carry look-Ahead generator block of each stage. As we increase the number of bits in the CLA that is the word size, the complexity increases because the number of gates increases in calculating the carry expression C i +1 thus the area increases. CLA is a balance between Carry Select Adder and a Ripple Carry Adder as it has area delay product value between them.

Figure 5: Carry Select Adder with Look-ahead Carry Generation logic

2. SIMULATION RESULTS
Figure 6,7,8,9 and 10 show the simulation results of 16-bit Variable block ripple carry adder, carry skip adder, carry select adder, carry look-ahed adder,carry select adder with look-ahead adder respectively

Figure 4. Block Diagram of Carry Look-Ahead Adder

That is why CLA is widely used in the addition stages of multipliers. Carry look ahead is a well-known technique for decreasing the latency of addition by reducing the logic depth where w is the word length of the addends. It is one of the fastest adder architecture and allows significant design trade-offs to be made in terms of latency, area and power. .

Figure 6: Simulation waveform of Ripple Carry Adder

E. Carry Select Adder with Lookahead Carry generation (CSLA):As in CSA there is linear dependency is to anticipate both possible values of the carry input i.e. 0and 1and evaluate the result in advance. Once the real value of the carry is known the result can be easily selected with the help of a simple multiplexer stage as shown in fig. 5. But the carry ripples through the stage depending upon the number of bits by stage. More the number of bits per stage more will be the rippling of carry through the stage, more dependency and delay. This dependency is eliminated by implementing look-ahead carry generation logic at each rippling stages. Area and delay is reduced in this architecture as compared to CSA and CLA.

Figure 7: Simulation waveform of Carry Skip Adder

2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 3, ISSUE 8, AUGUST 2011, ISSN 2151-9617 HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG

93

Firstly functionality of most widely used adder circuits e.g. Ripple Carry Adder, Carry Bypass/Skip adder, carry Look-Ahead Adder, Carry Select Adder, Carry Select Adder with Look-ahead Carry generation in VLSI arithmetic circuits is individually described in hardware description language. Then functional verification of each of this adder circuit is carried out using industry standard ModelSim XE III 6.3c simulator. Then each adder circuit is synthesized using Xilinx ISE 8.1 i Project Navigator Synthesis Tool (XST). The synthesis report provides detailed information about the device utilization i.e. how much of FPGAs resources are used to realize the different adder circuits on FPGA and the delay summary for each adders architecture. TABLE 1 AREA UTILIZATION SUMMARY OF DIFFERENT ADDER
Figure 8: Simulation waveform of Carry Select Adder Device Utilization Summary Number of slices (1920) Number of 4 input LUTs (3840) Number of bonded IOBs(17 3)

ARCHITECTURES

RCA

CSKA

CLA

CSA

CSLA

19 (0.98%) 33 (0.85%)

22 (1.14%)

21 (1.09%)

27 (1.40%)

27 (1.40%)

39 (1.01%)

36 (0.93%) 50 (28.9%)

48 (1.25)

47 (1.22)

50 (28.9%)

50 (28.9%)

50 (28.9)

50 (28.9)

Figure 9: Simulation waveform of Carry Look-ahead Adder

140 120 100 80 60 40 20 0 RCA CSKA CLA CSA CSLA Number of bonded IOBs Number of 4 input LUTs Number of Slices

Figure 11: Comparison of Area Utlization of different adders Figure 10: Simulation waveform of Carry Select Adder with Lookahead Carry Genration

TABLE 2 TIMING SUMMARY OF DIFFERENT ADDER ARCHITECTURES

3. CONCLUSION
2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 3, ISSUE 8, AUGUST 2011, ISSN 2151-9617 HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/ WWW.JOURNALOFCOMPUTING.ORG

94

Timing Summary
Maximum combinational path delay Logic delay Routing delay

RCA

CSKA

CLA

CSA

CSLA

ders, IEEE Trans. on Computer, vol. 42, pp. 11631170, 1993

27.81ns

28.52ns

28.51ns

20.92ns

17.16ns

13.28ns

13.28ns

13.28ns

10.89ns

9.45ns

14.52ns

15.23ns

15.22ns

10.03ns

7.71ns

60 50 40 30 20 10 0 RCA CSKA CLA CSA CSLA Maximum combinational path delay Logical delay Routing delay

Pankaj Sharma obtained Bachelor of Engineering from Bhai Maha Singh College of Engineering, Muktsar (Punjab Technical Univeristy, Jalandhar) in Year 2008 and Presently Purusing Master of Technology Electrinocs and communication engineering from Adesh Institute of Engineering & Technology, Faridkot.His areaof interest include Wireless network, Computer network and micproprocessor etc.

Figure 12: Comparison of Timing Utlization of different adders

REFERENCES
[1] Jan. M. Rabaey , Anantha Chandrakasan & Borivoje Nikolic , ( 2003) Digital Integrated Circuits, Prentice Hall Electronics and VLSI Series, Second Edition. [2] Hasan Krad and Aws Yousif Al-Taie , Performance analysis of a 32-bit multiplier with a carry-look-ahead adder and a 32-bit Multiplier with a ripple adder using VHDL Journal of Computer Science 4 (4): 305308, 2008 ISSN 1549-3636. [3] M. Morris Mano , Digital Logic and Computer Design, Prentice Hall of India, First Edition-1998. [4] Ohsang Kwon, Earl E. Swartzlander & Kevin Nowka, A Fast Hybrid Carry Look ahead/Carry-Select Adder Design Great Lakes Symposium on VLSI Proceedings of the 11th VLSI, pp 149 152 , ISBN:158113-351-0, 2001. [5] Jeong - Gun Lee, Jeong -A Lee, Byeong - Seok Lee & Milos D. Ercegovac, A Design Method for Heterogeneous Adders International Conference on Embedded Software and Systems (Lecture Notes in Computer Science-4523), pp 121132, 2007. [6] John. F. Wakerley, Digital Design Principles and Practices, Pearson Education Asia, Fourth Edition2006. [7] Stephen Brown & Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, Tata McGraw-Hill Publishing Company limited, Seventh Edition-2006. [8] A. Tyagi, A reduced area scheme for carry-select ad-

Rahul Malhotra has his Bachelor of Engineering Degree in Electronics & Communication Engineering from Baba Saheb Naik College of Engineering,Pusad under Amravati University ,Amravati India in 2001 and Mtech degree in Electrinocs and communication Engineering from Giani zail Singh College of Engineering & Technology .Bathinda,India in 2008 and Ph.D in Electronics & Communication Engineering from Punjab Technical University,Jalandhar in 2011 .He joined as a lecturer in2001 at Guru Gobind Singh Talwandi Sabo, india.He joined as a Assistant Professor in Adesh Institute of Engineering & Technology,Faridkot,India in 2008.He joined as a Associated Professor in Bhai Maha Singh College of Engineering ,Muktsar,India in 2010.Presently ,He Working Associate Professore at Adesh Institute of Engineering & Technology,Faridkot. His area of interest includes Wireless Communication, Adhoc Network and Fuzzt Logic& Genetic Algorithms.He is member of India Society for Technical Education, The Institution of Electronics & Telecommunication Engineering (India), Institution of Engineering

2011 Journal of Computing Press, NY, USA, ISSN 2151-9617