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ANKIT RATHI 1. Write HDL code to realize all the logic gates.

AND GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port (a : in std_logic; b : in std_logic; y : out std_logic); end andgate; architecture Behavioral of andgate is begin y <= a and b; end Behavioral; VERILOG module and_gate(a,b,y); input a; input b; output y; assign y = a & b; endmodule OR GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity orgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end orgate; architecture Behavioral of orgate is begin y <= a or b; end Behavioral; VERILOG module or_gate(a,b,y); input a; input b; output y; assign y = a | b; endmodule

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ANKIT RATHI

NOT GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity notgate is Port ( a : in std_logic; y : out std_logic); end notgate; architecture Behavioral of notgate is begin y <= not a ; end Behavioral; VERILOG module not_gate(a,y); input a; output y; assign y = ~ a; endmodule NAND GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nandgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end nandgate; architecture Behavioral of nandgate is begin y <= a nand b ; end Behavioral; VERILOG module nand_gate(a,b,y); input a; input b; output y; assign y = ~( a & b ) ; endmodule

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ANKIT RATHI

NOR GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity norgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end norgate; architecture Behavioral of norgate is begin y <= a nor b ; end Behavioral; VERILOG module nor_gate(a,b,y); input a; input b; output y; assign y = ~ (a | b); endmodule XOR GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end xorgate; architecture Behavioral of xorgate is begin y <= a xor b; end Behavioral; VERILOG module xor_gate(a,b,y); input a; input b; output y; assign y = a ^ b ; endmodule

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ANKIT RATHI

XNOR GATE VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnorgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end xnorgate; architecture Behavioral of xnorgate is begin y <= a xnor b ; end Behavioral; VERILOG module xnor_gate(a,b,y); input a; input b; output y; assign y = ~ (a ^ b); endmodule

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ANKIT RATHI 2. Write a HDL program for the following combinational designs a. 2 to 4 decoder b. 8 to 3 (encoder without priority & with priority) c. 8 to 1 multiplexer d. 4 bit binary to gray converter e. Multiplexer, de-multiplexer, comparator. 2:4 DECODER VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2_4 is Port ( reset : in std_logic; din : in std_logic_vector ( 1 downto 0 ); dout : out std_logic_vector ( 3 downto 0 )); end decoder2_4; architecture Behavioral of decoder2_4 is begin process (reset,din) begin if(reset = '1')then dout <= "0000"; else case din is when "00" => dout <= "0001" ; when "01" => dout <= "0010" ; when "10" => dout <= "0100" ; when "11" => dout <= "1000" ; when others => dout <= "0000"; end case; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module decoder2_4v(reset,din,dout); input reset; input [1:0] din; output [3:0] dout; reg [3:0] dout; always @(reset,din) begin if (reset==1'b1) begin dout=4'b0000; end else begin case(din) 2'b00 : dout=4'b0001; 2'b01 : dout=4'b0010; 2'b10 : dout=4'b0100; 2'b11 : dout=4'b1000; endcase end end endmodule

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ANKIT RATHI 8:3 ENCODER (WITHOUT PRIORITY) VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3 is Port ( reset : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end encoder8_3; architecture Behavioral of encoder8_3 is begin process(reset,din) begin if (reset='1') then dout<="000"; else case din is when "00000001"=> dout<="000"; when "00000010"=> dout<="001"; when "00000100"=> dout<="010"; when "00001000"=> dout<="011"; when "00010000"=> dout<="100"; when "00100000"=> dout<="101"; when "01000000"=> dout<="110"; when "10000000"=> dout<="111"; when others => dout<="000"; end case; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module encoder8_3v(din,reset,dout); input [7:0] din; input reset; output [2:0] dout; reg [2:0] dout; always @(din,reset) begin if (reset == 1'b1) dout = 3'b000; else begin case (din) 8'b00000001 : dout=3'b000; 8'b00000010 : dout=3'b001; 8'b00000100 : dout=3'b010; 8'b00001000 : dout=3'b011; 8'b00010000 : dout=3'b100; 8'b00100000 : dout=3'b101; 8'b01000000 : dout=3'b110; 8'b10000000 : dout=3'b111; default : dout=3'b000; endcase end end endmodule

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ANKIT RATHI 8:3 PRIORITY ENCODER VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pri_enc is Port ( reset : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end pri_enc; architecture Behavioral of pri_enc is begin process(reset,din) begin if(reset='1')then dout<=(others=>'0'); else if(din(0)='1')then dout<="000"; elsif(din(1)='1')then dout<="001"; elsif(din(2)='1')then dout<="010"; elsif(din(3)='1')then dout<="011"; elsif(din(4)='1')then dout<="100"; elsif(din(5)='1')then dout<="101"; elsif(din(6)='1')then dout<="110"; elsif(din(7)='1')then dout<="111"; else dout<="000"; end if; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module prienc123(IR,RA,reset); input [7:0] IR; output [2:0] RA; input reset; reg [2:0] RA; always @(IR,reset) begin if(reset==1'b1) RA=3'b000; else begin casex (IR) 8'bxxxxxxx1 : RA= 3'b000; 8'bxxxxxx10 : RA= 3'b001; 8'bxxxxx100 : RA= 3'b010; 8'bxxxx1000 : RA= 3'b011; 8'bxxx10000 : RA= 3'b100; 8'bxx100000 : RA= 3'b101; 8'bx1000000 : RA= 3'b110; 8'b10000000 : RA= 3'b111; default : RA=3'b000; endcase end end endmodule

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ANKIT RATHI 8:1 MULTIPLEXER VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8_1 is Port ( d : in std_logic_vector(7 downto 0); reset : in std_logic; sel : in std_logic_vector(2 downto 0); y : out std_logic); end mux8_1; architecture Behavioral of mux8_1 is begin process (sel,reset,d) is begin if (reset='1')then y <= '0'; else case sel is when "000" => y <= d(0); when "001" => y <= d(1); when "010" => y <= d(2); when "011" => y <= d(3); when "100" => y <= d(4); when "101" => y <= d(5); when "110" => y <= d(6); when "111" => y <= d(7); when others => null; end case; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module mux8_1v(d,reset,sel,y); input [7:0] d; input reset; input [2:0] sel; output y; reg y; always@(reset,sel,d) begin if(reset==1) y = 1'b0; else begin case(sel) 3'd0 : y = d[0]; 3'd1 : y = d[1]; 3'd2 : y = d[2]; 3'd3 : y = d[3]; 3'd4 : y = d[4]; 3'd5 : y = d[5]; 3'd6 : y = d[6]; 3'd7 : y = d[7]; endcase end end endmodule

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ANKIT RATHI BINARY TO GRAY VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binarytogray is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end binarytogray; architecture Behavioral of binarytogray is begin process(b) begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end process; end Behavioral; VERILOG module bintogray(b,g); input [3:0] b; output [3:0] g; reg [3:0] g; always@(b) begin g[3]=b[3]; g[2]=b[3] ^ b[2]; g[1]=b[2] ^ b[1]; g[0]=b[1] ^ b[0]; end endmodule

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ANKIT RATHI GRAY TO BINARY VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity graytobin is Port ( g : in std_logic_vector(3 downto 0); b : out std_logic_vector(3 downto 0)); end graytobin; architecture Behavioral of graytobin is begin process(g) begin b(3)<=g(3); b(2)<=g(3) xor g(2); b(1)<=g(3) xor g(2) xor g(1); b(0)<=g(3) xor g(2) xor g(1) xor g(0); end process; end Behavioral; VERILOG module gratobin(g,b); input [3:0] g; output [3:0] b; reg [3:0] b; always@(g) begin b[3]=g[3]; b[2]=g[3] ^ g[2]; b[1]=g[3] ^ g[2] ^ g[1]; b[0]=g[3] ^ g[2] ^ g[1] ^ g[0]; end endmodule

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ANKIT RATHI 1:8 DEMULTIPLEXER VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1X8 is Port ( y : in std_logic; reset : in std_logic; sel : in std_logic_vector(2 downto 0); d : out std_logic_vector(7 downto 0)); end demux1X8; architecture Behavioral of demux1X8 is begin process(reset,y,sel) begin if(reset=1)then d<=(others=>0); else case sel is when "000" => d(0) <= y ; when "001" => d(1) <= y ; when "010" => d(2) <= y ; when "011" => d(3) <= y ; when "100" => d(4) <= y ; when "101" => d(5) <= y ; when "110" => d(6) <= y ; when "111" => d(7) <= y ; when others => null; end case; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module demux1_8(reset,y,sel,d); input y; input reset; input [2:0] sel; output [7:0] d; reg [7:0] d; always@(sel,y,reset) begin if(reset==1b1) d=8b00000000; else begin case (sel) 3'b000 : d[0] = y ; 3'b001 : d[1] = y ; 3'b010 : d[2] = y ; 3'b011 : d[3] = y ; 3'b100 : d[4] = y ; 3'b101 : d[5] = y ; 3'b110 : d[6] = y ; 3'b111 : d[7] = y ; default :begin end endcase end end endmodule

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ANKIT RATHI COMPARATOR VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( reset : in std_logic; a : in std_logic_vector(1 downto 0); b : in std_logic_vector(1 downto 0); aeqb,agtb,altb : out std_logic); end comp; architecture Behavioral of comp is begin process(reset,a,b) variable t1,t2,t3:std_logic; begin if(reset='1')then t1:='0'; t2:='0'; t3:='0'; else if(a=b)then t1:='1'; t2:='0'; t3:='0'; elsif(a>b)then t1:='0'; t2:='1'; t3:='0'; else t1:='0'; t2:='0'; t3:='1'; end if; end if; aeqb<=t1; agtb<=t2; altb<=t3; end process; end Behavioral;

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ANKIT RATHI VERILOG module comparator(a,b,en,aeqb,agtb,altb); input [1:0] a; input [1:0] b; input en; output aeqb; output agtb; output altb; reg aeqb,agtb,altb; always @(a,b,en) begin if (en==1) if(a==b) begin aeqb=1; agtb=0; altb=0; end else if(a>b) begin aeqb=0; agtb=1; altb=0; end else begin aeqb=0; agtb=0; altb=1; end else begin aeqb=0; agtb=0; altb=0; end end endmodule

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ANKIT RATHI 3. Write a HDL code to describe the functions of a Full Adder Using three modeling styles.

DATA FLOW DESCRIPTION VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( a,b,cin : in std_logic; sum,cout : out std_logic); end FullAdder; architecture dtfl of FullAdder is begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (cin and a); end dtfl; VERILOG module FullAdder(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum = a ^ b ^ cin ; assign cout = (a & b) | (b & cin) | (cin & a); endmodule

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ANKIT RATHI BEHAVIORAL DESCRIPTION VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Seq_Full is Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; Sum : out std_logic; Cout : out std_logic); end Seq_Full; architecture Behavioral of Seq_Full is begin process(A,B,Cin) begin if(A='0' and B='0' and Cin='0')then Sum<='0'; Cout<='0'; elsif(A='0' and B='0' and Cin='1')then Sum<='1'; Cout<='0'; elsif(A='0' and B='1' and Cin='0')then Sum<='1'; Cout<='0'; elsif(A='0' and B='1' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='0' and Cin='0')then Sum<='1'; Cout<='0'; elsif(A='1' and B='0' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='0')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='1')then Sum<='1'; Cout<='1'; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG


module fulladd(a,b,cin,sum,cout); input a,b,cin; output sum,cout; reg sum,cout; always@(a,b,cin) begin if(a==1'b0 & b==1'b0 & cin==1'b0) begin sum=1'b0; cout=1'b0; end else if(a==1'b0 & b==1'b0 & cin==1'b1) begin sum=1'b1; cout=1'b0; end else if(a==1'b0 & b==1'b1 & cin==1'b0) begin sum=1'b1; cout=1'b0; end else if(a==1'b0 & b==1'b1 & cin==1'b1) begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b0 & cin==1'b0) begin sum=1'b1; cout=1'b0; end else if(a==1'b1 & b==1'b0 & cin==1'b1) begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b1 & cin==1'b0) begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b1 & cin==1'b1) begin sum=1'b1; cout=1'b1; end end endmodule

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ANKIT RATHI STRUCTURAL DESCRIPTION VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( I1 : in std_logic; I2 : in std_logic; O1 : out std_logic; O2 : out std_logic); end HA; architecture Behavioral of HA is begin O1 <= I1 xor I2; O2 <= I1 and I2; end Behavioral; ---------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is port ( I1: in std_logic; I2: in std_logic; O1: out std_logic); end orgate; architecture Behavioral of orgate is begin O1 <= I1 or I2; end Behavioral; -----------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FA is Port ( a,b,cin : in std_logic; sum,cout : out std_logic); end FA; architecture Behavioral of FA is component HA port (I1, I2 : in std_logic; O1, O2 : out std_logic); end component; component orgate

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ANKIT RATHI port (I1, I2 : in std_logic; O1 : out std_logic); end component; signal s0,c0,c1:std_logic; begin HA1 : HA port map (a,b,s0,c0); HA2 : HA port map (cin,s0,sum,c1); O1 : orgate port map (c0,c1,cout); end Behavioral; VERILOG module FA(a,b,cin,sum,cout); input a; input b; input cin; output sum; output cout; HA H1 (a,b,s0,c0); HA H2 (cin,s0,sum,c1); or O1 (cout,c0,c1); endmodule ---------------------------------------------------------------module HA(a,b,s,c); input a,b; output s,c; xor (s,a,b); and (c,a,b); endmodule

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ANKIT RATHI 4. Write a model for 32 bit ALU using the schematic diagram shown below

ALU should use combinational logic to calculate an output based on the four bit op-code input. ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low. ALU should decode the 4 bit op-code according to the given in example below.

VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU is Port ( a,b : in std_logic_vector(3 downto 0); opcode : in std_logic_vector(3 downto 0); enable : in std_logic; y : out std_logic_vector(7 downto 0)); end ALU; architecture Behavioral of ALU is begin process(enable,a,b,opcode) begin if(enable='1')then case opcode is when "0001" => y <= "000" & (('0'& a) + ('0' & b)); when "0010" => y <= "000" & (('0' & a)-('0' & b)); when "0011" => y <= "0000" & (not a); when "0100" => y <= a * b; when "0101" => y <= "0000" & (a and b); when "0110" => y <= "0000" & (a or b); when "0111" => y <= "0000" & (a nand b); when "1000" => y <= "0000" & (a xor b); when others => y <= (others=>'0'); end case; else

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ANKIT RATHI y <= (others=>'0'); end if; end process; end Behavioral; VERILOG module ALU_MIXED(a,b,opcode,enable,y); input [3:0] a,b; input [3:0] opcode; input enable; output [7:0] y; reg [7:0] y; always@(a,b,enable,opcode) begin if(enable==1'b1) begin case (opcode) 4'b0001 : y = a + b; 4'b0010 : y = a - b; 4'b0011 : y = ~ a; 4'b0100 : y = a * b; 4'b0101 : y = a & b; 4'b0110 : y = a | b; 4'b0111 : y = ~(a & b); 4'b1000 : y = a ^ b; default: y=8'd0; endcase end else begin y=8'd0; end end endmodule

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ANKIT RATHI 5. Develop the HDL code for the following flip-flops, SR, D, JK, T. SR FLIP FLOP VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SR_ff is Port ( S : in std_logic; R : in std_logic; clk : in std_logic; reset : in std_logic; q,qb : out std_logic); end SR_ff; architecture Behavioral of SR_ff is begin process (clk,reset) variable temp : std_logic; begin if(reset='1')then temp := '0'; elsif(clk'event and clk='1')then if(S='0' and R='0')then temp := temp ; elsif(S='0' and R='1')then temp := '0' ; elsif(S='1' and R='0')then temp := '1' ; elsif(S='1' and R='1')then temp := 'Z' ; end if; end if; q <= temp; qb <= not temp; end process; end Behavioral;

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ANKIT RATHI VERILOG module SR_f_f(SR,clk,reset,q,qb); input [1:0] SR ; input clk,reset; output q,qb; reg q,qb; always@(posedge clk) begin if(reset==1'b1) q = 1'b0; else begin case (SR) 2'b00 : q = q ; 2'b01 : q = 1'd0 ; 2'b10 : q = 1'd1 ; 2'b11 : q = 1'dZ ; endcase end qb = ~ q; end endmodule

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ANKIT RATHI D FLIP FLOP VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity D_ff is Port ( d : in std_logic; reset : in std_logic; clk : in std_logic; q,qb : buffer std_logic); end D_ff; architecture Behavioral of D_ff is --signal clk_div : std_logic_vector(25 downto 0); --signal clkdiv : std_logic; begin --process(clk) --begin -if(clk='1' and clk'event)then -clk_div<=clk_div+1; -end if; --end process; --clkdiv<=clk_div(22); process(clk,reset) --process(clkdiv,reset) begin if(reset='1')then q <= '0'; elsif(clk'event and clk='1')then --elsif(clkdiv'event and clkdiv='1')then q <= d; end if; end process; qb <= not q; end Behavioral;

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ANKIT RATHI VERILOG module D_f_f(d,clk,reset,q,qb); input d; input clk; input reset; output q; output qb; reg q,qb; //clock divider //reg [24:0] clk_signal; //always@(posedge clk) //begin //if(reset) //clk_signal=25'd0; //else //clk_signal=clk_signal+1; //end always@(posedge clk or posedge reset) //always@(posegde clk_signal[21] or posedge reset) begin if(reset==1'b1) begin q<=1'b0; qb<=1'b1; end else begin q<=d; qb<=~d; end end endmodule

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ANKIT RATHI T FLIP FLOP VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity T_ff is Port ( clk : in std_logic; reset : in std_logic; t : in std_logic; q : inout std_logic; qb : inout std_logic); end T_ff; architecture Behavioral of T_ff is --signal clk_div : std_logic_vector(25 downto 0); --signal clkdiv : std_logic; begin --process(clk) --begin -if(clk='1' and clk'event)then -clk_div<=clk_div+1; -end if; --end process; --clkdiv<=clk_div(22); process(clk,reset) --process(clkdiv,reset) begin if reset='1' then q <= '0'; elsif(clk'event and clk='1')then --elsif(clkdiv'event and clkdiv='1')then if t='1' then q <= not q ; else q<=q; end if; end if; end process; qb <= not q ; end Behavioral;

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ANKIT RATHI VERILOG module T_f_f(clk,reset,t,q,qb); input clk; input reset; input t; output q; output qb; reg q,qb; //clock divider //reg [24:0] clk_signal; //always@(posedge clk) //begin //if(reset) //clk_signal=25'd0; //else //clk_signal=clk_signal+1; //end always@(posedge clk) //always@(posegde clk_signal[21] or posedge reset) begin if (reset==1'b1) begin q=1'b0; qb=1'b1; end else begin if(t==1'b1) q = ~q; else q = q; end qb=~q; end endmodule

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ANKIT RATHI JK FLIP FLOP VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JK_ff is Port ( J : in std_logic; K : in std_logic; clk : in std_logic; reset: in std_logic; q : buffer std_logic; qb : inout std_logic); end JK_ff; architecture JK_ff_arch of JK_ff is --signal clk_div : std_logic_vector(25 downto 0); --signal clkdiv : std_logic; begin --process(clk) --begin --if(clk='1' and clk'event)then --clk_div<=clk_div+1; --end if; --end process; --clkdiv<=clk_div(22); process(clk,reset) --process(clkdiv,reset) variable temp:std_logic; begin if(reset='1')then temp := '0'; elsif(clk'event and clk='1')then --elsif(clkdiv'event and clkdiv='1')then if(J='0' and K='0')then temp := temp ; elsif(J='0' and K='1')then temp := '0' ; elsif(J='1' and K='0')then temp := '1' ; elsif(J='1' and K='1')then temp := not temp ; end if; end if; q <= temp; qb <= not temp; end process; end JK_ff_arch;

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ANKIT RATHI VERILOG module JK_f_f(JK,clk,reset,q,qb); input [1:0] JK; input clk; input reset; output q,qb; reg q,qb; //clock divider //reg [24:0] clk_signal; //always@(posedge clk) //begin //if(reset) //clk_signal=25'd0; //else //clk_signal=clk_signal+1; //end always@(posedge clk) //always@(posegde clk_signal[21] or posedge reset) begin if (reset==1b1) q = 1'd0 ; else begin case(JK) 2'b00 : q = q ; 2'b01 : q = 1'd0 ; 2'b10 : q = 1'd1 ; 2'b11 : q = ~ q ; endcase end qb = ~q; end endmodule

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ANKIT RATHI 6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and any sequence counters. SYNCHRONOUS BINARY UP COUNTER VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sync_rst_binary is Port ( clk : in std_logic; reset : in std_logic; qout : inout std_logic_vector(3 downto 0)); end sync_rst_binary; architecture Behavioral of sync_rst_binary is --signal clk_div:std_logic_vector(25 downto 0); --signal clkdiv:std_logic; begin --process(clk) --begin --if(clk='1' and clk'event)then --clk_div<=clk_div+1; --end if; --end process; --clkdiv<=clk_div(22); process(clk) --process(clkdiv) begin if(clk'event and clk='1') then --if(clkdiv='1' and clkdiv'event)then if(reset='1')then qout<="0000"; else qout<=qout+1; end if; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module SYNC_RESET_BINARY(clk,reset,qout); input clk; input reset; output [3:0] qout; reg [3:0] qout; //reg [24:0]clk_signal; //always@(posedge clk) //begin //if(reset==1'b1) //clk_signal=25'b0; //else //clk_signal=clk_signal+1; //end always@(posedge clk) //always@(posedge clk_signal[21]) begin if(reset==1'b1) qout=4'b0000; else qout=qout+1; end endmodule

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ANKIT RATHI ASYNCHRNOUS BINARY COUNTER. VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ASYNC_RST_COUNTER is Port ( clk : in std_logic; reset : in std_logic; qout : inout std_logic_vector(3 downto 0)); end ASYNC_RST_COUNTER; architecture Behavioral of ASYNC_RST_COUNTER is --signal clk_div:std_logic_vector(25 downto 0); --signal clkdiv:std_logic; begin --process(clk) --begin --if(clk='1' and clk'event)then --clk_div<=clk_div+1; --end if; --end process; --clkdiv<=clk_div(22); process(clk) --process(clkdiv) begin if(reset='1')then qout<="0000"; elsif(clk'event and clk='1')then qout<=qout+1; end if; end process; end Behavioral;

--elsif(clkdiv'event and clkdiv='1')then

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ANKIT RATHI VERILOG module async_reset_binary(clk,reset,qout); input clk; input reset; output [3:0] qout; reg [3:0] qout; //clock divider //reg [24:0]clk_signal; //always@(posedge clk) //begin //if(reset'1'b1) //clk_signal=25'd0; //else //clk_signal=clk_signal+1; //end always@(posedge clk or posedge reset) begin if(reset) begin qout=4'b0000; end else begin qout=qout+1; end end endmodule

//always@(posedge clk_signal[21] or posedge reset)

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ANKIT RATHI SYNCHRONOUS BCD COUNTER. VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SYNC_RST_BCD is Port ( clk : in std_logic; reset : in std_logic; qout : inout std_logic_vector(3 downto 0)); end SYNC_RST_BCD; architecture Behavioral of SYNC_RST_BCD is --signal clk_div:std_logic_vector(25 downto 0); --signal clkdiv:std_logic; begin --process(clk) --begin --if(clk='1' and clk'event)then --clk_div<=clk_div+1; --end if; --end process; --clkdiv<=clk_div(22); process(clk) --process(clkdiv) begin if(clk='1' and clk'event)then --if(clkdiv'event and clkdiv='1')then if(reset='1')then qout<="0000"; else qout<=qout+1; if(qout="1001")then qout<="0000"; end if; end if; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module sync_reset_bcd(reset,clk,qout); input reset; input clk; output [3:0] qout; reg [3:0] temp; //reg [24:0] clk_signal; assign qout=temp; //clock divider //always@(posedge clk) //begin //if(reset'1'b1) //clk_signal=25'd0; //else //clk_signal=clk_signal+1; //end always@(posedge clk) //always@(posedge clk_signal[21]) begin if(reset==1'b1) temp=4'b0000; else begin temp=temp+1; if(temp==4'b1001) temp=4'b0000; end end endmodule

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ANKIT RATHI ASYNCHRONOUS BCD COUNTER VERILOG library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ASYNC_RST_BCD is Port ( clk : in std_logic; reset : in std_logic; qout : inout std_logic_vector(3 downto 0)); end ASYNC_RST_BCD; architecture Behavioral of ASYNC_RST_BCD is --signal clk_div:std_logic_vector(25 downto 0); --signal clkdiv:std_logic; begin --process(clk) --begin --if(clk='1' and clk'event)then --clk_div<=clk_div+1; --end if; --end process; --clkdiv<=clk_div(22); process(clk,reset) --process(clkdiv,reset) begin if(reset='1')then qout<="0000"; elsif(clk'event and clk='1')then --elsif(clkdiv'event and clkdiv='1')then qout<=qout+1; if(qout="1001")then qout<="0000"; end if; end if; end process; end Behavioral;

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ANKIT RATHI VERILOG module ASYNC_RESET_BCD(clk,reset,qout); input clk; input reset; output [3:0] qout; reg [3:0] temp; //reg [24:0] clk_signal; assign qout=temp; //clock divider //always@(posedge clk) //begin //if(reset'1'b1) //clk_signal=25'd0; //else //clk_signal=clk_signal+1; //end always@(posedge clk or posedge reset) //always@(posedge clk_signal[21] or posedge reset) begin if(reset==1'b1) temp=4'b0000; else begin temp=temp+1'b1; if(temp==4'b1001) temp="0000"; end end endmodule

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ANKIT RATHI Using a Moore Model generate a sequence generator to generate the sequence 4,8,15,16,23,42 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SEQGEN1 is Port ( clk : in STD_LOGIC; count : out STD_LOGIC_VECTOR (5 downto 0)); end SEQGEN1; architecture Behavioral of SEQGEN1 is type state_type is(S0,S1,S2,S3,S4,S5); signal ps,ns:state_type; --signal clk_div:std_logic(25 downto 0); --signal clkdiv:std_logic; begin --process(clk) --begin --if(clk='1' and clk'event)then --clk_div<=clk_div+1; --end if; --end process; --clkdiv<=clk_div(22); process(clk) --process(clkdiv) begin if(clk='1' and clk'event)then --if(clkdiv='1' and clkdiv'event)then ps<=ns; end if; end process; process(ps) begin case ps is when S0=> count<="000100"; ns<=S1; when S1=> count<="001000"; ns<=S2; when S2=> count<="001111"; ns<=S3; when S3=> count<="010000"; ns<=S4; when S4=> count<="010111"; ns<=S5; when S5=> count<="101010"; ns<=S0; when OTHERS=> NULL; end case; end process; end Behavioral;

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ANKIT RATHI ANY SEQUENCE GENERATOR 0,2,7,9 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity anycount is Port ( clk : in std_logic; reset : in std_logic; q : inout std_logic_vector(3 downto 0):="0000"); end anycount; architecture Behavioral of anycount is --signal clk_div:std_logic_vector(25 downto 0); --signal clkdiv:std_logic; begin --process(reset,clk) --begin --if(reset='1')then --clk_div<=(others=>'0'); --elsif(clk'event and clk='1')then --clk_div<=clk_div+1 ; --end if; --end process; --clkdiv<=clk_div(22); process(reset,clk) --process(clkdiv,reset) begin if (reset='1') then q<="0000"; elsif(clk'event and clk='1')then --elsif(clkdiv'event and clkdiv='1')then case q is when"0000"=>q<="0010"; when"0010"=>q<="0111"; when"0111"=>q<="1001"; when others=>q<="0000"; end case; end if; end process; end Behavioral;

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ANKIT RATHI VHDL CODE FOR UP AND DOWN COUNTER 7 SEGMENT DISPLAY library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity updown is Port ( clk : in std_logic; reset : in std_logic; q : inout std_logic_vector(3 downto 0); dis : out std_logic ; seg : out std_logic_vector(6 downto 0)); end updown; architecture Behavioral of updown is signal s1:std_logic_vector(25 downto 0); signal s2:std_logic; signal dir:std_logic:='1'; begin process(reset,clk) begin if (reset='1')then s1<=(others=>'0'); dis<='0'; elsif(clk'event and clk='1')then dis<='1'; s1<=s1+1; end if; end process; s2<=s1(22); process(s2,reset) begin if(reset='1')then q <= (others=>'0'); elsif(s2'event and s2='1')then if(dir='1')then q<=q+1; else q<=q-1; end if; end if; if(q>"1110")then dir<='0'; elsif(q<="0001")then dir<='1'; end if; end process; seg(6 downto 0) <= "0111111" when q="0000" else "0000110" when q="0001" else

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ANKIT RATHI "1011011" when q="0010" else "1001111" when q="0011" else "1100110" when q="0100" else "1101101" when q="0101" else "1111101" when q="0110" else "0000111" when q="0111" else "1111111" when q="1000" else "1101111" when q="1001" else "1110111" when q="1010" else "1111100" when q="1011" else "0111001" when q="1100" else "1011110" when q="1101" else "1111001" when q="1110" else "1110001" when q="1111" else "0000000"; end Behavioral;

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ANKIT RATHI VHDL CODE TO CONTROL SPEED, DIRECTION OF STEPPER MOTOR. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity stepper is Port ( clk : in std_logic; reset : in std_logic; dir : in std_logic; s0 : inout std_logic_vector(3 downto 0)); end stepper; architecture stepper_arch of stepper is signal s1:std_logic_vector(25 downto 0); signal s2:std_logic; begin process(reset,clk) begin if(reset='1')then s1<=(others=>'0'); elsif(clk'event and clk='1')then s1<=s1+1; end if; end process; s2<=s1(16); process(reset,s2) begin if(reset='1')then s0<="0001"; elsif(s2'event and s2='1')then if(dir='1')then s0(2 downto 0) <= s0(3 downto 1); s0(3)<=s0(0); elsif(dir='0')then s0(3 downto 1)<=s0(2 downto 0); s0(0)<=s0(3); end if; end if; end process; end stepper_arch;

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ANKIT RATHI VHDL CODE FOR RELAY. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity relay is Port ( clk : in std_logic; reset : in std_logic; coil : in std_logic; r0 : inout std_logic); end relay; architecture relay_arch of relay is signal s1:std_logic_vector(25 downto 0); signal s2:std_logic; begin process(reset,clk) begin if(reset='1')then s1<=(others=>'0'); elsif(clk'event and clk='1')then s1<=s1+1; end if; end process; s2<=s1(22); process(coil,s2) begin if(coil='1')then r0<='1'; elsif(s2'event and s2='1')then r0<=not r0; end if; end process; end relay_arch;

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ANKIT RATHI KEYPAD SCANNER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keypad is Port ( clk :in std_logic; rst :in std_logic; rl :in std_logic_vector(3 downto 0); sl :out std_logic_vector(3 downto 0); seg7 :out std_logic_vector(7 downto 0); dis_s :out std_logic_vector(5 downto 0)); end keypad; architecture Behavioral of keypad is signal d:std_logic_vector(3 downto 0); signal ored:std_logic; signal scan:std_logic_vector(1 downto 0); signal sl_s:std_logic_vector(3 downto 0); signal decoded:std_logic_vector(1 downto 0); signal display_s:std_logic_vector(3 downto 0); signal s1:std_logic_vector(20 downto 0); signal s2:std_logic; signal s3:std_logic; signal s4:std_logic; begin process(clk,rst) begin if(rst='1')then s1<=(others=>'0'); elsif(clk' event and clk='1')then s1<=s1+1; end if; end process; s2<=s1(14); s3<=s1(11); process(s2,rst) begin if(rst='1')then scan<=(others=>'0'); elsif(s2'event and s2='1')then scan<=scan+1; end if; end process; sl_s<= "0111" when scan ="00" else "1011" when scan ="01" else "1101" when scan ="10" else "1110";

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ANKIT RATHI sl<=sl_s; ored<=((not rl(0))or(not rl(1)) or(not rl(2)) or (not rl(3))); process (s3,rst) begin if (rst='1')then d<=(others=>'0'); elsif(rising_edge (s3))then d<=d(2 downto 0) & ored; end if; end process; s4<='1' when (d="1111") else '0'; decoded<="00"when(rl="0111")else "01"when(rl="1011")else "10"when(rl="1101")else "11"; process (s4,rst) begin if(rst='1')then display_s<=(others=>'0'); elsif(rising_edge (s4))then display_s<=scan & decoded; end if; end process; seg7(7 downto 0)<= "10111111"when display_s="0000" else "10000110"when display_s="0001" else 11011011"when display_s="0010" else "11001111"when display_s="0011" else "11100110"when display_s="0100" else "11101101"when display_s="0101" else "11111101"when display_s="0110" else "10000111"when display_s="0111" else "11111111"when display_s="1000" else "11101111"when display_s="1001" else "11110111"when display_s="1010" else "11111100"when display_s="1011" else "10111001"when display_s="1100" else "11011110"when display_s="1101" else "11111001"when display_s="1110" else "11110001"when display_s="1111" else "10000000"; dis_s<=(others=>'1'); end Behavioral;

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ANKIT RATHI Write HDL code to generate different waveforms (Sine, Square,Triangle, Ramp etc.,) using DAC change the frequency and amplitude. NEGATIVE RAMP WAVE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity negramp_wave is Port ( reset : in std_logic; clk : in std_logic; d0 : inout std_logic_vector(11 downto 0)); end negramp_wave; architecture Behavioral of negramp_wave is signal clk_div:std_logic_vector(50 downto 0); signal clkdiv:std_logic; begin process(reset,clk) begin if reset='1' then clk_div<=(others=>'0'); elsif(clk'event and clk='1')then clk_div<=clk_div+1; end if; end process; clkdiv<=clk_div(1); process(reset,clkdiv) begin if(reset='1')then d0<=(others=>'0'); elsif(clkdiv'event and clkdiv='1')then d0<=d0-1; end if; end process; end Behavioral;

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ANKIT RATHI POSITIVE RAMP WAVE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity posramp_wave is Port ( reset : in std_logic; clk : in std_logic; d0 : inout std_logic_vector(11 downto 0)); end posramp_wave; architecture Behavioral of posramp_wave is signal clk_div:std_logic_vector(50 downto 0); signal clkdiv:std_logic; begin process(reset,clk) begin if reset='1' then clk_div<=(others=>'0'); elsif(clk'event and clk='1')then clk_div<=clk_div+1; end if; end process; clkdiv<=clk_div(1); process(reset,clkdiv) begin if(reset='1')then d0<=(others=>'0'); elsif(clkdiv'event and clkdiv='1')then d0<=d0+1; end if; end process; end Behavioral;

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ANKIT RATHI SQUARE WAVE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity square_wave is Port ( reset : in std_logic; clk : in std_logic; sq : inout std_logic_vector(11 downto 0)); end square_wave; architecture Behavioral of square_wave is signal clk_div:std_logic_vector(50 downto 0); signal clkdiv:std_logic; begin process(reset,clk) begin if reset='1' then clk_div<=(others=>'0'); elsif(clk'event and clk='1')then clk_div<=clk_div+1; end if; end process; clkdiv<=clk_div(12); process(reset,clkdiv) begin if(reset='1')then sq<=(others=>'0'); elsif(clkdiv'event and clkdiv='1')then sq<=not sq; end if; end process; end Behavioral;

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ANKIT RATHI STAIRCASE WAVE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity staircase_wave is Port ( reset : in std_logic; clk : in std_logic; d0 : inout std_logic_vector(11 downto 0)); end staircase_wave; architecture Behavioral of staircase_wave is signal clk_div:std_logic_vector(50 downto 0); signal clkdiv:std_logic; begin process(reset,clk) begin if reset='1' then clk_div<=(others=>'0'); elsif(clk'event and clk='1')then clk_div<=clk_div+1; end if; end process; clkdiv<=clk_div(1); process(reset,clkdiv) begin if(reset='1')then d0<=(others=>'0'); elsif(clkdiv'event and clkdiv='1')then d0<=d0+333; end if; end process; end Behavioral;

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ANKIT RATHI TRIANGULAR WAVE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity triangular_wave is Port ( reset : in std_logic; clk : in std_logic; d0 : inout std_logic_vector(11 downto 0)); end triangular_wave; architecture Behavioral of triangular_wave is signal s1:std_logic_vector(25 downto 1); signal s2:std_logic; signal dir:std_logic:='1'; begin process(reset,clk) begin if(reset='1')then s1<=(others=>'0'); elsif(clk'event and clk='1')then s1<=s1+1; end if; end process; s2<=s1(1); process(s2,reset) begin if(reset='1')then d0<=(others=>'0'); elsif(s2'event and s2='1')then if(dir='1')then d0<=d0+1; else d0<=d0-1; end if; end if; if(d0>"111111111101")then dir<='0'; elsif(d0<"000000000000")then dir<='1'; end if; end process; end Behavioral;

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ANKIT RATHI SINE WAVE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sinewave is Port ( clk : in std_logic; reset : in std_logic; dac_out : out std_logic_vector(0 to 7)); end sinewave; architecture Behavioral of sinewave is signal temp:std_logic_vector(3 downto 0); signal counter:std_logic_vector(0 to 7); signal en:std_logic; begin process(clk) begin if rising_edge(clk) then temp<=temp+1; end if; end process; process(temp(3)) begin if(reset='1')then counter<="00000000"; elsif rising_edge(temp(3))then if (counter<240 and en='0')then counter<=counter+40; en<='0'; elsif(counter=0)then en<='0'; else en<='1'; counter<=counter-40; end if; end if; end process; dac_out<=counter; end Behavioral;

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ANKIT RATHI DISPLAYING HELP ON THE 7 SEGMENT DISPLAY. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity display_help is Port ( clk : in std_logic; reset : in std_logic; seg : out std_logic_vector(6 downto 0); d : inout std_logic_vector(3 downto 0)); end display_help; architecture Behavioral of display_help is signal clk_div:std_logic_vector(21 downto 0); signal clkdiv:std_logic_vector(1 downto 0); begin process(clk,reset) begin if(reset='1')then clk_div<=(others=>'0'); elsif(clk'event and clk='1')then clk_div<=clk_div+1; end if; end process; clkdiv<=clk_div(12 downto 11); process(clkdiv) begin case clkdiv is when "00" => d <= "1000"; when "01" => d <= "0100"; when "10" => d <= "0010"; when others => d <= "0001"; end case; end process; seg<="1110110" when d="1000" else "1111001" when d="0100" else "0111000" when d="0010" else "1110011"; end Behavioral;

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