Problem Specification

The meteorological department receives image data from satellite at fixed, reasonably long intervals. The image is a 7-bit grayscale bitmap of size 8x8. What this means is that the image is composed of 8x8 pixels, with each pixel value varying from 0 (for black) to 127 (for white). The receiving station receives this bitmap data through an 8-bit input port. The MSB of this data is always zero since the maximum value of an individual pixel is 127. The receiving station has to transmit this data to the lab for analysis. Since the image does not differ much between successive receptions, hence it is wasteful to transmit the received data as it is over the communication channel. Instead, 2 consecutive frames are stored and information regarding a given pixel is transmitted only if its value has changed with respect to its previous value. This reduces the volume of communication since only the incremental changes in the image are actually transmitted. The changes in data are encoded using Hamming code and then transmitted over a serial link. On the other side (the lab), this encoded data is received over the serial link. The data is decoded and error detection and correction is done on this decoded data (Assume that only single bit errors may occur). This incremental data is then used to reconstruct the image that was originally sent by the satellite.

System Architecture

Transmitter Subsystem at Receiving Station

Receiving Subsystem at Lab

Frame Buffer Controller Subsystem

This subsystem consists of the following components 1. Two frame buffers. One of the frame buffers will store the previous image data and the other one will store the incoming image data. Each of the frame buffers will be of size 8x8 with a word size of 8 bits. 2. The controller itself. This controller is responsible for filling the current frame buffer with the incoming data. Once the complete data for the current image is received, it then has to calculate the difference in pixel values for each of the pixels. The controller will have an inbuilt DMA controller as well, which will be used to transfer the differential image data to the memory from where the transmission subsystem can take over.

Transmission Subsystem at the Receiving Station

This subsystem chiefly consists of the following components 1. The data compressor. This component goes through a well defined area of the memory where the differential data has been stored and isolates all those entries which have a non-zero difference. On encountering each such value, it populates a data packet of size 14 bytes. The format of the data packet is discussed later. 2. The Hamming Code generator. This component operates on the data packet created by the data compressor. This will use the (18, 14) Hamming Code (discussed later) to generate a final data packet of 18 bits. 3. This 18-bit data will then be given to the Asynchronous transmitter which will then transmit this data over the communication channel (Protocol discussed later)

Main Controller Subsystem

This subsystem is responsible for overall control of the receiving and transmitting subsystem. The data feed received from the satellite is not under the control of the main controller. The frame buffer controller takes care of this. Whenever the current frame buffer is full (i.e. complete image data has been received), the frame buffer controller requests the main controller for DMA. On receiving the bus grant, it transfers the differential image data to a well defined area in the memory. On completing the data transfer, the FBC relinquishes control of the memory. After the bus has been released, the main controller then signals the data compressor to start its processing. This requires the use of the bus to transfer non-zero differences to the internal buffer inside the data compressor. Whenever the data compressor detects a non-zero differential, it immediately transfers the differential data to its internal buffer and creates a packet which is then passed on to the Hamming Code Generator. The Hamming Code Generator in turn creates the final packet to be sent and sends it over the channel with the help of the asynchronous transmitter. During this time, the frame buffer can get filled up again since it does not require the use of the bus.

Receiver Subsystem at the lab

The receiver subsystem is a complement of the transmission subsystem. This subsystem consists of the following components 1. The Asynchronous receiver. This receives serial data over the communication channel. This data is then grouped together in packets of 18 bits to reconstruct the original packet which was transmitted by the transmitter. 2. The error detector/corrector. Assuming that only single bit errors may occur during the transmission of data, this component detects if any transmission error has occurred and if it has, then it corrects the data. The additional hamming bits are stripped and the original 14-bit data packet is reconstructed. 3. The data expander. This component then populates a well defined area of the memory with the differential data. All locations for which there is no differential data received are set to 0 to indicate that there has been no change in pixel values for those locations.

Bus and Memory Organization

The bus is an address/data multiplexed 8-bit bus. The same bus is used to carry address information as well as data. The differentiation between whether the given data currently on the bus represents an address or data is based on the control signal ALE (Address Latch Enable) which when high signals that the current contents of the bus represent an address. The memory is composed of 8-bit words. The total memory addressable by the 8-bit address bus is 256 bytes. This memory is divided into 4 banks, Bank 0 to 3. Bank 0 contains the ROM while banks 1 to 3 are RAM banks. Each bank is selected by the higher 2 bits of the address bus (A7 A6) and the remaining bits of the address bus select a single word within the selected bank. Memory writes occur in the following sequence 1. In the first clock cycle, the ALE signal is held at high. At the same time, the 8-bit address is put on the bus. The signal ALE activates an Address Latch which latches on to the address at the negedge. 2. In the second clock cycle, the ALE is de-asserted and the data is loaded onto the bus. At the same time the signal MEMW is asserted to indicate that data is to be written. At the negedge, this data then gets stored to the memory location whose address had been latched in the previous cycle Memory reads also occur in a similar fashion 1. In the first clock cycle, ALE is asserted and the 8-bit address is put on the bus. This address is then latched by the address latch at the negedge. 2. In the second clock cycle, ALE is de-asserted and the MEMR signal is asserted to indicate that data is to be read from the memory. The data in the memory

location whose address had been latched earlier is then transferred to the data bus at the negedge.

Memory Organization

Frame Buffer Subsystem Operation

The frame buffer subsystem operates as follows 1. On receiving a reset both frame buffers are filled with 0s. Also the current memory bank is set to 1. 2. FB0Sel is asserted and IORead is also asserted. As a result, frame buffer 0 is selected to be the active frame buffer and the incoming data is also enabled. 3. For the next 64 clock cycles, FB0Sel and IORead remain asserted. In each clock cycle in this period, one of the locations of the frame buffer is filled with the incoming 8-bit data. 4. At the end of 64 clock cycles, IORead is de-asserted and the DMA Controller operation begins. HOLD signal is also asserted. 5. In the next clock cycle, the HLDA signal is received, which indicates that the subsystem can now take control of the bus. 6. The counter is loaded with the initial value of 0, and at the same time, the current memory bank to write to is chosen as the (previous + 1) value

7. The address is generated as the concatenation of the bank select and the counter value. The counter increments every alternate clock cycle (since data is transmitted in the intermediate clock cycle) 8. In the first clock cycle, ALE is asserted and the concatenation is loaded onto the bus. 9. In the second clock cycle, ALE is de-asserted, MEMW is asserted and the data bus is loaded with the difference of the frame buffer values (current value previous value). 10. This pair of activity continues for 64 * 2 clock cycles at the end of which data has been completely transferred to the selected memory bank. 11. HOLD signal is now de-asserted indicating that the DMA controller is done with the transfer of data. 12. In the next cycle HLDA is de-asserted by the main controller. During this cycle, IORead is asserted and FB0Sel is de-asserted so that incoming data will be directed to the other frame buffer. 13. Now the process continues as before.

Main Controller Operation

The main controller operates as follows 1. Whenever it receives a reset, it sends a reset to all the peripherals. Also the current memory bank is set to 1. 2. Whenever it receives a HOLD, it sends a HLDA in the next clock cycle. Similarly when HOLD is de-asserted, HLDA is de-asserted in the next clock cycle. 3. When the HOLD is de-asserted, then it means that the data has been transferred to the current memory bank and now it needs to be transferred to the transmission subsystem. So the counter is loaded with an initial value 0, ALE is asserted and the concatenation of the memory bank value and the counter value is loaded on to the bus. 4. In the next clock cycle MEMR is asserted and thus the bus is loaded with the contents of the currently selected memory location. The MEMR also enables the compressor to read the data on the bus. 5. This sequence continues for the next 64 clock cycles when the entire data is transferred. 6. At the end of these (64 * 2) clock cycles, the memory bank counter is incremented.

System Verilog Features to be used

1. All connections to be made using .* or .name

2. Design re-usable components using parameters and parameter types. This is especially true for general purpose blocks like the subtractor, the comparator etc 3. Use FSMs for modeling activities that have a well-defined sequence. Also use enums to represent the various states of the FSM. 4. Use structs and unions. The bus for example, will be a struct consisting of the data/address bus and the control bus. The data/address bus itself is a union of the data and address buses since the same bus is multiplexed to carry address and data as well. The control bus again is a struct made up of the individual control signals. 5. The array types have to be designed such that the packed and unpacked dimensions represent the way the array is going to be handled. For example, the memory would be designed as an unpacked array of bytes, which in itself would be a packed array of bits. 6. Use casting wherever required. For example, the subtractor would need to convert the numbers into a signed format before subtraction. Also the logic that determines the next memory bank to be selected should be designed to increment an enum. 7. Use the always_latch, always_comb and always_ff constructs to indicate the kind of logic that is going to be created inside. 8. Use unique and priority keywords wherever needed.

Transmission Subsystem Operation

The transmission subsystem functions as follows 1. Whenever the main controller asserts the MEMR on the posedge of the clock, the data bus is read on the negedge of the clock. At the same time the counter is incremented to keep track of the current offset in the memory bank. 2. The data that is latched is then compared with a comparator to determine whether the difference is zero or not. If the difference is zero, then nothing needs to be done. 3. If the difference is non-zero, then the row and column information is calculated as follows : Row = counter / 8 Column is counter % 8 4. A packet with the following format is constructed (3 bits row information) (3 bits column information) (8 bits difference value) 5. This packet is given to the hamming code generator which creates the final packet to be transmitted as follows

H1 H2 H3 H4 R1 R2 R3 C1 C2 C3 D1 D2 D3 D4 D5 D6 D7 D8 Where H1 = Exor (R1 H2 = Exor (R2 H3 = Exor (C1 H4 = Exor (D2

R3 C2 C2 D1 D3 D5 D7) R3 C3 D1 D4 D5 D8) C2 C3 D1 D2 D6 D7 D8) D3 D4 D5 D6 D7 D8)

6. This data is then passed on to the Asynchronous Transmitter which works at a frequency 25 times that of the normal clock. The operation of the transmitter is described below.

Asynchronous Transmitter Operation

The asynchronous transmitter operates as follows. 1. When there is no transmission of data, the communication channel is kept at a logic 1 2. Whenever, there is a new frame to be transmitted, the channel is brought to logic 0 for 2 clock cycles. This tells the receiver that new frame information is starting. 3. After this, the channel is kept to 0 for an additional one clock cycle, to allow the receiver to synchronize. 4. Next, the 18 bits of data are transmitted, one at each clock pulse. 5. At the end of this, an additional 0 is transmitted to indicate the end of the data. 6. Next clock cycle, the channel is again brought to logic 1. 7. This continues till all data has been transmitted. 8. When the entire frame data has been transmitted, two additional zeroes are transmitted to indicate the end of the frame data. The channel is once again brought to logic 1.