Introduction to VHDL

Introduction to VHDL

What is VHDL?
VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit

Introduction to VHDL

Developed in the early 1980s

Method of describing electronic systems for the American Department of Defense

Use for digital design only

Synthesis tools used to create and optimize the implementation

Introduction to VHDL

Electronic Design Process

Introduction to VHDL

Electronic Design Process

In general, VHDL is used with synthesis tools for ASIC and PLD design

Introduction to VHDL

Limitations of VHDL
Digital only, not analogyet Completely dependent upon synthesis tools
Slightly different syntax Not much control on physical hardware layout

Introduction to VHDL

Levels of Abstraction in Digital Design

Each level of abstraction defines how much detail about the design is specified in its description

Introduction to VHDL

Levels of Abstraction in Digital Design

Layout is the lowest level of abstraction Specifies the actual layout of the design on silicon, and may also specify detailed timing information or analog effects

Introduction to VHDL

Levels of Abstraction in Digital Design

Logic level deals with the interconnection of logic gates and registers Layout information and analog effects are ignored Deals with function, architecture, and technology

Introduction to VHDL

Levels of Abstraction in Digital Design

Register Transfer Language VHDL used to define every register in the design Still contains architectural information

Introduction to VHDL

Levels of Abstraction in Digital Design

Behavioral level uses VHDL to describe function of a design, without specifying the architecture of registers Contains as much timing information as a designer requires to represent the function

Introduction to VHDL

Behavioral vs. RTL (Structural)

Behavioral Code describes the functionality and behavior of the function Structural Code describes the actual gate and register level of the function

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Typical Synthesis Design Flow

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VHDL Language Concepts

Concurrency VHDL is able to describe activity that happens in parallel Hierarchy the ability to describe the structure. Also, the ability to mix descriptions of structure with descriptions of behavior Sequential VHDL has statements that execute on after the other in sequence, such as a traditional software language like C Time VHDL allows us to model time

Introduction to VHDL

Libraries
Contains a package or a collection of packages Resource Libraries
Standard Package IEEE developed packages Altera Component packages Any library of design units that are referenced in a design

Working Library
Library into which the unit is being compiled

Introduction to VHDL

Model Referencing of Libraries/Packages

All packages must be compiled Implicit Libraries
Work STD
Note: Items in these packages do not need to be referenced, they are implied

LIBRARY Clause
Defines the library name that can be reference Is a symbolic name to path/directory Defined by the compiler

USE Clause
Specifies the package and object in the library that you have specified in the library clause

Introduction to VHDL

Libraries

LIBRARY std;
Contains the following packages
Standard (Types: Bit, Boolean, Integer, Real, and Time. All operator functions to support types) Textio (File operations)

An implicit library (built-in)

Does not need to be referenced

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Libraries

LIBRARY ieee;
Contains the following packages:
std_logic_1164 (std_logic types & related functions) std_logic_arith (arithmetic functions std_logic_signed (signed arithmetic functions) std_logic_unsigned (unsigned arithmetic functions)

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Libraries in VHDL

LIBRARY <any_name>; USE <any_name>.<package_name>.all;

LIBRARY ieee; USE ieee.std_logic_1164.all;

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Entity
The main VHDL building block Describes the interface to a hierarchical block without defining behavior

Equivalent to a symbol in a schematic design

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The 2-to-1 Multiplexer

d0 f d1 s

ENTITY mux2to1 IS PORT( d0, d1, s f END mux2to1;

:IN STD_LOGIC; :OUT STD_LOGIC);

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Architecture
The behavior of an entity is the architecture Architecture is described using behavioral code or structural code

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d0 f d1 s

Behaviorally If s=0, d0 passes through and f=d0 If s=1, d1 passes through and f=d1

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d0 f d1 s

ARCHITECTURE behavior OF mux2to1 IS BEGIN WITH s SELECT f <= d0 WHEN '0', d1 WHEN OTHERS; END behavior;

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d0 f d1 s

Structurally
d0

f d1

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d0

d0 f d1 s
f f d1

s s

ARCHITECTURE structure OF mux2to1 IS BEGIN f <= (d0 AND (NOT s)) OR (d1 AND s); END structure;

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Hierarchy

Entities can be pieced together to form larger structures The interconnection of the entities and their architectures describe the hierarchy A design entity instantiates lower level design entities, referred to as components

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Hierarchy A good example is the construction of a 4-to-1 mux from 2 2-to-1 muxes being used as components
d0 d1 f d2

d3

s1

s0

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The 4-to-1 Mux

d0 d0 d1

d1

d2 d3

d2 d3
s1 s0

ENTITY mux4to1 IS PORT( d0, d1, d2, d3, s0, s1 f END mux4to1;

:IN STD_LOGIC; :OUT STD_LOGIC);

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d0 d1 d2 d3 f

s1 s0

ENTITY mux4to1 IS PORT(w0, w1, w2, w3, sel0, sel1 f END mux4to1;

:IN STD_LOGIC; :OUT STD_LOGIC);

ARCHITECTURE structure OF mux4to1 IS SIGNAL I1, I2 :STD_LOGIC; COMPONENT mux2to1 PORT(d0, d1, s :IN STD_LOGIC; f :OUT STD_LOGIC); END COMPONENT; BEGIN u1:mux2to1 PORT MAP(w0, w1, sel0, I1); u2:mux2to1 PORT MAP(w2, w3, sel0, I2); u3:mux2to1 PORT MAP(I1, I2, sel1, f); END structure;

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Configurations
It is possible for an entity to have multiple architectures, thus, a specific architecture must be assigned to the entity for proper compilation and simulation Not required! If no configuration is given, the most recently compiled architecture of an entity will be used

Introduction to VHDL

Configurations
Theory behind the configuration

Introduction to VHDL

Configurations

Introduction to VHDL

Configurations

ENTITY mux2to1 IS PORT( d0, d1, s :IN f END mux2to1;

STD_LOGIC; :OUT STD_LOGIC);

ARCHITECTURE behavior OF mux2to1 IS BEGIN WITH s SELECT f <= d0 WHEN '0', d1 WHEN OTHERS; END behavior; CONFIGURATION mux2to1_config OF mux2to1 IS FOR behavior END FOR; END mux2to1_config;

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Processes
A process is a region of VHDL code that executes SEQUENTIALLY Exists inside the architecture

Multiple processes execute with each other concurrently

Introduction to VHDL

Processes
ENTITY orgate IS PORT (a,b : in bit; z : out bit); END orgate; ARCHITECTURE Behavior OR orgate IS BEGIN or_func: PROCESS (a,b) BEGIN IF (a='1' OR b='1') THEN z <= '1'; ELSE z <= '0'; END IF; END PROCESS or_func; END Behavior

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Packages
A package contains a collection of definitions that may be referenced by many designs at the same time Usage is similar to that of a component Separate design file that exists outside of the other design units seen thus far, such as entities and architectures

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Back to the 4-to-1 Mux example

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux2to1 IS PORT (d0, d1, s :IN STD_LOGIC; f :OUT STD_LOGIC); END mux2to1; ARCHITECTURE LogicFunc OF mux2to1 IS BEGIN f <= (d0 AND (NOT s)) OR (d1 AND s); END LogicFunc; LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE mux2to1_package IS COMPONENT mux2to1 PORT (d0, d1, s :IN STD_LOGIC; f :OUT STD_LOGIC); END COMPONENT; END mux2to1_package; LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.mux2to1_package.all; ENTITY mux4to1 IS PORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC; f :OUT STD_LOGIC); END mux4to1; ARCHITECTURE structure OF mux4to1 IS SIGNAL I1, I2 :STD_LOGIC; BEGIN u1:mux2to1 PORT MAP(w0, w1, sel0, I1); u2:mux2to1 PORT MAP(w2, w3, sel0, I2); u3:mux2to1 PORT MAP(I1, I2, sel1, f); END structure;

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THE COMPLETE IDEA

A complete design hierarchy is defined by multiple entities, which have at least one architecture

Introduction to VHDL

THE COMPLETE IDEA

Each of these entities and architectures will reference standards and types from within a stated library

Introduction to VHDL

THE COMPLETE IDEA

Many of these entities and architectures will reference one or more packages of common definitions

Introduction to VHDL

THE COMPLETE IDEA

The link between each level of hierarchy, and the specification as to which architecture will be used is provided by the configuration

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Types
VHDL defines that every signal must have a data type associated with it when the signal is declared.
The type defines a set of values, and an assignment to that signal must always be of a value defined by that set

Signals are generally declared either in the PORT ENTITY fulladd IS entity, or within an explicit signal section of: an bit; PORT (a,b,Cin IN declaration inOUT bit); sum, Carry : an architecture.
END fulladd; ARCHITECTURE struct OF fulladd IS SIGNAL n_sum : bit; -- other declarations BEGIN -- Code END struct;

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Types When an assignment is made to a signal, the types on either side of the signal assignment operator must match up
ENTITY fulladd IS PORT (a,b,Cin : IN bit; Sum, Carry : OUT bit); END fulladd; ARCHITECTURE Logic OF fulladd IS BEGIN Sum <= a XOR b; END Logic;

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Predefined Types

PACKAGE standard IS TYPE boolean IS (true, false); TYPE bit IS (0, 1) TYPE character IS (-- ascii set) TYPE integer IS range implementation_defined; TYPE real IS range implementation_defined; -- bit_vector, string, time END standard;

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Predefined Types

Introduction to VHDL

Predefined Types There are some limitations to the predefined standard type

Signals are only allowed to be one of the types specified (i.e. bit, string, boolean, etc.)
More powerful type is defined by the IEEE standard 1164

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Standard Logic represented by IEEE 1164

In general, std_logic should be used ALL OF THE TIME

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Arrays

An array is a collection of objects Each object is of the same type Two standard array types are bit_vectors and strings

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Arrays

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Arrays Assignment

Assignment is by position number, not by index number There is no concept of a most significant bit in the language

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Arrays Assignment

A slice of an array may be referenced, including a single element The direction of the slice (i.e. to or downto) must match the direction in which the array is declared

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Arrays and Concatenation

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Arrays and Aggregates

Another method of assigning elements to an array is with an aggregate Uses round brackets with elements separated by a comma

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Arrays Assigned by Name

It is possible to specify the element of the array by name, as well as by position The range of an array can be specified, as long as the same value is being assigned to each element in the range

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Arrays Assigned by Name

Aggregates have the ability to use the others statement, which will assign a value to all other elements of the array that have not been specified Not all synthesis tools support the use of aggregates, so concatenation may be required

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User Defined Types

Types can also be defined by the user A user defined type is known as an enumerated type Types are most commonly defined inside a package, architecture, or process Most synthesis tools are able to synthesize VHDL containing enumerated types

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User Defined Types

Syntax for declaring a user defined type

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User Defined Types

Having defined a type, signals can be defined of that type SIGNAL state cannot be assigned anything which is not of type my_state

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User Defined Types

Synthesis tools build logic from a signal which is of an enumerated type Usually the minimum number of bits required to represent the number of possible values

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VHDL Operators
There are 3 varieties of operators: logical, relational, and arithmetic

Logical operators are and, or, etc.

Relational operators are used to compare different values Arithmetic operators are used for performing mathematics

Introduction to VHDL

VHDL Operators - Logical

Includes AND, OR, NAND, NOR, and XOR All have the same precedence Execute from left to right NOT has a higher precedence, and therefore executes before other operators in an expression Logical operations can only be applied to arrays of the same type and length Matching elements in arrays is by POSITION!

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VHDL Operators - Relational

Relational operators return a boolean value Most often used within if-then-else statements to control the flow of code depending on different conditions

Introduction to VHDL

VHDL Operators - Relational

The rules for using relational operators are that the operands must be of the same type For an array, the operands can be of different lengths; the operands are aligned to the left, and compared to the right This makes 111 greater than 1011 !

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VHDL Operators - Arithmetic

Predefined for types integer, real (except for modulus and remainder), and type time. As vectors do not represent a numerical value, the arithmetic operators cannot be used with types bit_vector or std_logic_vector

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More Sequential Statements in VHDL

Processes If-then-else statements Case statements

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Back to the Process

Sequentially executing statements Syntax: Optional label, the key word PROCESS, and a sensitivity list

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Back to the Process

A process does execute continuously It is invoked when one of the signals in its sensitivity list changes value, or has an event Sensitivity lists MUST BE COMPLETE so that all processes execute properly!

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The IF Statement

The if statement tests a condition, and executes a different set of statements depending on the result The two basic forms are the if-then and the ifthen-else statements Note that there is a space between the end and the if

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The IF-ELSIF Statement

The IF-ELSEIF statement allows a series of conditions to be tested, and the first condition that is true will cause the statements that follow to be executed Cannot happen for more than one branch of the structure The flow then passes to the END IF statement at the bottom

Introduction to VHDL

The IF-ELSIF Statement

The order in which statements are written in the IF-ELSIF structure is very important More than one of the conditions may be true The first true condition causes its set of statements to be executed

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The IF-ELSIF Example

If X has the value 0000, then both sets of conditions are true Since x = 0000 is tested first, z will be assigned the value of a IF-ELSIF statements have a built in priority

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The CASE Statement

The CASE statement considers all the possible values that an object can take, and executes a different branch depending on the current value of the object

Introduction to VHDL

The CASE Statement

Values cannot be specified more than once! All values MUST be specified, either explicitly, or with an others clause

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The FOR Loop

A FOR loop will iterate around a loop a fixed number of times while incrementing a value through a fixed range In this example, the variable i is being incremented from 0 to 5, making 6 passes around the loop There is no need to declare the loop variable in any other part of the code; it is implicitly declared when it is used in the FOR loop