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8051

8051

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Published by: api-3697683 on Oct 14, 2008
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03/18/2014

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3-3
TQFP
23
1
INDEX
CORNER
34
P1.0
V
C
C
P1.1
P1.2
P1.4
P1.3
NC
42
43
40
41
654
44
32
26
25
28
27
24
1819202122
P1.7
P1.6
P1.5
NC
78
910
11
121314151617
29
30
3938373635
33
32
31
NC
PSEN
XTAL1
G
ND
XTAL2
G
ND
P0.0
(AD0)
ALE
(
)
P3.7
RD
EA
(
)
P3.6
W
R
(RXD) P3.0
P0.7 (AD7)
P2.6 (A14)
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3
(AD3)
P0.2
(AD2)
P0.1
(AD1)
(
) P3.2
INT0
(TXD) P3.1
(T1) P3.5
(
) P3.3
INT1
(T0) P3.4
P2.7 (A15)
(A11)
P2.3
(A12)
P2.4
(A10)
P2.2
(A9)
P2.1
(A8)
P2.0
RST
P2.5 (A13)
Features

\u2022Compatible with MCS-51\u2122 Products
\u20224K Bytes of Factory Programmable QuickFlash\u2122 Memory
\u2022Fully Static Operation: 0 Hz to 20 MHz
\u2022Three-Level Program Memory Lock
\u2022128 x 8-Bit Internal RAM
\u202232 Programmable I/O Lines
\u2022Two 16-Bit Timer/Counters
\u2022Six Interrupt Sources
\u2022Programmable Serial Channel
\u2022Low Power Idle and Power Down Modes

Description

The AT80F51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of QuickFlash Memory. The device is manufactured using Atmel\u2019s high density nonvolatile memory technology and is compatible with the industry standard MCS- 51\u2122 instruction set and pinout. The on-chip QuickFlash allows custom codes to be quickly programmed in the factory. By combining a versatile 8-bit CPU with Quick- Flash on a monolithic chip, the Atmel AT80F51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control appli- cations.

PDIP
P1.0
VCC
P1.1
P0.0 (AD0)
P1.2
(
) P3.2
INT0
ALE
(
) P3.7
RD
P2.3 (A11)
(TXD) P3.1
EA
(
) P3.6
WR
P2.4 (A12)
(RXD) P3.0
P0.7 (AD7)
(T1) P3.5
P2.6 (A14)
RST
P0.6 (AD6)
P1.7
P0.5 (AD5)
P1.6
P0.4 (AD4)
P1.5
P0.3 (AD3)
P1.4
P0.2 (AD2)
P1.3
P0.1 (AD1)
(
) P3.3
INT1
PSEN
XTAL2
P2.2 (A10)
(T0) P3.4
P2.7 (A15)
XTAL1
P2.1 (A9)
GND
P2.0 (A8)
P2.5 (A13)
20
19
18
17
16
15
123456
78910

11 12 13 14

21
22
23
24
25
26

40 39 38

37
36
35
34
33
32

31 30 29 28 27

0979A-A\u201312/97
(continued)

8-Bit
Microcontroller
with 4K Bytes
QuickFlash\u2122
Memory

AT80F51
Pin Configurations
PLCC
P1.0
V
C
C
P1.1
P0.0
(AD0)
P1.2
ALE
(
)
P3.7
RD
XTAL1
EA
(
)
P3.6
W
R
G
ND
(RXD) P3.0
P0.7 (AD7)
P2.6 (A14)
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3
(AD3)
P1.4
P0.2
(AD2)
P1.3
P0.1
(AD1)
PSEN
XTAL2
(
) P3.2
INT0
(TXD) P3.1
(T1) P3.5
(
) P3.3
INT1
(T0) P3.4
P2.7 (A15)
(A11)
P2.3
(A12)
P2.4
(A10)
P2.2
(A9)
P2.1
(A8)
P2.0
NC
23
1
RST
P1.7
P1.6
P1.5
INDEX
CORNER
NC
NC
P2.5 (A13)
34
NC
42
43
40
41
65 4
44
32
26
25
28
27
181920
24
2122
78910

11 12 13 14 15 16 17

29
30
39
38
37
36
35

33 32 31

AT80F51
3-4
Block Diagram
PORT 2 DRIVERS
PORT 2
LATCH
P2.0 - P2.7
QUICK
FLASH
PORT 0
LATCH
RAM

PROGRAM
ADDRESS
REGISTER

BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
RAM ADDR.
REGISTER
INSTRUCTION
REGISTER
B
REGISTER
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
STACK
POINTER
ACC
TMP2
TMP1
ALU
PSW

TIMING
AND
CONTROL

PORT 3
LATCH
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1
LATCH
PORT 1 DRIVERS
P1.0 - P1.7
OSC
GND
VCC
PSEN
ALE
EA
RST
PORT 0 DRIVERS
P0.0 - P0.7
AT80F51
3-5

The AT80F51 provides the following standard features: 4K bytes of QuickFlash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt archi- tecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT80F51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM con- tents but freezes the oscillator disabling all other chip func- tions until the next hardware reset.

Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs.

Port 0 may also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode P0 has internal pul- lups.

Port 0 also outputs the code bytes during program verifica- tion. External pullups are required during program verifica- tion.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during
QuickFlash verification.
Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash verification.
Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special features
of the AT80F51 as listed below:
Port 3 also receives some control signals for QuickFlash
verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external tim- ing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Mem- ory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur- ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT80F51 is executing code from external pro-
gram memory, PSEN is activated twice each machine
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)

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