The need to reduce power consumption\u2014long recognized as a signi\ue000cant design issue\u2014becomes more
critical as larger, \ue001aster ICs go into portable applications. As a result, techniques \ue001or managing power
throughout the design fow are evolving to assure that all parts o\ue001 the product receive power properly and
e\ue001\ue000ciently, and that the product is reliable. Techniques such as multi-voltage islands and dynamic scaling
o\ue001 both clock \ue001requency and threshold voltage help conserve battery power in portable applications, while
delivering high per\ue001ormance.
Perhaps more critically, increases in system-on-chip (SoC) size and speed have led to power consumption
challenges across a broad range o\ue001 designs that have not been viewed traditionally as supply-limited. In
these designs, heat dissipation and reliability issues such as electromigration and IR drop have become
vitally important. (For in\ue001ormation on dealing with power-related reliability issues, please consult the
Synopsys Pro\ue001essional Services\u2019 White paper \u201cDesign Planning Strategies to Improve Physical Design
Flows\u2014Floorplanning and Power Planning\u201d http://www.synopsys.com/cgi-bin/sps/wp/dps/paper1.cgi)
Power issues in mainstream deep submicron designs may limit \ue001unctionality or per\ue001ormance and severely
a\ue001\ue001ect manu\ue001acturability and yield. Higher power dissipation increases junction temperature, which slows
transistors and increases interconnect resistance. Design techniques aimed at improving per\ue001ormance
may there\ue001ore \ue001all short i\ue001 power is not considered. Lower-than-expected per\ue001ormance decreases device
yield. Additionally, higher power dissipation requires more system-level measures \ue001or thermal management.
In general, these power issues are increasing SoC and system costs. Managing power consumption at
appropriate points in the SoC design fow keeps these costs under control.
The total power consumed by a chip equals dynamic power plus static power. Dynamic power is the power consumed in switching logic states, both internal to the cells (internal power) and \ue001or driving the chip\u2019s nets and external loads (switching power):
Dynamic power = CV2F
where C is the load, V is the voltage swing and F is the number o\ue001 logic-state transitions.
As semiconductor structures become smaller, device and interconnect capacitances decrease, allowing \ue001or
Although transistors have some reverse-biased diode leakage \ue001rom drain to substrate, the larger portion o\ue001 leakage power is due to the sub-threshold current through a transistor that is turned o\ue001\ue001. This sub-threshold current results \ue001rom the conduction between source and drain through the transistor channel.
The sub-threshold leakage current is problematic because it increases as transistor threshold voltages
(Vth) decrease. In \ue001act, the move to 130 nanometer (nm) and beyond may boost leakage power as high as
50 percent o\ue001 the total chip power (Figure 1). Increased leakage power helps to exponentially increase
reliability related \ue001ailures in chips (even in standby).
Figure 1: Increase in leakage power\u2014Bringing down transistor threshold voltages helps decrease dynamic
power but increases sub-threshold leakage current. A power-aware design \ue000ow is thus needed to meet timing
requirements and keep power consumption within acceptable limits. Source: Intel. Published in IC Insights Inc.
2003 Technology Trends.
As CMOS technologies scale down, the main approach \ue001or reducing power has been to scale down the
supply voltage VDD. Voltage scaling is a good technique \ue001or controlling a chip\u2019s dynamic power because o\ue001
the quadratic e\ue001\ue001ect o\ue001 voltage on power consumption. However, just reducing the power supply degrades
circuit speed because the switching delay time is proportional to the load capacitance and the ratio Vth/
VDD. To maintain su\ue001\ue000cient drive strength \ue001or \ue001ast switching, Vth must decrease in proportion to VDD. This
relationship leads to the leakage power increase. Fortunately, a power-aware design fow helps balance
timing requirements with various power goals.
The higher the level o\ue001 design abstraction, the greater the infuence on power consumption. At the system
and algorithm levels, \ue001or example, using a parallel approach rather than a serial implementation reduces
clock \ue001requencies, which helps to decrease power consumption signi\ue000cantly. The lower power o\ue001 the parallel
approach may come at the expense o\ue001 somewhat greater area or slower per\ue001ormance.
MHz. Additionally, the supply voltage was reduced \ue001rom 1.8V to 1.25V. The parallel processing logic was much larger than the serial processing equivalent, but the logic\u2019s reduced voltage and operating \ue001requency reduced the power consumption by 75 percent. This parallel approach was able to save power because power has a squaring \ue001unction to voltage and only a linear \ue001unction \ue001or \ue001requency and switching. In other designs, the area penalty has been small but the power savings signi\ue000cant, so it is worth exploring the tradeo\ue001\ue001s.
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