Published in IET Computers & Digital Techniques

Received on 10th October 2008

Revised on 27th July 2009
doi: 10.1049/iet-cdt.2008.0130
ISSN 1751-8601
Error control combining Hamming and product
codes for energy efcient nanoscale on-chip
interconnects
B. Fu P. Ampadu
ECE Department, University of Rochester, Rochester, NY 14627, USA
E-mail: ampadu@ece.rochester.edu
Abstract: The authors propose an energy efcient error control scheme that combines simple Hamming codes
with powerful product codes for deeply scaled on-chip interconnects. By using Hamming codes in low-noise
environments and product codes in high-noise environments, the proposed method achieves high reliability
while maintaining energy efciency; further, hardware sharing is introduced to reduce system overhead. To
achieve the same reliability in noisy environments, the proposed method uses a lower swing voltage than a
conventional Hamming implementation, resulting in a 30% energy reduction; an energy reduction of up to
40% is achieved compared to a multi-error correcting BCH code.
1 Introduction
In nanoscale technologies, on-chip interconnect errors
caused by supply voltage uctuation, crosstalk, process
variation, radiation and electromagnetic interference
become more common [15]. Simple linear block codes,
such as single-error correcting (SEC) codes have been
widely used [69]. Unfortunately, multiple random and
burst errors (a burst error is dened as errors in multiple
adjacent wires) occur more frequently as technology scales
[5, 6]; thus, previous approaches using SEC codes are
ineffective. More powerful codes can address multiple
errors, at the cost of large energy overhead. However, a
large error correction capability may not always be needed,
because noise conditions vary with different environmental
factors (e.g. temperature) and operating conditions (e.g.
supply voltage). By appropriately providing error control
based on noise conditions or system requirements, high
reliability and energy efciency is achieved [1013].
In this paper, we propose an error control scheme
combining Hamming codes with product codes to achieve
both reliability and energy efciency. The proposed method
can provide adjustable code strength according to noise
environments. Further, in order to reduce the system
overhead, a hardware sharing method is introduced. The
remainder of the paper is organised as follows: Section 2
introduces related work on error control for on-chip
interconnects. Section 3 describes the proposed error
correction scheme. System performance is evaluated in
Section 4. Conclusions are presented in Section 5.
2 Related work
Error control schemes, such as automatic repeat request
(ARQ) [6, 8, 10], forward error correction (FEC) [6, 7,
14, 15] and hybrid ARQ (HARQ) [8, 9], are widely used
to improve reliability in on-chip interconnects. In [6, 9],
cyclic redundancy check (CRC) codes are used to detect
errors, and retransmission is requested once errors are
detected. SEC codes (e.g. Hamming) [69] and duplicate-
add-parity (DAP) codes [7] are used to correct single
errors. In [6, 8, 9], SEC-double-error detecting (DED)
codes (e.g. extended Hamming) are used to perform
HARQ. These works have focused on 1- or 2-bit random
error scenarios; more powerful codes are needed to address
multiple errors. In [14], multiple SEC codes are combined
with an interleaver to address multiple adjacent errors. In
[15], a multiple-error correcting code is constructed by
combining Hamming codes with DAP codes. In [16],
BoseChaudhuri Hocquenghem (BCH) codes are
applied to network-on-chip (NoC) links. The combination
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of two-dimensional Hamming product codes with type-II
hybrid ARQ is proposed to address multiple interconnect
errors in [17].
Each error control scheme has different area, power,
throughput and error correction capability trade-offs.
Congurable error control schemes achieve energy
efciency by dynamically providing appropriate error
control based on noise conditions or system requirements.
In [10], parity check codes, SEC codes and SEC-DED
codes are used for error detection based on the number of
errors found over a xed time window. In [11], a
congurable error control scheme is used to meet different
quality-of-service (QoS) requirements based on the
particular application. In [12], an adaptive error control
scheme using a congurable SEC code and interleaver is
applied to address burst errors. In [13], different error
control schemes are selected according to the fault type.
Hamming codes with interleaving combined with
retransmission are used to handle transient errors, and split
retransmission and spare wires are used to address
intermittent and permanent errors. These methods do not
consider the correction of multiple random errors and burst
errors. In this paper, we combine product codes with
Hamming codes to address multiple errors in varied noise
environments.
3 Error control scheme combining
hamming and product codes
3.1 Multiple error correction using
hamming product codes
Product codes [18], which can be easily realised by
concatenating simple component codes, have a good
protection capability against both random and burst errors.
In product codes, a K-bit input message is arranged into a
k
2
k
1
matrix and encoded row by row and column by
column, as shown in Fig. 1. In our previous work [17], we
proposed combining Hamming product codes with type-II
HARQ [19] to achieve high reliability on-chip
communication when multiple errors are considered. In our
previous work, the transmission of the product codeword is
separated into two steps. First, the original message is
transmitted with row parity check bits. If the error patterns
in the rst transmission are detectable but uncorrectable
(e.g. two errors in a row), the column parity check bits are
transmitted. Multiple errors can be corrected when both
row and column parity check bits are used in the decoding
process.
In Hamming product codes with Type-II HARQ, the
required number of wires is decided by the maximum
number of wires in the rst transmission and the
retransmission. For a K-bit input message, which is
arranged into k
2
rows with length of k
1
[K=k
2
] and
encoded using an extended Hamming code EH(n
1
, k
1
) or
EH(n
2
, k
2
) for each row or column, the number of wires
W
L1
in the rst transmission (original it and row parity
check bits) is expressed as
W
L1
K k
2
r
eh
([K=k
2
]) (1)
where r
eh
([K=k
2
]) is the number of parity check bits added by
the extended Hamming code for the [K=k
2
]-bit row input.
The number of wire W
L2
in the retransmission (column
parity check bits for n
1
([K=k
2
] r
eh
([K=k
2
])) columns)
is expressed as
W
L2
([K=k
2
] r
eh
([K=k
2
])) r
eh
(k
2
) (2)
where r
eh
(k
2
) is the number of parity check bits added by the
extended Hamming code for the k
2
-bit column input.
From (1) and (2), the required number of wires in the link
is a function of the row number k
2
for a given input message
width K. Fig. 2a shows the number of wires in the link for
different input message widths K and the number of rows
in the message k
2
. It can be seen that the number of wires
in the link changes greatly for different k
2
values. For the
number of wires examined in Fig. 2a, a minimum value is
achieved when k
2
is equal to four. Fig. 2b also examines the
codec area with different k
2
values for a 64-bit input
message. The results show that the codec area is smallest at
k
2
4. Thus, to minimise the number of wires in the link
and codec area, k
2
4 is used in the Hamming product
codes design.
3.2 Proposed error control scheme
The core idea of the proposed error control scheme is to
construct a system with adjustable code strength, which can
be dynamically selected according to noise environments or
reliability requirements. Hamming codes have been widely
used in previous work because of their low codec overhead
[69]. As noise environments worsen, Hamming codes are
inefcient to maintain system reliability because of their
low error correction capability. In this paper, we propose
combining Hamming codes with product codes to
construct a congurable error control scheme. The
proposed error control scheme works in two operating
Figure 1 Implementation of product codes for on-chip
interconnects
252 IET Comput. Digit. Tech., 2010, Vol. 4, Iss. 3, pp. 251261
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-cdt.2008.0130
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modes: mode-(a) directly uses Hamming codes in low-noise
environments; and mode-(b) uses product codes for high-
noise environments. The proposed congurable error
control scheme can improve energy efciency for a specied
reliability requirement or varying noise environments by
switching between two operating modes. Directly using
Hamming codes in operating mode-(a) has smaller codec
energy. Also, fewer links lead to smaller link energy
consumption. In operating mode-(b), using product codes
can provide higher reliability.
Fig. 3a shows the concept of the proposed transmitter
design. In low-noise environments, encoder1 is congured
as a Hamming encoder, which uses the whole message as
the input. The encoded message is sent to the receiver
through an interleaver. The interleaver is implemented as
hardwire direct connection with negligible overhead. In
high-noise environments, encoder1 is congured as a
product code component row encoder. The component
encoder consists of multiple Hamming encoders, each
using a part of the message as its input. The interleaved
outputs of congurable encoder1 (original message and row
parity check bits) are sent to the receiver and
simultaneously fed to component encoder2 (column
encoder). The outputs of component encoder2 are saved
into a buffer and transmitted when required. Fig. 2b shows
the concept of the proposed receiver design. Decoder1 can
be congured as a Hamming decoder using the whole
codeword as the input or a product code component
decoder (row decoder). When the proposed error control
scheme is in operating mode-(b), the outputs of
congurable decoder1 are sent to component decoder2,
which is realised using an iterative decoding algorithm
[17]. The congurable control signal is generated by a link
quality monitor [10] or system software [11]. The link
quality monitor can be realised by counting the detected
errors (the syndrome value of decoder1 is non-zero) over a
period of time T
sampling
. The number of detected errors in
the sampling time can be described by
N
error

T
sampling
T
clock
P
detect
(3)
Figure 2 Effects of k
2
selection on the number of wires in the link and codec area
a Number of wires in the link
b Codec area for a 64-bit input message
Figure 3 Proposed error control scheme
a Transmitter
b Receiver
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where T
clock
is the system clock period. P
detect
is
the detectable error probability of the code. Hamming
codes can detect 1- and 2-bit errors. P
detect
can be
estimated by
P
detect
n 1 (1 1)
n1
C
2
n
1
2
(1 1)
n2
(4)
where n is the Hamming codeword width. 1 is the single wire
error probability, which is related to noise conditions. The
length of T
sampling
can be controlled by software. For a xed
T
sampling
and T
clock
, the number of detected errors N
error
depends on noise conditions. To decide the switching
between different operating modes, the number of detected
errors N
error
is compared to a preset threshold value. If the
number of detected errors is greater than the preset value,
operating mode-(b) is selected. When the conguration is
performed by the system software, an interface control
register is needed. The system software can select the
operation modes by setting the control register based on the
application requirement (e.g. if the correctness of operation
is the main concern, mode-(b) is used).
3.2.1 Proposed transmitter design
Fig. 4 shows the implementation of the proposed transmitter
design. In operating mode-(a), the input message is directly
encoded by a Hamming code. In operating mode-(b), the
K-bit input message is arranged into a 4 (K/4) matrix to
construct the product code and each row is encoded with
an extended Hamming code with a (K/4)-bit input. To
reduce the encoder area overhead, the congurable
encoder1 is implemented using a hardware sharing method
presented in our previous work [20]. In this method, the
Hamming encoder with a K-bit input is realised by
combining the outputs of four Hamming encoders, each of
them with a (K/4)-bit input. The following example
demonstrates the hardware sharing method. Consider a 16-
bit input message, which is separated into four rows. Each
row is encoded using an extended
G
1
[I
44
jP
44
]
1 0 0 0 1 1 0 1
0 1 0 0 1 1 1 0
0 0 1 0 1 0 1 1
0 0 0 1 0 1 1 1
_
_
_
_
_

_
(5)
P
T
44

1 1 1 0
1 1 0 1
0 1 1 1
1 0 1 1
_
_
_
_
_
_

M
1 0 1 1
_ _
(6)
G
2
[I
1616
jP
165
] (7)
P
T
165

1 1 1 0
1 1 0 1
0 1 1 1
0 0 0 0
0 0 0 0
.,,.
row a
1 1 1 0
1 1 0 1
0 1 1 1
1 1 1 1
0 0 0 0
.,,.
row b
1 1 1 0
1 1 0 1
0 1 1 1
0 0 0 0
1 1 1 1
.,,.
row c
1 1 1 0
1 1 0 1
0 1 1 1
1 1 1 1
1 1 1 1
.,,.
row d
_
_
_
_
_
_
_
_
_
_
_
_
_

M M M M
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
_
_
_
_
(8)
Hamming code H(8, 4) with the generator matrix in (5). The
parity check bits of each group can be combined to generate
parity check bits of an extended Hamming code H(21, 16)
with the generator matrix in (7), where P
T
165
is transpose
of parity matrix. The hardware implementation of the
H(8, 4) and H(22, 16) encoder is shown in Fig. 5. By using
Figure 4 Implementation of the proposed transmitter design
254 IET Comput. Digit. Tech., 2010, Vol. 4, Iss. 3, pp. 251261
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-cdt.2008.0130
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the hardware sharing method, the congurable encoder1 is
implemented in two stages parity calculation and merge
circuits, as shown in Fig. 4. The parity calculation outputs
can be directly used as the parity check bits of four
Hamming encoders with input width (K/4)-bit or merged
together to generate the parity check bits of a Hamming
encoder with input width K bits.
3.2.2 Proposed receiver design
Fig. 6 shows an implementation of the proposed receiver
design. Decoder1 can be congured as a single Hamming
decoder, which uses the whole codeword as the input, or a
component decoder (row decoder) in product codes. The
component decoder consists of four Hamming decoders
and each decoder uses a part of the codeword as input. The
realisation of congurable decoder1 is divided into three
steps, as shown in Fig. 6. The hardware sharing method
used in transmitter design is implemented for the parity
calculation circuits. The syndrome calculation circuit is an
XOR operation of the parity calculation outputs and the
parity check bits in the codeword. Syndrome calculation1
generates the syndrome vector of operating mode-(a) and
syndrome calculation2 generates the syndrome vector of
operating mode-(b). The syndrome vectors are fed into a
syndrome decoder and error correction circuit. The
syndrome decoder is implemented as an AND tree, whose
inputs are the syndrome value or its inverse. The error
correction is implemented as an XOR gate. A hardware
sharing method is proposed to realise the syndrome
decoder and error correction circuits in this paper. Fig. 7
shows an example of the proposed hardware sharing
method. The 16-bit message is encoded by a Hamming
code H(21, 16) [operating mode-(a)] or four extended
Figure 5 Hardware sharing method to calculate the parity check bits
Figure 6 Implementation of the proposed receiver design
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Hamming code EH(8, 4) [operating mode-(b)]. Four-bit
syndrome vectors are used for each EH(8, 4) code and a
5-bit vector is used for the H(21, 16) code. By properly
selecting the syndrome value and its inverse from the
different operating modes, the syndrome decoder circuits
and error correction circuit can be shared. 1 is assigned as
the extra syndrome bit for each EH(8, 4) code. The
outputs of congurable decoder1 are saved into a receiver
buffer. In operating mode-(a), only the decoded message is
saved. In operating mode-(b), the decoded message and
row parity check bits are both saved. The saved message
and row parity check bits are used to perform an iterative
decoding procedure when the column parity check bits are
transmitted [17].
4 Evaluation of the proposed
error control scheme
The proposed congurable error control scheme can be
employed in NoCs. In this context, the encoder and
decoder circuits are integrated into the NoC routers, as
shown in Fig. 8. Registers are inserted between encoder
and link, and also between link and decoder to allow
pipelined operation. In this section, the performance of the
proposed congurable coding scheme is evaluated in terms
of codec delay, complexity, reliability and energy
consumption. We used a 64-bit input message. The
Hamming code H(71, 64) is used in operating mode-(a). In
operating mode-(b), the 64-bit input message is arranged
into a 4 16 matrix. Each row is encoded using an
extended Hamming code EH(22, 16) and each column is
encoded using an extended Hamming code EH(8, 4). The
total number of wires in the link of the proposed method is
88. In operating mode-(a), only 71 wires are used and the
remaining wires are connected to ground. The proposed
error correction scheme is developed and veried in Verilog
HDL. The encoder and decoder are synthesised using
TSMC 45 nm technology. The delay, area and power of the
encoder and decoder are reported using synopsis design
compiler at 1 GHz clock frequency. The link power is
measured in Cadence Spectre using a 45 nm global link
interconnect model [21], with parameters shown in Table 1.
Simulation results of the proposed method are compared to
directly using Hamming code H(71, 64), a 3-bit error
correction BCH(85, 64), and a ReedSolomon RS(85, 65)
code. Zero padding is applied to meet the length
requirement of RS code. The number of wires in the link
for different coding schemes is shown in Table 2.
Figure 7 Hardware sharing of syndrome decoder and error correction circuits
Figure 8 Implementation of proposed congurable error
control scheme in NoC platform
256 IET Comput. Digit. Tech., 2010, Vol. 4, Iss. 3, pp. 251261
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4.1 Codec delay and area
Table 2 compares the synthesised codec delay of the proposed
scheme to the directly using H(71, 64), BCH(85, 64) and
RS(85, 65). The decoder delay, typically much larger than
encoder delay, is reported here. A three-stage pipelined
process is implemented in operating mode-(b) to decode
product codes [17]. The decoding process for operating
mode-(a), described in Fig. 6, is implemented within one
clock cycle. Compared to directly using H(71, 64) code,
the decoder delay of the proposed congurable coding
method increases about 10% because of the overhead of the
extra MUX for mode switching. The BCH(85, 64) and
RS(85, 65) decoder are implemented in a seven-stage
pipelined architecture. In order to improve the throughput
of BCH(85, 64) and RS(85, 65) codes, the parallel method
in [22] is applied. Compared to the RS(85, 65), the
proposed congurable coding method achieves a 15% delay
reduction.
Table 2 also shows the synthesised codec area for different
error control schemes. The area includes the encoder and
decoder area. The encoder area includes the retransmission
buffer. The decoder buffer storing the original message in
the receiver is not included, because it can always be shared
with the routing buffer in the router. The area of the error
counter and comparison circuits in the congurable control
logic is also included in the proposed method. The results
show that multiple error correction codes have much larger
area than that of simple Hamming codes. The area
overhead of the product codes is mainly because of the
retransmission buffer and the pipelined decoder architecture.
Compared to BCH(85, 64) and RS(85, 65), the product
code has a smaller area, because each component code is still
a simple Hamming code. BCH(85, 64) has the largest area
because of the complexity of the eld operation and the
decoding process. By using the proposed hardware sharing
method, the area overhead of the conguration circuit is
relatively small compared to product code itself [17].
4.2 Reliability
On-chip communication errors can be attributed to voltage
perturbations induced by noise from many sources. In [23],
a Gaussian pulse function is used to model the error
probability for a single wire when a transition occurs
1 Q
V
swing
2s
N
_ _

_
1
V
swing
=2s
N
1

2p
p e
y
2
=2
dy (9)
where V
swing
is the link swing voltage and s
N
is the standard
deviation of the noise voltage, which is assumed to be a
normal distribution. The model in (9) assumes the
probability of error in each wire is independent. As
technology scales, the probability of a single noise source
causing errors in multiple neighbouring wires increases [5,
6]. A more realistic error model including spatial burst
errors should be considered. The error model in (9) can be
extended to include burst errors. In the extended error
model, we still assume that a noise source affects wire d
n
with a probability 1. Instead of only affecting one wire, this
noise source also affects its neighbouring wires with a
certain probability P
n
. For the purpose of simplicity, two
different P
n
values, 10
22
and 1, are used in the simulations.
The case of P
n
equal to 1 refers to the case where a noise
source always causes a three-wire burst error.
Fig. 9 shows the residual it error rate of different error
control schemes as a function of noise voltage deviation at
P
n
1 and 10
22
. A link swing voltage of 1 V is assumed
in model (9). The simulation results show that the
H(71, 64) used in operating mode-(a) has the worst
residual it error rate, because Hamming codes can only
correct one error at a time and simultaneous errors greater
than one will lead to uncorrected errors. Compared to the
BCH(85, 64) code, the product code used in operating
mode-(b) achieves a better residual it error rate, because
the product code can effectively correct multiple random
and burst errors, whereas the BCH code is only good at
correcting multiple random errors. As P
n
increases, the
residual it error rate of the H(71, 64) code and
BCH(85, 64) code decreases because of the higher burst
error probability at larger P
n
. Compared to RS(85, 65), the
product code used in operating mode-(b) has a better error
correction capability, because RS(85, 65) can only correct
multiple errors within two symbols. In NoC links, burst
Table 1 Parameters used for link model
width (mm) 0.31
space (mm) 0.31
thickness (mm) 0.83
height (mm) 0.14
dielectric constant (k) 2.1
Table 2 Number of wires in the link, delay and area
comparison
Error control
scheme
The
number of
wires in
the link
(active/
total)
Decoder
delay (ns)
Codec
area
(mm
2
)
Hamming (71, 64) 71/71 0.53 1550
BCH(85, 64) 85/85 0.63 53547
RS(85, 65) 85/85 0.68 37482
product code 88/88 0.50 7671
proposed
congurable
coding method
(a) 71/88 0.58 8906
(b) 88/88
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errors caused by noise and crosstalk can begin at any bit
position of the links. More powerful RS code can be
constructed but with a larger delay and area overhead.
4.3 Power and energy consumption
Fig. 10 shows the energy consumption of the proposed method
at two operating modes. The energy includes encoder, decoder
and link energy consumption. The encoder and decoder energy
is reported by design compiler using TSMC45 nmtechnology
at clock frequency 1 GHz. Clock gating is applied for operating
mode-(a) to reduce the unnecessary energy consumption of the
transmission buffer and component2 decoder of the product
code. The link energy is measured in Cadence Spectre using
Predictive Technology Model 45 nm technology [24] at a
supply voltage of 1 V. The driver of the link is sized to allow a
clock frequency 1 GHz. With the 45 nm global link
parameter in Table 1, the corresponding resistance and
capacitance are 86 V/mm and 218 fF/mm for the link. In
NoC architectures, the link length is the distance between
two switches, which is decided by the tile dimensions. In
mesh- or torus-shaped NoC architectures, the distance
between two switches is generally a few millimetres [25, 26].
Two link lengths, 1 and 3 mm, are examined in the
simulation. The results show that the operating mode-(a)
consumes less codec and link energy compared to operating
mode-(b), if both of the operating modes meet the reliability
requirement. This is because gating techniques is applied and
fewer link wires in operating mode-(a). The results also show
that the link energy dominates the total energy consumption,
as the link length increases. For the 3 mm link length,
operating mode-(b) consumes about 28% more energy than
mode-(a).
The energy consumption of the proposed method is also
compared to the energy consumption of directly using
H(71, 64) code, BCH(85, 64) and RS(85, 64) code. First,
the comparison is performed under a xed residual it error
Figure 9 Residual it error rate of different error control schemes as a function of noise voltage deviation
a P
n
10
22
b P
n
1
Figure 10 Energy comparison of the proposed method for different link lengths
a Link length 1 mm
b Link length 3 mm
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rate requirement of 10
210
, shown in Fig. 11. Two noise
environments are considered. For the favourable
environment (s
N
0.06), the proposed method operates in
mode-(a). In the noisy environment (s
N
0.11), the
proposed method switches to operation mode-(b). As the
noise environment worsens, the direct implementation of the
H(71, 64) code requires a higher link swing voltage to meet
the reliability requirement [6, 7, 9, 27]; while the proposed
method can switch to more reliable operating mode-(b). In
the noisy environment (s
N
0.11), the conventional
Hamming implementation requires a 39% increase in the
link swing voltage compared to the proposed method to
achieve the required residual it error rate. The increased
link swing voltage greatly increases the link energy of the
conventional Hamming implementation. Fig. 12 shows
energy consumption of the four error control schemes for
link lengths of 1 and 3 mm. The results show that the
proposed method consumes the least energy in the high-
noise environment by switching to operating mode-(b). The
BCH(85, 64) code consumes the largest energy for a link
length 1 mm because its codec energy is larger than the
other error control schemes. For a 3 mm link in the noisy
environment (s
N
0.11), the proposed method achieves 30
and 25% improvement in energy consumption compared to
the direct implementation of H(71, 64) code and the
BCH(85, 64) code. In the more favourable condition
(s
N
0.06), direct implementation of the H(71, 64) code
consumes the least energy of the compared schemes. By
switching to operating mode-(a) in low-noise environments,
the proposed method consumes 10% more energy than the
H(71, 64) code because of the congurable system overhead.
Compared to BCH(85, 64), mode-(a) of the proposed
method achieves a 40% improvement in energy consumption.
We also evaluate the different requirements of residual it
error rate on the energy consumption. Fig. 13 shows the
energy consumption of different error control schemes at
residual it error rate 10
210
and 10
220
. The energy
consumption is measured at noise condition (s
N
0.06)
with a link length 3 mm. The results show that the high
reliability requirement (residual error rate 10
220
) has the
similar effect of the noisy environment. A 20% higher link
voltage is required for H(71, 64) to meet residual error rate
10
220
increasing the total energy consumption. By switching
to operating mode-(b), the proposed method can achieve 9%
energy reduction compared to directly using H(71, 64).
5 Conclusion
In this paper, an error control scheme combining Hamming
codes with product codes is proposed to address multiple
error correction. The proposed method provides both
reliable and energy efcient on-chip communication for
varied noise environments. To reduce system overhead, the
parity check calculation circuit, syndrome decoder and error
correction circuits are optimised using hardware sharing.
In the proposed scheme, the type of error correction code
can be dynamically selected according to the noise
environment. For a given system reliability requirement
in a noisy environment, the proposed error control scheme
achieves 25% energy reduction compared to a multi-error
correcting BCH code. The proposed method uses a lower
Figure 11 Example of mode switching for a given reliability
requirement
Figure 13 Energy comparison for different residual it error
rate requirements
Figure 12 Energy comparison for different noise
environments and link lengths
IET Comput. Digit. Tech., 2010, Vol. 4, Iss. 3, pp. 251261 259
doi: 10.1049/iet-cdt.2008.0130 & The Institution of Engineering and Technology 2010
www.ietdl.org
swing voltage than a conventional Hamming implementation
to achieve the same reliability in noisy environments,
resulting in a 30% energy reduction. In a low-noise
environment, the proposed method can achieve a 40%
reduction in energy consumption compared to a BCH
code, but has a 10% energy overhead penalty compared to
directly using Hamming codes.
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