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Table Of Contents

Document Conventions
1. Introduction
1.1. Specification Contents
1.2. Motivation
1.3. PCI Local Bus Applications
1.4. PCI Local Bus Overview
1.6. Administration
2. Signal Definition
2.1. Signal Type Definition
2.2. Pin Functional Groups
2.2.1. System Pins
2.2.2. Address and Data Pins
2.2.3. Interface Control Pins
2.2.4. Arbitration Pins (Bus Masters Only)
2.2.5. Error Reporting Pins
2.2.6. Interrupt Pins (Optional)
2.2.7. Additional Signals
2.2.8. 64-Bit Bus Extension Pins (Optional)
2.2.9. JTAG/Boundary Scan Pins (Optional)
2.2.10. System Management Bus Interface Pins (Optional)
2.3. Sideband Signals
2.4. Central Resource Functions
3. Bus Operation
3.1. Bus Commands
3.1.1. Command Definition
3.1.2. Command Usage Rules
3.2. PCI Protocol Fundamentals
3.2.1. Basic Transfer Control
3.2.2. Addressing
3.2.3. Byte Lane and Byte Enable Usage
3.2.4. Bus Driving and Turnaround
3.2.5. Transaction Ordering and Posting
3.2.6. Combining, Merging, and Collapsing
3.3. Bus Transactions
3.3.1. Read Transaction
3.3.2. Write Transaction
3.3.3. Transaction Termination
3.4. Arbitration
3.4.1. Arbitration Signaling Protocol
3.4.2. Fast Back-to-Back Transactions
3.4.3. Arbitration Parking
3.5. Latency
3.5.1. Target Latency
3.5.2. Master Data Latency
3.5.3. Memory Write Maximum Completion Time Limit
3.5.4. Arbitration Latency
3.6. Other Bus Operations
3.6.1. Device Selection
3.6.2. Special Cycle
3.6.3. IDSEL Stepping
3.6.4. Interrupt Acknowledge
3.7. Error Functions
3.7.1. Parity Generation
3.7.2. Parity Checking
3.7.3. Address Parity Errors
3.7.4. Error Reporting
3.7.5. Delayed Transactions and Data Parity Errors
3.7.6. Error Recovery
3.8. 64-Bit Bus Extension
3.9. 64-bit Addressing
3.10. Special Design Considerations
4.1. Overview
4.1.1. Transition Road Map
4.1.2. Dynamic vs. Static Drive Specification
4.2. Component Specification
4.2.1. 5V Signaling Environment
4.2.2. 3.3V Signaling Environment
4.2.3. Timing Specification
4.2.4. Indeterminate Inputs and Metastability
4.2.5. Vendor Provided Specification
4.2.6. Pinout Recommendation
4.3. System Board Specification
4.3.1. Clock Skew
4.3.2. Reset
4.3.3. Pull-ups
4.3.4. Power
4.3.5. System Timing Budget
4.3.6. Physical Requirements
4.3.7. Connector Pin Assignments
4.4. Add-in Card Specification
4.4.1. Add-in Card Pin Assignment
5.1. Overview
5.3. Connector Physical Description
5.4. Connector Physical Requirements
5.5. Connector Performance Specification
5.6. System Board Implementation
6. Configuration Space
6.1. Configuration Space Organization
6.2.1. Device Identification
6.2.2. Device Control
6.2.3. Device Status
6.2.4. Miscellaneous Registers
6.2.5. Base Addresses
6.3. PCI Expansion ROMs
6.3.1. PCI Expansion ROM Contents
6.3.2. Power-on Self Test (POST) Code
6.3.3. PC-compatible Expansion ROMs
6.5. Device Drivers
6.6. System Reset
6.7. Capabilities List
6.8. Message Signaled Interrupts
6.8.1. MSI Capability Structure
6.8.2. MSI-X Capability & Table Structures
6.8.3. MSI and MSI-X Operation
7. 66 MHz PCI Specification
7.1. Introduction
7.2. Scope
7.3. Device Implementation Considerations
7.3.1. Configuration Space
7.4. Agent Architecture
7.5. Protocol
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition
7.5.2. Latency
7.6. Electrical Specification
7.6.1. Overview
7.6.2. Transition Roadmap to 66 MHz PCI
7.6.3. Signaling Environment
7.6.4. Timing Specification
7.6.5. Vendor Provided Specification
7.6.6. Recommendations
7.7. System Board Specification
7.7.1. Clock Uncertainty
7.7.2. Reset
7.7.3. Pullups
7.7.4. Power
7.7.5. System Timing Budget
7.7.6. Physical Requirements
7.7.7. Connector Pin Assignments
7.8. Add-in Card Specifications
8. System Support for SMBus
8.1. SMBus System Requirements
8.1.1. Power
8.1.2. Physical and Logical SMBus
8.1.3. Bus Connectivity
8.1.4. Master and Slave Support
8.1.5. Addressing and Configuration
8.1.6. Electrical
8.1.7. SMBus Behavior on PCI Reset
8.2.1. Connection
8.2.2. Master and Slave Support
8.2.3. Addressing and Configuration
8.2.4. Power
8.2.5. Electrical
A. Special Cycle Messages
A.1. Message Encodings
A.2. Use of Specific Encodings
B. State Machines
B.1. Target LOCK Machine
B.2. Master Sequencer Machine
B.3. Master LOCK Machine
C. Operating Rules
C.1. When Signals are Stable
C.2. Master Signals
C.3. Target Signals
C.4. Data Phases
C.5. Arbitration
C.6. Latency
C.7. Device Selection
C.8. Parity
D. Class Codes
E. System Transaction Ordering
E.1. Producer - Consumer Ordering Model
E.2. Summary of PCI Ordering Requirements
E.3. Ordering of Requests
E.4. Ordering of Delayed Transactions
E.5. Delayed Transactions and LOCK#
E.6. Error Conditions
F. Exclusive Accesses
F.1. Exclusive Accesses on PCI
F.2. Starting an Exclusive Access
F.3. Continuing an Exclusive Access
F.4. Accessing a Locked Agent
F.5. Completing an Exclusive Access
G. I/O Space Address Decoding for Legacy Devices
H. Capability IDs
I. Vital Product Data
I.1. VPD Format
I.2. Compatibility
I.3. VPD Definitions
I.3.1. VPD Large and Small Resource Data Tags
I.3.2. VPD Example
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Published by: rp30 on Oct 06, 2011
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