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Table Of Contents

Guide Contents
System Generator PDF Doc Set
Additional Resources
Conventions
Typographical
Online Document
The Xilinx DSP Block Set
FIR Filter Generation
Support for MATLAB
System Resource Estimation
Hardware Co-Simulation
System Integration Platform
Downloading
Hardware Co-Simulation Support
System Requirements and Recommendations
Hardware Recommendations
Operating System and Software Requirements
Compatibility with Other Tools
Software Prerequisites
Using the ISE Design Suite Installer
Installing System Generator On the Linux OS
Post Installation Tasks
Hardware Co-Simulation Installation
Compiling Xilinx HDL Libraries
Configuring the System Generator Cache
Displaying and Changing Versions of System Generator
Release Notes 11.4
System Generator Enhancements
Xilinx Blockset Enhancements
Known Issues
Release Notes 11.3
Discontinued System Generator Features
Release Notes 11.2
Release Notes 11.1
Xilinx Basic Building Block Enhancements
Xilinx Blocks Superseded
Release Notes 10.1.3
Xilinx DSP Blockset Enhancements
Tool Flow and Integration
Release Notes 10.1.2
Release Notes 10.1.1
Release Notes 10.1
Upgrading a Xilinx System Generator Model
Upgrading v2.x and Prior Models
Upgrading v3.x, v6.x and v7.x Models
Examples
Introduction
Lesson 1 - Design Creation Basics
The System Generator Design Flow
The Xilinx DSP Blockset
Defining the FPGA Boundary
Adding the System Generator Token
Creating the DSP Design
Generating the HDL Code
Lab Exercise: Getting Started with System Generator
Lesson 2 - Fixed Point and Bit Operations
Fixed-Point Numeric Precision
System Generator Fixed-Point Quantization
Overflow and Round Modes
Bit-Level Operations
The Reinterpret Block
The Convert Block
The Concat Block
Slice Block
The BitBasher Block
Lesson 2 Summary
Lab Exercise: Signal Routing
Lesson 3 - System Control
Controlling a DSP System
The MCode Block
The Xilinx “xl_state” Data Type
State Machine Example
The Expression Block
Reset and Enable Ports
Bursty Data
Lesson 3 Summary
Lab Exercise: System Control
Lesson 4 - Multi-Rate Systems
Creating Multi-Rate Systems
Up and Down Sampling Blocks
Rate Changing Functional Blocks
Viewing Rate Changes in Simulink
Debugging Tools
Sample Period “Rules”
Lab Exercise: Multi-Rate Systems
Lesson 5 - Using Memories
Block vs. Distributed RAM
Initializing RAMs and ROMs
System Generator RAM Blocks
System Generator ROM Blocks
The Delay Block
The FIFO Block
Shared Memory Block
Lab Exercise: Using Memories
Lesson 6 - Designing Filters
The Virtex DSP48 Math Slice
FIR Compiler Block
Creating Coefficients with FDATool
Using FDA Tool Coefficients
Lab Exercise: Designing Filters
Additional Examples and Tutorials
Black Box Examples
DSP Examples
M-Code Examples
Index
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Published by Thomas Schulze

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Published by: Thomas Schulze on Oct 11, 2011
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