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Examples VHDL

Examples VHDL

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Published by: Phạm Hoàng Anh on Oct 13, 2011
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01/23/2013

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Examples of VHDL Descriptions
 
Advanced Electronic Design Automation
 
Examples of VHDL Descriptions
 
Author:Ian Elliott of Northumbria University
 
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described interms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can besynthesised using current synthesis tools.
 
Use the hierarchical links below to navigate your way through the examples:
 
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Combinational Logic
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Counters
http: / /www.ami.bolton.ac.uk /courseware /adveda /vhdl /vhdlexmp.html(1of67)[23 /1 /20024:15:01]
 
Examples of VHDL Descriptions
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Shift Registers
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Memory
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State Machines
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Systems
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ADC and DAC
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http: / /www.ami.bolton.ac.uk /courseware /adveda /vhdl /vhdlexmp.html(2of67)[23 /1 /20024:15:07]
 
Examples of VHDL Descriptions
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Registers
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Universal Register
Description - This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. The register can be loaded from a set of parallel data inputsand the mode is controlled by a 3-bit input. The 'termcnt' (terminal count) output goes high when the register contains zero.
 
LIBRARY ieee;USE ieee.Std_logic_1164.ALL;USE ieee.Std_logic_unsigned.ALL;ENTITY unicntr ISGENERIC(n : Positive := 8);
--size of counter/shifter 
PORT(clock, serinl, serinr : IN Std_logic;
--serial inputs
mode : IN Std_logic_vector(2 DOWNTO 0);
--mode control
datain : IN Std_logic_vector((n-1) DOWNTO 0);
--parallel inputs
dataout : OUT Std_logic_vector((n-1) DOWNTO 0); --
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termcnt : OUT Std_logic);
--terminal count output
END unicntr;ARCHITECTURE v1 OF unicntr ISSIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0);BEGINmain_proc : PROCESSBEGINWAIT UNTIL rising_edge(clock);CASE mode IS--resetWHEN "000" => int_reg <= (OTHERS => '0');--parallel loadWHEN "001" => int_reg <= datain;--count upWHEN "010" => int_reg <= int_reg + 1;--count downWHEN "011" => int_reg <= int_reg - 1;--shift leftWHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl;--shift rightWHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);--do nothingWHEN OTHERS => NULL;END CASE;END PROCESS;det_zero : PROCESS(int_reg) --
detects when count is 0
BEGINtermcnt <= '1';FOR i IN int_reg'Range LOOP
http: / /www.ami.bolton.ac.uk /courseware /adveda /vhdl /vhdlexmp.html(3of67)[23 /1 /20024:15:08]

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