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Table Of Contents

The Method of Logical Effort
1.1 Delay in a logic gate
1.2 Multi-stage logic networks
1.3 Choosing the best number of stages
1.4 Summary
1.5 Exercises
Design Examples
2.1 The AND function of eight inputs
2.1.1 Calculating gate sizes
2.2 Decoder
2.2.1 Generating complementary inputs
2.3. SYNCHRONOUS ARBITRATION 31
2.3 Synchronous arbitration
2.3.1 The original circuit
2.3.2 Improving the design
2.3.3 Restructuring the problem
2.4 Summary
2.5 Exercises
Deriving the Method of Logical Effort
3.1 Model of a logic gate
3.2 Delay in a logic gate
3.3 Minimizing delay along a path
3.4 Choosing the length of a path
3.5 Using the wrong number of stages
3.6 Using the wrong gate size
3.7 Summary
3.8 Exercises
Calculating the Logical Effort of Gates
4.1 Definitions of logical effort
4.2. GROUPING INPUT SIGNALS 61
4.2 Grouping input signals
4.3 Calculating logical effort
4.4 Asymmetric logic gates
4.5 Catalog of logic gates
4.5.1 NAND gate
4.5.2 NOR gate
4.5.3 Multiplexers, tri-state inverters
4.5.4 XOR, XNOR, and parity gates
4.5.5 Majority gate
4.5.6 Adder carry chain
4.5.7 Dynamic latch
4.5.8 Dynamic Muller C-element
4.5.9 Upper bounds on logical effort
4.6 Estimating parasitic delay
4.7. PROPERTIES OF LOGICAL EFFORT 77
4.7 Properties of logical effort
4.8 Exercises
Calibrating the Model
5.1 Calibration technique
5.2 Designing test circuits
5.2.1 Rising, falling, and average delays
5.2.2 Choice of input
5.2.3 Parasitic capacitance
5.3. OTHER CHARACTERIZATION METHODS 89
5.2.4 Process sensitivity
5.3 Other characterization methods
5.4. CALIBRATING SPECIAL CIRCUIT FAMILIES 91
5.4 Calibrating special circuit families
5.5 Summary
5.6 Exercises
Forks of Amplifiers
6.1 The fork circuit form
6.2. HOW MANYSTAGES SHOULD A FORK USE? 99
6.2 How many stages should a fork use?
6.3 Summary
6.4 Exercises
7.1.1 Branch paths with equal lengths
7.1.2 Branch paths with unequal lengths
7.2 Branches after logic
7.3. CIRCUITS THAT BRANCH ANDRECOMBINE 115
7.3 Circuits that branch and recombine
7.4 Interconnect
7.4.1 Short wires
7.4.2 Long wires
7.4.3 Medium wires
7.5 A design approach
7.6 Exercises
Asymmetric Logic Gates
8.1 Designing asymmetric logic gates
8.2 Applications of asymmetric logic gates
8.2.1 Multiplexers
8.3 Summary
8.4 Exercises
Unequal Rising and Falling Delays
9.1 Analyzing delays
9.2 Case analysis
9.2.1 Skewed gates
9.4 Summary
9.5 Exercises
Circuit Families
10.1 Pseudo-NMOS circuits
10.1.1 Symmetric NOR gates
10.2 Domino circuits
10.2.1 Logical effort of dynamic gates
10.2.2 Stage effort of domino circuits
10.2.3 Building logic in static gates
10.2.4 Designing dynamic gates
10.3 Transmission gates
10.4 Summary
10.5 Exercises
Wide Structures
11.1.1 Minimum logical effort
11.1.2 Minimum delay
11.2.2 Minimum delay
11.3 Decoders
11.3.1 Simple decoder
11.3.2 Predecoding
11.3.3 A better decoder
11.4 Multiplexers
11.4.1 How wide should a multiplexer be?
11.6 Exercises
Conclusions
12.1 The theory of logical effort
12.2. INSIGHTS FROM LOGICAL EFFORT 191
12.2 Insights from logical effort
12.3 A design procedure
12.4 Other approaches to path design
12.4.1 Simulate and tweak
12.4.2 Equal fanout
12.4.3 Equal delay
12.4.4 Numerical optimization
12.5 Shortcomings of logical effort
12.6 Parting words
Cast of Characters
Logical Effort Tools
B.1 Library characterization
B.2 Wide gate design
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logical effort

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Published by: api-3700940 on Oct 16, 2008
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