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Table Of Contents

CHAPTER 2 INSTRUCTION FORMAT
CHAPTER 3 INSTRUCTION SET REFERENCE
3.1.INTERPRETING THE INSTRUCTION REFERENCE PAGES
3.1.1.2. INSTRUCTION COLUMN
3.1.1.3. DESCRIPTION COLUMN
3.1.3.Intel C/C++ Compiler Intrinsics Equivalent
3.1.3.1. THE INTRINSICS API
3.1.3.2. MMX™ TECHNOLOGY INTRINSICS
3.1.3.3. SIMD FLOATING-POINT INTRINSICS
3.1.7.Real-Address Mode Exceptions
3.1.8.Virtual-8086 Mode Exceptions
3.1.10.SIMD Floating-Point Exceptions - Streaming SIMD Extensions Only
Table 3-3. Floating-Point Exception Mnemonics and Names
Table 3-4. SIMD Floating-Point Exception Mnemonics and Names
Table 3-5. Streaming SIMD Extensions Faults (Interrupts 6 & 7)
AAA—ASCII Adjust After Addition
AAD—ASCII Adjust AX Before Division
AAM—ASCII Adjust AX After Multiply
AAS—ASCII Adjust AL After Subtraction
3F AAS ASCII adjust AL after subtraction
ADDPS—Packed Single-FP Add
ADDSS—Scalar Single-FP Add
ANDNPS—Bit-wise Logical And Not For Single-FP
ANDPS—Bit-wise Logical And For Single FP
Figure 3-6. Operation of the ANDPS Instruction
ARPL—Adjust RPL Field of Segment Selector
BOUND—Check Array Index Against Bounds
BTC—Bit Test and Complement
BTR—Bit Test and Reset
CBW/CWDE—Convert Byte to Word/Convert Word to Doubleword
CDQ—Convert Double to Quad
CLD—Clear Direction Flag
CLI—Clear Interrupt Flag
CLTS—Clear Task-Switched Flag in CR0
CMC—Complement Carry Flag
CMOVcc—Conditional Move
CMP—Compare Two Operands
CMPPS—Packed Single-FP Compare
Figure 3-9. Operation of the CMPPS (Imm8=2) Instruction
Figure 3-11. Operation of the CMPPS (Imm8=4) Instruction
Figure 3-13. Operation of the CMPPS (Imm8=6) Instruction
CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands
CMPSS—Scalar Single-FP Compare
Figure 3-15. Operation of the CMPSS (Imm8=0) Instruction
Figure 3-17. Operation of the CMPSS (Imm8=2) Instruction
Figure 3-19. Operation of the CMPSS (Imm8=4) Instruction
Figure 3-21. Operation of the CMPSS (Imm8=6) Instruction
CMPXCHG—Compare and Exchange
CMPXCHG8B—Compare and Exchange 8 Bytes
COMISS—Scalar Ordered Single-FP Compare and Set EFLAGS
Figure 3-23. Operation of the COMISS Instruction, Condition One
Figure 3-24. Operation of the COMISS Instruction, Condition Two
Figure 3-25. Operation of the COMISS Instruction, Condition Three
Figure 3-26. Operation of the COMISS Instruction, Condition Four
CPUID—CPU Identification
Table 3-6. Information Returned by CPUID Instruction
Table 3-7. Processor Type Field
Table 3-8. Feature Flags Returned in EDX Register
Table 3-9. Encoding of Cache and TLB Descriptors
CVTPI2PS—Packed Signed INT32 to Packed Single-FP Conversion
Figure 3-28. Operation of the CVTPI2PS Instruction
CVTPS2PI—Packed Single-FP to Packed INT32 Conversion
Figure 3-29. Operation of the CVTPS2PI Instruction
CVTSI2SS—Scalar Signed INT32 to Single-FP Conversion
Figure 3-30. Operation of the CVTSI2SS Instruction
CVTSS2SI—Scalar Single-FP to Signed INT32 Conversion
Figure 3-31. Operation of the CVTSS2SI Instruction
CVTTPS2PI—Packed Single-FP to Packed INT32 Conversion (Truncate)
Figure 3-32. Operation of the CVTTPS2PI Instruction
CVTTSS2SI—Scalar Single-FP to Signed INT32 Conversion (Truncate)
Figure 3-33. Operation of the CVTTSS2SI Instruction
CWDE—Convert Word to Doubleword
DAA—Decimal Adjust AL after Addition
DAS—Decimal Adjust AL after Subtraction
DIVPS—Packed Single-FP Divide
Figure 3-34. Operation of the DIVPS Instruction
DIVSS—Scalar Single-FP Divide
Figure 3-35. Operation of the DIVSS Instruction
EMMS—Empty MMX™ State
ENTER—Make Stack Frame for Procedure Parameters
FBLD—Load Binary Coded Decimal
FBSTP—Store BCD Integer and Pop
FCLEX/FNCLEX—Clear Exceptions
FCMOVcc—Floating-Point Conditional Move
FCOM/FCOMP/FCOMPP—Compare Real
FDECSTP—Decrement Stack-Top Pointer
FIST/FISTP—Store Integer
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant
FLDCW—Load Control Word
FLDENV—Load FPU Environment
FMUL/FMULP/FIMUL—Multiply
FPATAN—Partial Arctangent
FPREM—Partial Remainder
FPREM1—Partial Remainder
FRNDINT—Round to Integer
FRSTOR—Restore FPU State
FSAVE/FNSAVE—Store FPU State
FSTCW/FNSTCW—Store Control Word
FSTENV/FNSTENV—Store FPU Environment
FSTSW/FNSTSW—Store Status Word
FSUB/FSUBP/FISUB—Subtract
FSUBR/FSUBRP/FISUBR—Reverse Subtract
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Real
FXCH—Exchange Register Contents
Streaming SIMD Extension State
FXTRACT—Extract Exponent and Significand
INS/INSB/INSW/INSD—Input from Port to String
INT n/INTO/INT 3—Call to Interrupt Procedure
INVD—Invalidate Internal Caches
INVLPG—Invalidate TLB Entry
Jcc—Jump if Condition Is Met
LAHF—Load Status Flags into AH Register
LAR—Load Access Rights Byte
LDMXCSR—Load Streaming SIMD Extension Control/Status
LDS/LES/LFS/LGS/LSS—Load Far Pointer
LEA—Load Effective Address
LEAVE—High Level Procedure Exit
LES—Load Full Pointer
LFS—Load Full Pointer
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
LGS—Load Full Pointer
LLDT—Load Local Descriptor Table Register
LIDT—Load Interrupt Descriptor Table Register
LMSW—Load Machine Status Word
LOCK—Assert LOCK# Signal Prefix
LODS/LODSB/LODSW/LODSD—Load String
LOOP/LOOPcc—Loop According to ECX Counter
LSL—Load Segment Limit
LSS—Load Full Pointer
LTR—Load Task Register
MASKMOVQ—Byte Mask Write
MAXPS—Packed Single-FP Maximum
Figure 3-36. Operation of the MAXPS Instruction
MAXSS—Scalar Single-FP Maximum
MINPS—Packed Single-FP Minimum
Figure 3-38. Operation of the MINPS Instruction
MINSS—Scalar Single-FP Minimum
MOV—Move to/from Control Registers
MOV—Move to/from Debug Registers
MOVAPS—Move Aligned Four Packed Single-FP
MOVHLPS— High to Low Packed Single-FP
Figure 3-42. Operation of the MOVHLPS Instruction
MOVHPS—Move High Packed Single-FP
MOVLHPS—Move Low to High Packed Single-FP
Figure 3-44. Operation of the MOVLHPS Instruction
MOVLPS—Move Low Packed Single-FP
MOVMSKPS—Move Mask To Integer
Figure 3-46. Operation of the MOVMSKPS Instruction
MOVNTPS—Move Aligned Four Packed Single-FP Non Temporal
MOVNTQ—Move 64 Bits Non Temporal
MOVS/MOVSB/MOVSW/MOVSD—Move Data from StringtoString
MOVSS—Move Scalar Single-FP
MOVSX—Move with Sign-Extension
MOVUPS—Move Unaligned Four Packed Single-FP
MOVZX—Move with Zero-Extend
MUL—Unsigned Multiply
MULPS—Packed Single-FP Multiply
Figure 3-50. Operation of the MULPS Instruction
MULSS—Scalar Single-FP Multiply
Figure 3-51. Operation of the MULSS Instruction
NEG—Two's Complement Negation
NOT—One's Complement Negation
OR—Logical Inclusive OR
ORPS—Bit-wise Logical OR for Single-FP Data
Figure 3-52. Operation of the ORPS Instruction
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
PACKSSWB/PACKSSDW—Pack with Signed Saturation
PACKUSWB—Pack with Unsigned Saturation
PADDB/PADDW/PADDD—Packed Add
PADDSB/PADDSW—Packed Add with Saturation
PADDUSB/PADDUSW—Packed Add Unsigned with Saturation
Figure 3-63. Operation of the PEXTRW Instruction
Figure 3-64. Operation of the PINSRW Instruction
PMADDWD—Packed Multiply and Add
PMAXSW—Packed Signed Integer Word Maximum
PMAXUB—Packed Unsigned Integer Byte Maximum
PMINSW—Packed Signed Integer Word Minimum
PMINUB—Packed Unsigned Integer Byte Minimum
PMOVMSKB—Move Byte Mask To Integer
Figure 3-70. Operation of the PMOVMSKB Instruction
PMULHUW—Packed Multiply High Unsigned
Figure 3-71. Operation of the PMULHUW Instruction
PMULHW—Packed Multiply High
PMULLW—Packed Multiply Low
POP—Pop a Value from the Stack
POPA/POPAD—Pop All General-Purpose Registers
POPF/POPFD—Pop Stack into EFLAGS Register
POR—Bitwise Logical OR
PSRLW/PSRLD/PSRLQ—Packed Shift Right Logical
PSUBB/PSUBW/PSUBD—Packed Subtract
PSUBSB/PSUBSW—Packed Subtract with Saturation
PSUBUSB/PSUBUSW—Packed Subtract Unsigned with Saturation
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ—Unpack High Packed Data
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ—Unpack Low Packed Data
PUSH—Push Word or Doubleword Onto the Stack
PUSHA/PUSHAD—Push All General-Purpose Registers
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
PXOR—Logical Exclusive OR
RCL/RCR/ROL/ROR-—Rotate
RCPPS—Packed Single-FP Reciprocal
Figure 3-86. Operation of the RCPPS Instruction
RCPSS—Scalar Single-FP Reciprocal
Figure 3-87. Operation of the RCPSS Instruction
RDMSR—Read from Model Specific Register
RDPMC—Read Performance-Monitoring Counters
RDTSC—Read Time-Stamp Counter
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix
RET—Return from Procedure
RSM—Resume from System Management Mode
RSQRTPS—Packed Single-FP Square Root Reciprocal
Figure 3-88. Operation of the RSQRTPS Instruction
RSQRTSS—Scalar Single-FP Square Root Reciprocal
Figure 3-89. Operation of the RSQRTSS Instruction
SAHF—Store AH into Flags
SHLD—Double Precision Shift Left
SHRD—Double Precision Shift Right
SHUFPS—Shuffle Single-FP
Figure 3-90. Operation of the SHUFPS Instruction
SIDT—Store Interrupt Descriptor Table Register
SLDT—Store Local Descriptor Table Register
SMSW—Store Machine Status Word
SQRTPS—Packed Single-FP Square Root
Figure 3-91. Operation of the SQRTPS Instruction
SQRTSS—Scalar Single-FP Square Root
Figure 3-92. Operation of the SQRTSS Instruction
STD—Set Direction Flag
STI—Set Interrupt Flag
STMXCSR—Store Streaming SIMD Extension Control/Status
STOS/STOSB/STOSW/STOSD—Store String
STR—Store Task Register
SUBPS—Packed Single-FP Subtract
Figure 3-93. Operation of the SUBPS Instruction
SUBSS—Scalar Single-FP Subtract
Figure 3-94. Operation of the SUBSS Instruction
SYSENTER—Fast Transition to System Call Entry Point
SYSEXIT—Fast Transition from System Call Entry Point
0F, 35 SYSEXIT Transition from System Call Entry Point
UCOMISS—Unordered Scalar Single-FP compare and set EFLAGS
Figure 3-95. Operation of the UCOMISS Instruction, Condition One
Figure 3-96. Operation of the UCOMISS Instruction, Condition Two
Figure 3-97. Operation of the UCOMISS Instruction, Condition Three
Figure 3-98. Operation of the UCOMISS Instruction, Condition Four
UD2—Undefined Instruction
UNPCKHPS—Unpack High Packed Single-FP Data
Figure 3-99. Operation of the UNPCKHPS Instruction
UNPCKLPS—Unpack Low Packed Single-FP Data
Figure 3-100. Operation of the UNPCKLPS Instruction
VERR/VERW—Verify a Segment for Reading or Writing
WBINVD—Write Back and Invalidate Cache
WRMSR—Write to Model Specific Register
XCHG—Exchange Register/Memory with Register
XLAT/XLATB—Table Look-up Translation
XOR—Logical Exclusive OR
XORPS—Bit-wise Logical Xor for Single-FP Data
Figure 3-101. Operation of the XORPS Instruction
A.2.5.Opcode Extensions For One- And Two-byte Opcodes
APPENDIX C COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
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Intel Instruction Set

Intel Instruction Set

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