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CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP NOP
t
RP
*
*
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
Begin Auto-precharge
*
Bank can be reactivated at completion of t
RP
.
DOUT A
0
DOUT A
0
NOP
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
(Burst Length = 1, CAS Latency = 2, 3)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
18
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Burst Read with Auto-Precharge
Burst Read with Auto-Precharge
COMMAND
NOP NOP NOP NOP
READ A
Auto-Precharge
t
RP
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP NOP
t
RP
*
*
*
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
Begin Auto-precharge
DOUT A
0
DOUT A
0
NOP
DOUT A
1
DOUT A
1
*
Bank can be reactivated at completion of t
RP
.
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
(Burst Length = 2, CAS Latency = 2, 3)
COMMAND
NOP NOP NOP NOP
READ A
Auto-Precharge
t
RP
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP NOP
t
RP
*
*
*
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
Begin Auto-precharge
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
NOP
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
*
Bank can be reactivated at completion of t
RP
.
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
(Burst Length = 4, CAS Latency = 2, 3)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
19
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted
by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge
function will begin with the new command. The bank being auto-precharged may be reactivated after the delay t
RP
.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Read
Burst Read with Auto-Precharge Interrupted by Write
t
RP
COMMAND
NOP NOP NOP NOP
READ A
Auto-Precharge
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP
t
RP
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
*
Bank can be reactivated at completion of t
RP
.
DOUT A
0
DOUT A
1
NOP
DOUT A
0
DOUT A
1
DOUT B
0
DOUT B
1
READ B
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*
*
(Burst Length = 4, CAS Latency = 2, 3)
COMMAND
NOP NOP NOP
READ A
Auto-Precharge
t
RP
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP
t
CK2,
DQs
CAS latency = 2
DQM
NOP
DOUT A
0
DIN B
0
DIN B
1
WRITE B
DIN B
2
DIN B
3
NOP
DIN B
4
*
Bank can be reactivated at completion of t
RP
.
t
RP
is a function of clock cycle time and speed sort..
See the Clock Frequency and Latency table.
*
(Burst Length = 8, CAS Latency = 2)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
20
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-
precharge cannot be reactivated until t
DAL
, Data-in to Active delay, is satisfied.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.
It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the
write. The bank undergoing auto-precharge can not be reactivated until t
DAL
is satisfied.
Burst Write with Auto-Precharge
Burst Write with Auto-Precharge Interrupted by Write
DIN A
0
COMMAND
NOP NOP NOP NOP
WRITE A
Auto-Precharge
DIN A
1
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP
DIN A
0
DIN A
1
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
NOP NOP NOP
*
Bank can be reactivated at completion of t
DAL
.
t
DAL
t
DAL
*
*
(Burst Length = 2, CAS Latency = 2, 3)
See the Clock Frequency and Latency table.
t
DAL
is a function of clock cycle time and speed sort.
DIN A
0
COMMAND NOP NOP NOP
WRITE A
Auto-Precharge
DIN A
1
t
DAL
CK
T0 T1 T2 T3 T4 T5
NOP
t
CK3,
DQs
CAS latency = 3
WRITE B
DIN B
0
DIN B
1
DIN B
2
DIN B
3
T6 T7 T8
NOP NOP NOP
*
Bank can be reactivated at completion of t
DAL
.
*
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
t
DAL
is a function of clock cycle time and speed sort.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
21
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered
when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-
charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which
bank(s) is to be precharged when the command is issued.
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a
delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is
known as t
DPL
, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be
executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-
charge time (t
RP
).
Burst Write with Auto-Precharge Interrupted by Read
Bank Selection for Precharge by Address Bits
A10 Bank Select Precharged Bank(s)
LOW BA0, BA1 Single bank defined by BA0, BA1
HIGH DONT CARE All Banks
DIN A
0
COMMAND
NOP NOP NOP
WRITE A
Auto-Precharge
DIN A
1
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP NOP
*
t
CK3,
DQs
CAS latency = 3
Bank A can be reactivated at completion of t
DAL
.
*
READ B
DIN A
2
NOP
DOUT B
0
DOUT B
1
DOUT B
2
t
DAL
t
RP
is a function of clock cycle and speed sort.
COMMAND
NOP NOP NOP WRITE Ax
0
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP NOP
DIN Ax
0
DIN Ax
1
Bank can be reactivated at completion of t
RP
.
*
Activate
Bank Ax
t
CK2,
DQs
CAS latency = 2
t
DPL
*
t
RP
Precharge A
t
DPL
and t
RP
are functions of clock cycle and speed sort.
See the Clock Frequency and Latency table.
(Burst Length = 2, CAS Latency = 2)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
23
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command
is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to
appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
COMMAND
READ Ax
0
NOP NOP NOP NOP NOP NOP NOP
t
CK2,
DQs
CAS latency = 2
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
Precharge A
t
CK3,
DQs
CAS latency = 3
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
t
RP
t
RP
*
*
Bank A can be reactivated at completion of t
RP
.
*
See the Clock Frequency and Latency table.
(Burst Length = 8, CAS Latency = 2, 3)
t
RP
is a function of clock cycle time and speed sort.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
24
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the
device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the
Data-in to Precharge delay, t
DPL
.
Precharge Termination of a Burst Write
COMMAND
NOP NOP NOP WRITE Ax
0
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
NOP NOP NOP
DIN Ax
1
DIN Ax
2
t
DPL
DIN Ax
0
t
CK2,
DQs
CAS latency = 2
NOP
DIN Ax
1
DIN Ax
2
DIN Ax
0
t
CK3,
DQs
CAS latency = 3
DQM
Precharge A
t
DPL
is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
(Burst Length = 8, CAS Latency = 2, 3)
t
DPL
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
25
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic
Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (t
RP
) before
the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the
refresh cycle. No control of the external address pins is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto
Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or
equal to the RAS cycle time (t
RC
).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav-
ing CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the
Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self
Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is
cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device
exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (t
RC
) plus
the Self Refresh exit time (t
SREX
).
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
26
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down
mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (t
RP
) must
occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation,
Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or
Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power
Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does
not perform any refresh operations, therefore the device cant remain in Power Down mode longer than the Refresh period
(t
REF
) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect
Command) is required on the next rising clock edge.
Power Down Mode Exit Timing
COMMAND
NOP COMMAND NOP NOP NOP NOP NOP
CKE
: H or L
CK
Tm Tm+2 Tm+1 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8
t
CES(min)
t
CK
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
27
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is
activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is
activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent
of CAS latency.
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No
Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Com-
mand will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is
brought high, the RAS, CAS, and WE signals become dont cares.
Data Mask Activated during a Read Cycle
COMMAND
NOP READ A NOP NOP NOP NOP NOP NOP NOP
DQM
: H or L
A two-clock delay before
the DQs become Hi-Z
DQs
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
DOUT A
0
DOUT A
1
(Burst Length = 4, CAS Latency = 2)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
28
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks
is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or freezes
any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and
the time at which the SDRAMs operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands
that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE
returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto
the DQ pins will be actively held valid until Clock Suspend mode is exited.
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-
pend mode is exited.
Clock Suspend during a Read Cycle
Clock Suspend during a Write Cycle
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
COMMAND
NOP READ A NOP NOP NOP NOP
CKE
DQs
DOUT A
0
DOUT A
2 DOUT A
1
: H or L
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DOUT element at the DQs when the
suspend operation starts is held valid
(Burst Length = 4, CAS Latency = 2)
CK
T0 T2 T1 T3 T4 T5 T6 T7 T8
COMMAND
NOP WRITE A NOP NOP NOP NOP
CKE
DQs
DIN A
2
DIN A
3
: H or L
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DIN is masked during the Clock Suspend Period
DIN A
1
DIN A
0
(Burst Length = 4, CAS Latency = 2)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
29
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Command Truth Table (See note 1)
Function Device State
CKE
CS RAS CAS WE DQM
BA0,
BA1
A10
A11,
A9-A0
Notes
Previous
Cycle
Current
Cycle
Mode Register Set Idle H X L L L L X OP Code
Auto (CBR) Refresh Idle H H L L L H X X X X
Entry Self Refresh Idle H L L L L H X X X X
Exit Self Refresh
Idle (Self-
Refresh)
L H
H X X X
X X X X
L H H H
Single Bank Precharge
See Current
State Table
H X L L H L X BS L X 2
Precharge all Banks
See Current
State Table
H X L L H L X X H X
Bank Activate Idle H X L L H H X BS Row Address 2
Write Active H X L H L L X BS L Column 2
Write with Auto-Precharge Active H X L H L L X BS H Column 2
Read Active H X L H L H X BS L Column 2
Read with Auto-Precharge Active H X L H L H X BS H Column 2
Reserved H X L H H L X X X X
No Operation Any H X L H H H X X X X
Device Deselect Any H X H X X X X X X X
Clock Suspend Mode Entry Active H L X X X X X X X X
4
Clock Suspend Mode Exit Active L H X X X X X X X X
Data Write/Output Enable Active H X X X X X L X X X
5
Data Mask/Output Disable Active H X X X X X H X X X
Power Down Mode Entry Idle/Active H L
H X X X
X X X X 6, 7
L H H H
Power Down Mode Exit
Any (Power
Down)
L H
H X X X
X X X X 6, 7
L H H H
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the
Current State Truth Table.
2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1
selects bank 3.
3. Not applicable.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device
state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device cant remain in
this mode longer than the Refresh period (t
REF
) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
30
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Enable (CKE) Truth Table
Current State
CKE Command
Action Notes
Previous
Cycle
Current
Cycle
CS RAS CAS WE
BA0,
BA1
A11 - A0
Self Refresh
H X X X X X X X INVALID 1
L H H X X X X X Exit Self Refresh with Device Deselect 2
L H L H H H X X Exit Self Refresh with No Operation 2
L H L H H L X X ILLEGAL 2
L H L H L X X X ILLEGAL 2
L H L L X X X X ILLEGAL 2
L L X X X X X X Maintain Self Refresh
Power Down
H X X X X X X X INVALID 1
L H H X X X X X Power Down mode exit, all banks idle 2
L H L X X X X X ILLEGAL 2
L L X X X X X X Maintain Power Down Mode
All Banks Idle
H H H X X X
Refer to the Idle State section of the
Current State Truth Table
3
H H L H X X 3
H H L L H X 3
H H L L L H X X CBR Refresh
H H L L L L OP Code Mode Register Set 4
H L H X X X
Refer to the Idle State section of the
Current State Truth Table
3
H L L H X X 3
H L L L H X 3
H L L L L H X X Entry Self Refresh 4
H L L L L L OP Code Mode Register Set
L X X X X X X X Power Down 4
Any State
other than
listed above
H H X X X X X X
Refer to operations in the Current State
Truth Table
H L X X X X X X Begin Clock Suspend next cycle 5
L H X X X X X X Exit Clock Suspend next cycle
L L X X X X X X Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE
(t
CES
) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising
clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-
tion.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
31
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Current State Truth Table (Part 1 of 3)(See note 1)
Current State
Command
Action Notes
CS RAS CAS WE BA0,BA1 A11 - A0 Description
Idle
L L L L OP Code Mode Register Set Set the Mode Register 2
L L L H X X Auto or Self Refresh Start Auto or Self Refresh 2, 3
L L H L BS X Precharge No Operation
L L H H BS Row Address Bank Activate Activate the specified bank and row
L H L L BS Column Write w/o Precharge ILLEGAL 4
L H L H BS Column Read w/o Precharge ILLEGAL 4
L H H H X X No Operation No Operation
H X X X X X Device Deselect No Operation or Power Down 5
Row Active
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge Precharge 6
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write Start Write; Determine if Auto Precharge 7, 8
L H L H BS Column Read Start Read; Determine if Auto Precharge 7, 8
L H H H X X No Operation No Operation
H X X X X X Device Deselect No Operation
Read
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge Terminate Burst; Start the Precharge
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write Terminate Burst; Start the Write cycle 8, 9
L H L H BS Column Read Terminate Burst; Start a new Read cycle 8, 9
L H H L X X Burst Stop Burst Stop
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Write
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge Terminate Burst; Start the Precharge
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write Terminate Burst; Start a new Write cycle 8, 9
L H L H BS Column Read Terminate Burst; Start the Read cycle 8, 9
L H H L X X Burst Stop Burst Stop
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t
RAS
) must be satisfied.
7. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
32
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Read with
Auto Pre-
charge
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL 4
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write ILLEGAL 4
L H L H BS Column Read ILLEGAL 4
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Write with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL 4
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write ILLEGAL 4
L H L H BS Column Read ILLEGAL 4
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Precharging
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge No Operation; Bank(s) idle after t
RP
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write ILLEGAL 4
L H L H BS Column Read ILLEGAL 4
L H H H X X No Operation No Operation; Bank(s) idle after t
RP
H X X X X X Device Deselect No Operation; Bank(s) idle after t
RP
Row
Activating
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL 4
L L H H BS Row Address Bank Activate ILLEGAL 4, 10
L H L L BS Column Write ILLEGAL 4
L H L H BS Column Read ILLEGAL 4
L H H H X X No Operation No Operation; Row Active after t
RCD
H X X X X X Device Deselect No Operation; Row Active after t
RCD
Current State Truth Table (Part 2 of 3)(See note 1)
Current State
Command
Action Notes
CS RAS CAS WE BA0,BA1 A11 - A0 Description
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t
RAS
) must be satisfied.
7. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
33
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Write
Recovering
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL 4
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write Start Write; Determine if Auto Precharge 9
L H L H BS Column Read Start Read; Determine if Auto Precharge 9
L H H H X X No Operation No Operation; Row Active after t
DPL
H X X X X X Device Deselect No Operation; Row Active after t
DPL
Write
Recovering
with
Auto Pre-
charge
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL 4
L L H H BS Row Address Bank Activate ILLEGAL 4
L H L L BS Column Write ILLEGAL 4, 9
L H L H BS Column Read ILLEGAL 4, 9
L H H H X X No Operation No Operation; Precharge after t
DPL
H X X X X X Device Deselect No Operation; Precharge after t
DPL
Refreshing
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL
L L H H BS Row Address Bank Activate ILLEGAL
L H L L BS Column Write ILLEGAL
L H L H BS Column Read ILLEGAL
L H H H X X No Operation No Operation; Idle after t
RC
H X X X X X Device Deselect No Operation; Idle after t
RC
Mode
Register
Accessing
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L BS X Precharge ILLEGAL
L L H H BS Row Address Bank Activate ILLEGAL
L H L L BS Column Write ILLEGAL
L H L H BS Column Read ILLEGAL
L H H H X X No Operation No Operation; Idle after two clock cycles
H X X X X X Device Deselect No Operation; Idle after two clock cycles
Current State Truth Table (Part 3 of 3)(See note 1)
Current State
Command
Action Notes
CS RAS CAS WE BA0,BA1 A11 - A0 Description
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t
RAS
) must be satisfied.
7. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
34
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Absolute Maximum Ratings
Symbol Parameter Rating Units Notes
V
DD
Power Supply Voltage -1.0 to +4.6 V 1
V
DDQ
Power Supply Voltage for Output -1.0 to +4.6 V 1
V
IN
Input Voltage -0.3 to V
DD
+0.3 V 1
V
OUT
Output Voltage -0.3 to V
DD
+0.3 V 1
T
A
Operating Temperature (ambient)
Commerical 0 to +70 C 1
Industrial -40 to +85 C 1
T
STG
Storage Temperature -55 to +150 C 1
P
D
Power Dissipation 1.0 W 1
I
OUT
Short Circuit Output Current 50 mA 1
1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended DC Operating Conditions
Symbol Parameter
Rating
Units Notes
Min. Typ. Max.
V
DD
Supply Voltage 3.0 3.3 3.6 V 1
V
DDQ
Supply Voltage for Output 3.0 3.3 3.6 V 1
V
IH
Input High Voltage 2.0 3.0 V
DD
+ 0.3 V 1, 2
V
IL
Input Low Voltage -0.3 0 0.8 V 1, 3
V
OH
Output Logic High Voltage 2.4 V I
oH
= ~mA
V
OL
Output Logic [o; Voltage 04 V I
oL
= mA
1. All voltages referenced to V
SS
and V
SSQ
.
2. V
IH
(max) = V
DD
+ 2.3V for pulse width 3ns.
3. V
IL
(min) = V
SS
- 2.0V for pulse width 3ns.
Capacitance (T
A
= 23C, f = 1MHz, V
DD
= 3.3V, V
REF
=1.4+/-200mV )
Symbol Parameter Min.
64Mb
Max.
128Mb
Max.
Units
C
IN
Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) 2.5 5.0 3.8 pF
C
ADD
Address 2.5 5.0 3.8 pF
C
CLK
Input Clock (CLK) 2.5 4.0 3.5 pF
C
OUT
Output Capacitance (DQ0 - DQ15) 4.0 6.5 6.0 pF
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
35
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DC Electrical Characteristics (V
DD
= 3.3V 0.3V)
Symbol Parameter Min. Max. Units
I
I(L)
Input Leakage Current, any input
(0.0V V
IN
V
DD
), All Other Pins Not Under Test = 0V
-1 +1 A
I
O(L)
Output Leakage Current
(D
OUT
is disabled, 0.0V V
OUT
V
DDQ
)
-1 +1 A
V
OH
Output Level (LVTTL)
Output H Level Voltage (
IOUT
= -2.0mA)
2.4 V
V
OL
Output Level (LVTTL)
Output L Level Voltage (I
OUT
= +2.0mA)
0.4 V
DC Output Load Circuit
Output
1200
50pF
3.3 V
870
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
36
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
dc
Operating, Standby, and Refresh Currents
Parameter Symbol Test Condition
Max.
Units Notes
6K 6KI 75B 75BI
Operating Current I
CC1
1 bank operation
t
RC
= t
RC
(min), t
CK
= min
Active-Precharge command cycling without
burst operation
130 130 90 90 mA 1, 2, 3
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE V
IL
(max), t
CK
= min,
CS = V
IH
(min)
4 4 4 4 mA 1
I
CC2PS
CKE V
IL
(max), t
CK
= Infinity,
CS = V
IH
(min)
4 4 4 4 mA 1
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
CKE V
IH
(min), t
CK
= min,
CS = V
IH
(min)
20 20 20 20 mA 1, 5
I
CC2NS
CKE V
IH
(min), t
CK
= Infinity, 10 10 10 10 mA 1, 7
No Operating Current
(Active state: 4 bank)
I
CC3N
CKE V
IH
(min), t
CK
= min,
CS = V
IH
(min)
35 35 35 35 mA 1, 5
I
CC3P
CKE V
IL
(max), t
CK
= min, 5 7 5 7 mA 1, 6
Operating Current (Burst
Mode)
I
CC4
t
CK
= min, Read/ Write command cycling,
Multiple banks active, gapless data, BL = 4
150 150 110 110 mA 1, 3, 4
Auto (CBR) Refresh Current I
CC5
t
CK
= min, t
RC
= t
RC
(min)
CBR command cycling
220 220 200 200 mA 1
Self Refresh Current I
CC6
CKE 0.2V 4 4 4 4 mA 1
1. Currents given are valid for a single device. .
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
. Input
signals are changed up to three times during t
RC
(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t
CK
(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
37
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Characteristics (V
DD
= 3.3V 0.3V)
1. An initial pause of 200s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
4. Load Circuit A: AC timing tests have V
IL
= 0.4 V and V
IH
= 2.4 V with the timing referenced to the 1.40V crossover point
5. Load Circuit A: AC measurements assume t
T
= 1.0ns.
AC Characteristics Diagrams
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
1.4V
1.4V
t
T
Vtt = 1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit (A)
t
CKH
t
CKL
V
IL
V
IH
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
38
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock and Clock Enable Parameters
Symbol Parameter
-6K/6KI -75B/75BI
Units Notes
Min. Max. Min. Max.
t
CK3
Clock Cycle Time, CAS Latency = 3 6 7.5 ns
t
CK2
Clock Cycle Time, CAS Latency = 2 10 10 ns
t
AC3 (A)
Clock Access Time, CAS Latency = 3 5 5.4 ns 1
t
AC2 (A)
Clock Access Time, CAS Latency = 2 6 6 ns 1
t
CKH
Clock High Pulse Width 2.5 2.5 ns
t
CKL
Clock Low Pulse Width 2.5 2.5 ns
t
CES
Clock Enable Set-up Time 1.5 1.5 ns
t
CEH
Clock Enable Hold Time 0 0.8 ns
t
SB
Power down mode Entry Time 0 6 0 7.5 ns
t
T
Transition Time (Rise and Fall) 0.3 8 0.5 10 ns
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
Common Parameters
Symbol Parameter
-6K/6KI -75B/75BI
Units Notes
Min. Max. Min. Max.
t
CS
Command Setup Time 1.5 1.5 ns
t
CH
Command Hold Time 0.8 0.8 ns
t
AS
Address and Bank Select Set-up Time 1.5 1.5 ns
t
AH
Address and Bank Select Hold Time 0.8 0.8 ns
t
RCD
RAS to CAS Delay 18 20 ns 1
t
RC
Bank Cycle Time 54 67.5 ns 1
t
RAS
Active Command Period 36 100K 45 100K ns 1
t
RP
Precharge Time 16 20 ns 1
t
RRD
Bank to Bank Delay Time 12 15 ns 1
t
CCD
CAS to CAS Delay Time 1 1 CK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol Parameter
-6K/6KI -75B/75BI
Units
Min. Max. Min. Max.
t
RSC
Mode Register Set Cycle Time 12 15 ns
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
39
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Read Cycle
Symbol Parameter
-6K/6KI -75B/75BI
Units Notes
Min. Max. Min. Max.
t
OH
Data Out Hold Time
ns 1
2.5 2.7 ns 2, 4
t
LZ
Data Out to Low Impedance Time 0 0 ns
t
HZ
Data Out to High Impedance Time 3 6 3 7 ns 3
t
DQZ
DQM Data Out Disable Latency 2 2 CK
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
Symbol Parameter
-6K/6KI -75B/75BI
Units Notes
Min. Max. Min. Max.
t
REF
Refresh Period 64 64 ms 1
t
SREX
Self Refresh Exit Time 1 1 CK
1. 4096 auto refresh cycles.
Write Cycle
Symbol Parameter
-6K/6KI -75B/75BI
Units
Min. Max. Min. Max.
t
DS
Data In Set-up Time 1.5 1.5 ns
t
DH
Data In Hold Time 1 0.8 ns
t
DPL
Data input to Precharge 12 15 ns
t
WR
Write Recovery Time 12 15 ns
t
DAL3
Data In to Active Delay, CAS Latency = 3 5 5 CK
t
DAL2
Data In to Active Delay, CAS Latency = 2 4 4 CK
t
DQW
DQM Write Mask Latency 0 0 CK
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
40
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Frequency and Latency
Symbol Parameter -6K/6KI -75B/75BI Units
f
CK
Clock Frequency 166 133 MHz
t
CK
Clock Cycle Time 6.0 7.5 ns
t
AA
CAS Latency 3 3 CK
t
RP
Precharge Time 3 3 CK
t
RCD
RAS to CAS Delay 3 3 CK
t
RC
Bank Cycle Time 10 9 CK
t
RAS
Minimum Bank Active Time 7 6 CK
t
DPL
Data In to Precharge 2 2 CK
t
DAL
Data In to Active/Refresh 5 5 CK
t
RRD
Bank to Bank Delay Time 2 2 CK
t
CCD
CAS to CAS Delay Time 1 1 CK
t
WL
Write Latency 0 0 CK
t
DQW
DQM Write Mask Latency 0 0 CK
t
DQZ
DQM Data Disable Latency 2 2 CK
t
CSL
Clock Suspend Latency 1 1 CK
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
41
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Parameters for Write Timing
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
*
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
4
T
1
0
T
1
6
T
1
7
T
1
8
T
1
9
T
1
5
T
2
2
T
2
0
T
2
1
H
i
-
Z
A
1
0
A
0
-
A
9
,
t
C
E
S
t
C
S t
C
H
t
A
S
t
R
C
D
t
D
A
L
t
D
S
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
W
r
i
t
e
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
0
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
1
W
r
i
t
e
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
1
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
W
r
i
t
e
C
o
m
m
a
n
d
B
a
n
k
0
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
0
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
t
D
H
A
x
0
A
x
3
A
x
2
A
x
1
B
x
0
B
x
3
B
x
2
B
x
1
A
y
0
A
y
3
A
y
2
A
y
1
t
C
K
2
t
C
K
H
t
C
K
L
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
1
R
A
y
C
B
x
C
A
y
R
A
y
R
B
x
R
B
x
C
A
x
R
B
y
R
B
y
R
A
z
R
A
z
R
A
x
R
A
x
t
A
H
*
B
A
0
=
B
a
n
k
2
,
3
=
I
d
l
e
t
R
C
t
C
E
H
t
D
P
L
t
R
P
t
R
R
D
t
D
P
L
a
n
d
t
D
A
L
d
e
p
e
n
d
o
n
c
l
o
c
k
c
y
c
l
e
t
i
m
e
a
n
d
(
B
u
r
s
t
l
e
n
g
t
h
=
4
,
C
A
S
l
a
t
e
n
c
y
=
2
)
s
p
e
e
d
s
o
r
t
.
S
e
e
t
h
e
C
l
o
c
k
F
r
e
q
u
e
n
c
y
a
n
d
L
a
t
e
n
c
y
T
a
b
l
e
.
A
1
1
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
42
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Parameters for Read Timing (3/3/3)
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
*
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
0
H
i
-
Z
A
1
0
A
0
-
A
9
,
t
R
C
D
t
R
A
S
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
1
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
t
C
K
3
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
1
t
R
C
t
A
C
3
t
O
H
B
x
0
B
x
1
C
B
x
R
A
y
R
B
x
R
B
x
R
A
y
C
A
x
R
A
x
R
A
x
*
B
A
0
=
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
0
B
a
n
k
2
,
3
=
I
d
l
e
t
R
P
B
x
2
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
1
t
R
R
D
A
x
3
A
x
2
A
x
1
A
x
0
(
B
u
r
s
t
l
e
n
g
t
h
=
4
,
C
A
S
l
a
t
e
n
c
y
=
3
;
t
R
C
D
,
t
R
P
=
3
)
A
1
1
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
43
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Parameters for Read Timing (2/2/2)
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
*
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
0
H
i
-
Z
A
1
0
t
C
S
t
C
H
t
C
E
H
t
A
S
t
A
H
t
R
R
D
t
R
C
D
t
R
A
S
(
m
i
n
)
t
L
Z
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
1
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
t
C
E
S
t
C
K
2
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
1
t
R
C
t
R
P
t
A
C
2
t
O
H
t
H
Z
t
C
K
H
B
x
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
1
B
x
1
t
H
Z
C
B
x
R
A
y
R
B
x
R
B
x
R
A
y
C
A
x
R
A
x
R
A
x
t
C
K
L
A
x
0
A
x
1
*
B
A
0
=
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
0
B
a
n
k
2
,
3
=
I
d
l
e
t
R
P
N
o
t
e
:
M
u
s
t
s
a
t
i
s
f
y
t
R
A
S
(
m
i
n
)
F
o
r
-
2
6
0
:
e
x
t
e
n
d
t
R
C
D
1
c
l
o
c
k
(
B
u
r
s
t
l
e
n
g
t
h
=
2
,
C
A
S
l
a
t
e
n
c
y
=
2
;
t
R
C
D
,
t
R
P
=
2
)
A
0
-
A
9
,
A
1
1
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
44
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Parameters for Read Timing (3/2/2)
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
*
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
0
H
i
-
Z
A
1
0
t
C
S
t
C
H
t
C
E
H
t
A
S
t
A
H
t
R
C
D
t
L
Z
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
1
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
t
C
K
3
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
1
t
R
P
t
A
C
3
t
O
H
t
H
Z
t
C
K
H
B
x
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
1
B
x
1
t
H
Z
C
B
x
R
A
y
R
B
x
R
B
x
R
A
y
C
A
x
R
A
x
R
A
x
t
C
K
L
A
x
0
A
x
1
*
B
A
0
=
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
0
B
a
n
k
2
,
3
=
I
d
l
e
t
R
P
t
C
E
S
N
o
t
e
:
M
u
s
t
s
a
t
i
s
f
y
t
R
A
S
(
m
i
n
)
.
E
x
t
e
n
d
e
d
t
R
C
D
1
c
l
o
c
k
.
N
o
t
r
e
q
u
i
r
e
d
f
o
r
B
L
4
.
t
R
R
D
t
R
A
S
t
R
C
(
B
u
r
s
t
l
e
n
g
t
h
=
2
,
C
A
S
l
a
t
e
n
c
y
=
3
;
t
R
C
D
,
t
R
P
=
2
)
A
0
-
A
9
,
A
1
1
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
45
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Parameters for Read Timing (3/3/3)
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
*
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
0
H
i
-
Z
A
1
0
A
0
-
A
9
,
t
R
R
D
t
R
C
D
t
R
A
S
(
m
I
n
)
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
1
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
t
C
K
3
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
1
t
R
C
t
R
P
t
A
C
3
t
O
H
B
x
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
1
B
x
1
C
B
x
R
A
y
R
B
x
R
B
x
R
A
y
C
A
x
R
A
x
R
A
x
R
e
a
d
w
i
t
h
A
u
t
o
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
B
a
n
k
0
B
e
g
i
n
A
u
t
o
P
r
e
c
h
a
r
g
e
B
a
n
k
0
t
R
P
A
x
0
A
x
1
N
o
t
e
:
M
u
s
t
s
a
t
i
s
f
y
t
R
A
S
(
m
i
n
)
.
E
x
t
e
n
d
e
d
t
R
C
D
n
o
t
r
e
q
u
i
r
e
d
f
o
r
B
L
4
.
t
C
E
H
A
1
1
T
1
4
*
B
A
0
=
B
a
n
k
2
,
3
=
I
d
l
e
(
B
u
r
s
t
l
e
n
g
t
h
=
2
,
C
A
S
l
a
t
e
n
c
y
=
3
;
t
R
C
D
,
t
R
P
=
3
)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
46
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Mode Register Set
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
B
A
0
,
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
4
T
1
0
T
1
6
T
1
7
T
1
8
T
1
9
T
1
5
T
2
2
T
2
0
T
2
1
H
i
-
Z
A
1
0
,
A
1
1
A
0
-
A
9
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
A
l
l
B
a
n
k
s
M
o
d
e
R
e
g
i
s
t
e
r
S
e
t
C
o
m
m
a
n
d
A
n
y
C
o
m
m
a
n
d
A
d
d
r
e
s
s
K
e
y
t
R
P
t
C
K
2
t
R
S
C
(
C
A
S
l
a
t
e
n
c
y
=
2
)
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
47
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Power-On Sequence and Auto Refresh (CBR)
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
B
S
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
4
T
1
0
T
1
6
T
1
7
T
1
8
T
1
9
T
1
5
T
2
2
T
2
0
T
2
1
H
i
-
Z
A
1
0
A
0
-
A
9
,
P
r
e
c
h
a
r
g
e
C
o
m
m
a
n
d
A
l
l
B
a
n
k
s
t
R
P
M
i
n
i
m
u
m
o
f
8
R
e
f
r
e
s
h
C
y
c
l
e
s
a
r
e
r
e
q
u
i
r
e
d
1
s
t
A
u
t
o
R
e
f
r
e
s
h
C
o
m
m
a
n
d
t
R
C
H
i
g
h
l
e
v
e
l
i
s
r
e
q
u
i
r
e
d
8
t
h
A
u
t
o
R
e
f
r
e
s
h
C
o
m
m
a
n
d
I
n
p
u
t
s
m
u
s
t
b
e
s
t
a
b
l
e
f
o
r
2
0
0
s
t
C
K
A
n
y
C
o
m
m
a
n
d
2
C
l
o
c
k
m
i
n
.
M
o
d
e
R
e
g
i
s
t
e
r
A
d
d
r
e
s
s
K
e
y
S
e
t
C
o
m
m
a
n
d
A
1
1
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
48
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Suspension / DQM During Burst Read
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
4
T
1
0
T
1
6
T
1
7
T
1
8
T
1
9
T
1
5
T
2
2
T
2
0
T
2
1
H
i
-
Z
A
1
0
A
0
-
A
9
,
R
A
x
A
x
0
A
x
1
A
x
2
A
x
3
A
c
t
i
v
a
t
e
C
o
m
m
a
n
d
B
a
n
k
0
C
l
o
c
k
S
u
s
p
e
n
d
2
C
y
c
l
e
s
C
l
o
c
k
S
u
s
p
e
n
d
1
C
y
c
l
e
C
l
o
c
k
S
u
s
p
e
n
d
3
C
y
c
l
e
s
R
A
x
R
e
a
d
C
o
m
m
a
n
d
B
a
n
k
0
C
A
x
t
H
Z
t
C
K
3
*
B
A
1
A
x
4
A
x
6
A
x
7
t
C
E
S
t
C
E
H
*
B
A
0
=
B
a
n
k
2
,
3
=
I
d
l
e
(
B
u
r
s
t
l
e
n
g
t
h
=
8
,
C
A
S
l
a
t
e
n
c
y
=
3
;
t
R
C
D
=
3
)
A
1
1
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
49
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Suspension / DQM During Burst Write
\
C
K
C
K
E
C
S
D
Q
R
A
S
C
A
S
W
E
*
B
A
1
D
Q
M
T
2
T
3
T
4
T
0
T
1
T
6
T
7
T
8
T
9
T
5
T
1
1
T
1
2
T
1
3
T
1
4
T
1
0
T
1
6
T
1
7
T
1
8
T
1
9
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50
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9/2008
51
NANYA TECHNOLOGY CORPORATION
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9/2008
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9/2008
54
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9/2008
55
NANYA TECHNOLOGY CORPORATION
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NT5SV8M16FS / NT5SV8M16FT
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9/2008
56
NANYA TECHNOLOGY CORPORATION
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61
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
62
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
CS Function (Only CS signal needs to be asserted at minimum rate)
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
63
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions (400mil; 54 lead; Thin Small Outline Package)
Lead #1
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
64
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Revision Log
Rev Date Modification
1.0 Sep 2006 Official Release
1.1 Jan 2007 Add Waveforms
1.2 Oct 2007 Add ICC data max description
1.3 Sep 2008
Add burst stop command in State Truth Table
Support industrial temperature scope
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.3
9/2008
65
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Nanya Technology Corporation.
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of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTCs
standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this
warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government
requirements.
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