Many existing approaches on \ufb02ash-memory management are based on RAM-resident tables in which one single granularity size is used for both address translation and space management. As high-capacity \ufb02ash- memory is becoming a\ufb00ordable more than ever, the dilemma of how to manage the RAM space or how to improve the access performance is emerging for many vendors. In this paper, we propose a tree-based man- agement scheme which adopts multiple granularities in \ufb02ash-memory man- agement. Our objective is to not only reduce the run-time RAM footprint but also manage the write workload, due to housekeeping. The proposed method was evaluated under realistic workloads, where signi\ufb01cant advan- tages over existing approaches were observed, in terms of the RAM space, access performance, and \ufb02ash-memory lifetime.
Flash-memory is non-volatile, shock-resistant, and power-economic. With re- cent technology breakthroughs in both capacity and reliability, \ufb02ash-memory storage systems are much more a\ufb00ordable than ever. As a result, \ufb02ash-memory is now among the top choices for storage media in embedded systems. For ex- ample, \ufb02ash-memory storage systems could provide good vibration tolerance for
manufacturing systems. Compared to hard disks, \ufb02ash-memory is more suitable to mobile devices since solid-state devices inherently consume less energy than mechanical devices do.
Due to the very distinct characteristics of \ufb02ash memory, management schemes for traditional memory systems (e.g., DRAM and disks) could not be directly applied to \ufb02ash memory without introducing signi\ufb01cant performance degrada- tion. In particular, \ufb02ash memory is a kind of write-once and bulk-erase medium. For performance consideration, updates to data are usually handled in an out- place fashion, rather than by directly overwriting old data. With respect to a piece of data, under out-place updates, its newest version is written to some available space and its old copies are considered as being invalidated. Because where a piece of data resides on \ufb02ash memory might be changed from time to time due to out-place updates, a piece of data is associated with logical ad- dresses for its identi\ufb01cation. Thus how to e\ufb03ciently translate logical addresses into \ufb02ash-memory (physical) addresses is important. Besides address transla- tion, space on \ufb02ash memory already written (programmed) with data can not be overwritten unless it is erased. As data are written to \ufb02ash memory, the amount of space available to writes would become low, and to recycle space occupied by invalidated data by erasure is necessary. Erase operations bring two challenges to the management of space over \ufb02ash memory: First, erasure must be performed over a relatively large space (compare to that for a read and a write), so valid data might be involved in erasure. Second, any portion of \ufb02ash memory could tolerant only a limited number of erase operations before it becomes unreliable. Intensively erasing some certain \ufb02ash-memory space must be avoided.
Most of the existing implementations of \ufb02ash-memory storage systems adopt static data structures for their management. To be speci\ufb01c, two RAM-resident1 tables for address translation and space management are adopted. Address translation and space management are handled with a \ufb01xed granularity size, which commonly ranges from 512B to 16KB (it highly depends on the charac- teristics of each \ufb02ash-memory physical design). For example, if the granularity size is 512B, then one entry of the address translation table and one entry of the space management table cover 512B of logical space and 512B of physical space, respectively. The granularity size is a permanent and unchangeable system pa- rameter, and the choosing of the granularity size could be important. Such a design works pretty well for small-scale \ufb02ash-memory storage systems. When high-capacity \ufb02ash memory is considered2, a dilemma of a small RAM footprint size or e\ufb03cient on-line access performance is then faced: Fine-grain tables are e\ufb03cient in handling small requests and coarse-grain tables are conservative in RAM usages. Conversely, RAMspace requirements of \ufb01ne-grain tables could be una\ufb00ordable, and coarse-grain tables could provide poor performance for on-line access (please refer to experiments in Section 6).
managed by the operating system, e.g.,SmartM ediaTM . RAM can also be the embedded RAM on stand-alone \ufb02ash-memory storage devices such as that onC ompactF lashTM cards and USB \ufb02ash drives.
interesting observations were obtained (Please see Section 6.1 for details): The sizes of most writes are either pretty large (\u2265 64KB) or very small (\u2264 4KB), where small writes show signi\ufb01cant spatial localities, while many large writes tend to be sequential. In other words, the majority of the entire logical address space is accessed by large-size writes. This research is motivated by the needs of a \ufb02exible \ufb02ash-memory scheme with multiple graularities. When the capacity of \ufb02ash memory increases, people might consider a large management unit, such as multiple pages per management unit. Distinct from such an approach, the purpose of this work is to exploit how multi-granularity management could help in the balancing of the RAM footprint and the run-time performance. We proposed tree-based data structures and algorithms to balance the RAMspace requirements and the performance of on-line access. The main contributions of this work are as follows:
RAMspace for \ufb02ash-memory management but also restrict the write work- load to \ufb02ash memory, especially when high-capacity \ufb02ash memory is con- sidered.
The rest of this paper is organized as follows: An architectural view of \ufb02ash memory is detailed in Section 2. Section 3 introduces prior research related to the topics of \ufb02ash-memory management. In Section 4, we propose a tree- based approach to handle space management and address translation for \ufb02ash memory with variable sizes of granularity. Section 5 further extends our focus to the issues of run-time RAMspace requirements and \ufb02ash-memory endurance. The proposed tree-based scheme were evaluated and compared against a static table-driven scheme in Section 6. We concluded this paper in Section 7.
There are di\ufb00erent kinds of \ufb02ash memory available in the current market. In this section, we introduce the commonly adopted NAND \ufb02ash memory and its hardware characteristics.
There are two major types of \ufb02ash memory in the current market: NAND and NOR \ufb02ash memory. NAND \ufb02ash memory is mainly designed for data stor- age, and NOR \ufb02ash memory is for EEPROM replacement. Because NOR \ufb02ash adopts standard memory interface, the processor could directly execute pro- grams stored on it (such an ability is also called eXecute-In-Place, XIP). Table 1 shows comparisons between NAND \ufb02ash memory and NOR \ufb02ash memory. We focus this paper on NAND \ufb02ash memory because NAND \ufb02ash memory is more suitable for storage systems . Regarding \ufb02ash-memory storage sys- tem implementations, there are two major approaches: One is to emulate \ufb02ash
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