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Resume Prasanjeet

Resume Prasanjeet

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Published by api-3805096
my resume as updated on feb 2007
my resume as updated on feb 2007

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Published by: api-3805096 on Oct 17, 2008
Copyright:Attribution Non-commercial


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PHONE: 091-7104-235178,091-9890627466 \u2022 E-MAIL: PRASAN1400@GMAIL.COM
Leveraging my skills and discipline abilities for an active career in research and development..
To gain on the technical knowledge and to excel in the sphere of electronics engineering.
Bachelor of Engineering, Electronics and Telecommunications Engineering.
Name of Institute:
Yeshwantrao Chavan College of Engineering, Nagpur
Nagpur University
Pass with distinction (82 %)
All India Senior School Certificate Examination, 2002 (XIIth Board)
Name of Institute:
Kendriya Vidyalaya O.F.Ambajhari, Nagpur
Central Board Of Secondary Education (C.B.S.E)
Pass with distinction (91.8%)
All India Secondary School Examination, 2000 (Xth Board)
Name of Institute:
Kendriya Vidyalaya O.F.Eddumailaram, Medak
Central Board Of Secondary Education (C.B.S.E)
Pass with distinction (90.6%)
PG Diploma Program in VLSI Design 23rd Batch. (September,2006 to February,2007 )
Name of Institute :
Sandeepani School of VLSI Design.
(A Training Division of CG-CoreEL Programmable Solutions (P) Ltd).

Implementation of Industrial Process Controller Using Lab VIEW 7.1(July 2005 to February

In this project we have tried to control the production operations of an industrial (PASUPATI
ACRYLON LTD, Moradabad) process that deals with the manufacturing of acrylic fiber.
The project adds significant flexibility and customization to the industrial control hardware and
deals with the use of the integrated Lab VIEW environment to interface with real-world signals.

Multi-User Access Control System Using VHDL(January 2005 to May 2005)
This project aimed to develop an FSM based Combinational Lock using VHDL which could be
implemented as simple access control system or as a security system in bank lockers, safes etc.
E3-Transmit Framer Using VHDL (September 2006)

This project is aimed at generation of E3 framed data, which is used in synchronous serial transmission of data via telephone lines using TDM. The E3 transmitter is developed and tested functionally by coding and testing using test bench in VHDL.

Digital Alarm Clock Using Verilog (September 2006)

A Digital Alarm Clock, which can display current time, load new time, set alarm time and Sound alarm, was implemented in Verilog HDL. The design was implemented using a Finite State Machine (FSM) to control the operations of the clock. Test benches were written and the functionality was verified.

Round Robin Arbiter Using System Verilog(November 2006)

The arbiter is to control the access of three processors connected to same SRAM. The testing of
arbiter comprises of generation of constrained random test vectors and checking complete
functional coverage using cover property and assert property by using System Verilog for
complete assertion based verification of the arbiter using Questa-Sim.

Design of Complete Data Path and Control Unit of Pico Processor along with PS-2 Keyboard
Interface and VGA interface Using VHDL (October 2006 to January 2007)

The front end project I undertook in Sandeepani is the design and implementation of complete
data path and control unit of Pico processor ISA which comprises of 34 instructions. I designed
the complete control unit base on FSM approach which inculcates the multi cycle
implementation. The longest cycle comprises of 5 clock cycles. The complete design and
verification is done usingVHDL.Modelsim simulator is used for the functional verification of
the design and Leonardo Spectrum is used for the synthesizing the RTL from VHDL code.
Then the complete design is implemented on Spartan 3 board by doing the place and route on

Xilinx ISE simulator. Then the back annotated standard delay wave is checked for real time
simulation using Modelsim again and then finally the design is targeted to theSpartan- 3
XCS200256 device by using IMPACT. Later, I also developed the PS-2 Keyboard interface and
VGA interface for the same and demonstrated it at the Programmable Solutions in India
seminar conducted by Xilinx in Bangalore on 14th December 2006.
Use of thermal imaging in biomedical engineering
Presented a technical paper on this title at the National level paper presentation
Competition organized by S.V. Institute of Computer Studies, Kadi (Gujarat).
Antimatter and space propulsion
Presented a technical paper on this title at the \u201cIdea presentation\u201d competition
organized by YCCE, Nagpur (India).

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