Dual Voltage Controller Based Power Factor

Correction Circuit for Faster Dynamucs and Zero

Steady State Error
Manoj Rathi Nitin Bhiwapurkar Ned Mohan
Dept of Electrical Engineering,
University of Minnesota, Minneapolis, MN 55455, USA

marathi@ece.umn.edu nitinb@ece.umn.edu mohan8ece.umn.edu

Abstract- This paper analyzes dual voltage controllers for 11. CONVENTIONAL POWER FACTOR
CORRECTION
single-phase Power Factor Correction(PFC) Circuits using boost Usrsc BOOSTTOPOLOGY
CIRCUIT
topology. The proposed scheme uses dual voltage controllers, one
of the voltage controller having low bandwidth operates only dnr- In the conventional Power Factor Correction (PFC) circuit
ing steady condition, other voltage controller with high bandwidth using boost topology as shown in Fig. 1, with high power fac-
operates during the transient condition. At any given instant only
one voltage controller is in circuit. Lower bandwidth controller, tor, the input current is in phase with the input voltage. The
operating during steady state condition, maintains the THD within instantaneous power is given by eqn. 1.
the required limits and the dc-bus voltage at its reference value.
High handwidth controller improves the transient performance by P;, = VpkIpkSiTl2Wt (1)
having faster response to the disturbance. Faster response to dis-
turbances necessitates less energy storage in the dc-bus capacitor,
hence a smaller capacitance value is required which resulting in where Vpk and Ipk are the peak values of voltage and current
a compact and a light-weight circuit. The comparative study he- andw=Zxf.
tween the proposed scheme and the conventional PFC circuit is
carried out. The experimental results for the proposed scheme are L n
also presented.
Index Terms-Power factor correction (PFC), Boost Topology,
Dual voltage controller.

I. INTRODUCTION

I N a single-phase rectifier, the output capacitor draws current

only when the input AC voltage is greater than the output dc-
bus voltage, resulting in a non-sinusoidal input current. Hence
Fig. 1. Basic Block of Convention PFC

the Total Harmonic Distortion (THD) of the input current is

very high. To reduce the input current THD and to improve The eqn. 1 can be further simplified to
the power factor of the circuit;Power Factor Correction (PFC)
circuits using boost converters are very popular. 1
P,n = ZVpk'pk(1 - Cos(ht)) ('2)
The conventional power factor circuit has second harmonic
component in the dc-bus voltage, which is fed back to voltage Considering the ideal converter, the input power is equal to the
controller. As the output of voltage controller contains the sec- output power, we can write
ond harmonic component, so the current controller tries to com-
pensate for the second harmonic component, which distorts the
p,n = Po (3)
input current. The bandwidth of the voltage controller is kept
low in order to limit the input current distortion, which results in where Po is the output power. Comparing the eqn. 2' and eqn.
slower response and higher capacitance value requirement. The 3, we can see that the output power contains a and harmonic
proposed scheme uses dual controllers, one operating during component (P,,z) given by Iqn. 4
disturbances and the other operating during steady state condi-
tion. This scheme results in a faster response for disturbances Po2 = - ; E1v p k ' p k C O S ( 2 W t )
and smaller capacitance requirement. (4)

0-7803-7906-3/03/$17.0002003 IEEE. 238

If the output voltage Vdc is assumed to be constant over a power
'
cycle, then we can write :

where I02 is the capacitor current and V02 is the Znd harmonic
ripple voltage, C is the output filter capacitance and f o 2 = 2f
- : ..............
(i.e second harmonic frequency).
~~~ ~ ~~~~

Since the output voltage is fed back to the voltage controller,
the output of the voltage controller also has second harmonic
component. The current controller tries to compensate for the
second harmonic component, resulting in input current distor-
tion. In order to reduce the input current distortion, second
harmonic component to the input of current controller has to
be limited. The value of the capacitor is decided by the desired
holdup time (TfLo(d) and on the maximum second harmonic out-
put voltage ripple allowed in steady state.
As the output filter capacitance value cannot be kept very large,
the Znd harmonic voltage component in the feedback loop is
limited by reducing the bandwidth of the voltage controller,
thus making it slower.
To maintain input current sinusoidal with high power factor,
faster response of voltage control loop is sacrificed making the
output capacitor large and bulky which has to act as a buffer
between load changes and a slower voltage control loop.
D d "ollag. Convolln
Fig. 2. Block Diagram of Proposed PFC
lighter and more compact. Decreasing the value of capacitance
increases the output voltage ripple given by eqn. 5, but however
the slower controller acts during the steady state and takes care
of the voltage ripple in the feedback loop.
During transient conditions, such as load change, the output
voltagedeviates from the reference value. In order to bring this
voltage back to normal quickly, the control in the voltage loop
is switched from Cont-I to Cont-11.
Typically the Cont-I1 is kept in the voltage loop for approx-
imately one power cycle for best response time. The change
of the controller from Cont-I1 to Cont-I causes a change in the
output of current controller since the output of Cont-I and Cont-
I1 is not same. This may cause another transient in the output
voltage. To overcome this problem, the change in the controller
from Cont-I1 to Cont-I is done during the input voltage zero.
The Cont-I and Cont-11 are also designed to have zero steady
state error.

111. PROPOSED CONTROL S C H E M E WITH DUALVOLTAGE IV. DESIGN PARAMETERS A N D CONTROLLER DESIGN
CONTROLLER USING BOOST TOPOLOGY The PFC using boost topology with the proposed scheme is
designed for the specification detailed in Table. I. The value of
As we discussed in earlier section about the conventional
inductor and output capacitors found are detailed in Table. 11.
control scheme and its drawback, the response of the controller
can be improved by using the faster controller with higher band- TABLE I
width during the transient condition and a slower controller in D E S I G N SPECIFICATIONS USED FOR H A R D W A RPROTOTYPE
E
steady state.
The proposed control scheme is shown in Fig. 2 consist of
two voltage controllers, a slower and a faster one. The slower
voltage controller called Cont-I has low bandwidth and is used
only during steady-state operation and the faster voltage con-
troller called Cont-I1 has high bandwidth and operates only dur- 85- 120V,.,,
ing the disturbances. The Cont-I is designed to minimize the
input current distortion, which is exactly similar to the conven-
tional PFC controller.
In the conventional PFC circuits (having only slow volt- TABLE I1
age controller) the input current is distorted during tran- COMPONENT VALUES
sientsldisturbances. During transient conditions, the output
Component
voltage will be fluctuating and this output voltage is fed to the
Output Capacitor
current controller through the voltage controller, which further
Inductor 0.59mH
results in distortion of input current. In the proposed controller
a high bandwidth voltage controller is used during transients.
This results in more input current distortion during transient The two controllers for the proposed control scheme were de-
condition. Since faster controller acts during the transient con- 'signed for 35Hz and 670Hz. The Bode plots of the system with
ditions, transient condition lasts for short duration as compared 35Hz controller and 670Hz controller are shown in Fig. 3 and
to that of low bandwidth controller. This helps to lower the ca- Fig. 4 respectively. The change in controllers is implemented
pacitance requirement as given by eqn. 6, making the circuit using an analog multiplexer.
239
 I-,
\
50

I- 50~ . . . . . . 'D:. . . . .

.io0 - .................... ~ ~.

F,#q"S"CjpZ)

(a) Magnitude Plot (a) hlagnitude Plot

-20 10 rm "0 incm ..i+ :m iom . . . . . 101x0

-40.. . . :. . . . . ....
-60-
P 80- . . . .........
t.lOO............. ~ ............... ..:.
'B - 1 2 0 . . . . . . . . . . !
..
-160 . . .

-200 ........... .. .....

FroquenqlHz)

(b) Phase Plot (b) Phase Plot

Fig.4. Bode Plot of System with Faster Controller

Fig. 3. Bade Plot of System with Slower Controller

RESULTS
V. S I M U L A T I O N
The controllers designed where implement in the control
scheme. The simulation study was carried out to see the effec-
tiveness of the proposed control scheme. A 50% load change
(decrease in load) is applied at 400111s and its effect was ob-
served using both the control scheme. The simulation results
for the 50% load change using conventional and proposed con-
trol scheme is shown in Fig. 5 and Fig. 6 respectively. The
load change was applied at 400ms. In case of proposed control
scheme, Cont-I is removed and Cont-I1 is put in control loop at
401ms. The Cont-I is again brought in control loop at.417ms
(i.e near zero input voltage). From the simulation results it can
be clearly seen that proposed control scheme improves the per-
formance of the system. All the simulations are performed in
Orcad PSpice.
VI. EXPERIMENTAL
RESULTS
A hardware prototype for testing the functionality of pro-
posed control scheme is shown in Fig 7. The design specifi-
cation of the prototype are given in Table. I.
Prototype shown in Fig. 7 includes the scheme for switching
the control from Cont-I1 to Cont-I at input voltage zero. This
is more important because the Cont-I is slower controller with
less phase margin, and if the Cont-I is not put in circuit at volt-
age zero it may sense it as transients as explained earlier. So
switching the controller from Cont-I1 to Cont-I at input voltage
zero makes the circuit more stable.
240
Fig 8 shows the input linl: current (i,(t)) and input line volt-
age (V,) waveforms. It can be seen that input current (i.(t))
is sinusoidal and in phase with the input voltage (V8).Fig. 9
and Fig. 10 shows the restilts for load change from 0.5 A dc
to 1.5 A dc and vice versa respectively. In Fig. 9 and Fig. 10,
waveform 1 is rectified input voltage (V?),waveform 2 is in-
put supply current (a*(t)),waveform 3 is controller change sig-
nal and waveform 4 is DC voltage ripple (Vdcrip). From the
Fig. 9 and Fig. 10, it can be seen that the high bandwidth
controller responds faster to the disturbance, so as to reduce
the transient duration. The transient duration lasts for approxi-
mately 5 power cycles. Waveform 3 in Fig. 9 and Fig. 10 shows
the controller change signal. When the controller change signal
is high, voltage controller Cont-I1 is in circuit and when its low,
voltage controller Con1 - I is in control loop. Fig. 11 shows
the controller change signal (waveform 4) and output of Mux
(waveform 3) which is nothing but the Voltage Controller out-
put (Cont-I or Con[-11). It can be seen from the Fig. 11 that the
Cont-I1 compensates for the 120Hz ripple, which is according
to design. The performance obtained using hardware prototype
is detailed in Table. 111, which are all within the design specifi-
cation.
The capacitor value has reduced from 1OOOpF to 680pF by
implementing change of Cont-I1 to Cont-I at input voltage zero
crossing. Power, PF, Current THD and voltage THD measure-
ment was done using Power Analyzer.
 -1 I

(a) Output Voltage Waveform

(a) Output Voltagc Waveform

(b) Rectified Voltage and Culrent Waveform

(b) Rectified Voltage and Current Waveform

Fig. 6. Simulation Results with Proposed Voltage Controller

Fig.5 . Simulation Results with Conventional Voltage Controller

No. Parameters Load Con- Load Con-

dition 1 dition 2
1 Output Power Po 318.7W 115w
2 InputPF 0.998 0.997
3 Input Current THD 3.5 - 3.8 % 3.6 - 3.9 %
4 Input Voltage THD 2.2 - 2.5 % 2.4 - 2.7 %

VII. CONCLUSION Fig.7. Hardware Prototype

The proposed dual voltage controller is effective in improv-

ing the overall response during the disturbances. The faster re-
sponse of the controller during disturbances results in a smaller
value of dc-bus capacitor. The slower voltage controller main-
tains the THD within limits during the steady state. Both con-
trollers maintain the output voltage at its reference value. This
proposed scheme results in compact and light-weight power
factor correction circuits using boost topology.
241
VIII. FUTURE
SCOPE
The complete control scheme can be implemented digitally.
An FPGA or a fast DSP chip can be used to implement the
complete control scheme. This could lead to a further compact
circuit as complete control scheme could be implemented in a
 ..

Fig. 8. Hardware Results of Input Voltage and Input Current Waveform Fig. I I . Hardware Result of Output signal of MUX and Controller

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I I I I * I I

Fig. IO. Hardware Result of Step Decrease in Load

single chip.

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242