Design For Test

Preface
Read This First
About This Manual

This Design for Testability Reference Guide provides information on developing test strategies for ASIC designs. The following list summarizes the chapters of this ASIC document.
How to Use This Manual

The chapter highlights are presented in the following text. Chapter 1 Introduction to Design for Testability Introduces the subjects of designing for testability in the beginning of the design process, fault simulation, and dc parametric testing Chapter 2 Reasons for Using Design for Testability Discusses the time and money savings achieved by using and integrating design for testability (DFT) early in your design process. Discusses fault grading and fault coverage. Chapter 3 Developing a Testability Strategy Presents strategies for developing testability techniques Chapter 4 Test Pattern Requirements Presents the required and optional TDL pattern types Chapter 5 Ad Hoc Testability Practices Recommends some work-arounds and techniques that are useful for improving your testability
iii
How to Use This Manual
Chapter 6
Structured Testability Practices Discusses the different types of scan design testing
Chapter 7
IEEE Standard 1149.1-1990 Provides an overview of the IEEE Std 1149.1 and gives an overview of the boundary-scan architecture
Chapter 8
Generic Test Access Port Discusses the generic test access port (GTAP), which is used to enable and disable various DFT features
Chapter 9
Parallel Module Test Presents information on parallel module test (PMT), how to use PMT with MegaModules, such as how to test buses and hook up test buses to device pins
Chapter 10
Parametric Measurements Discusses using parametric testing to guarantee conformance to electrical data sheets and presents information on the use of boundary-scan, pattern sets, and TDL types
Chapter 11
Automatic Test Pattern Generation Presents automatic test pattern generation (ATPG) methodologies, such as path sensitization and full and partial scan
Chapter 12
Test Pattern Generation Discusses generating test patterns for use by automated test equipment (ATE)
Chapter 13
IEEE Standard 1149.1-Based dc Parametric Testing Discusses what is required in performing IEEE Standard 1149.1-based dc parametric testing
Chapter 14
Military ASIC Summarizes military ASIC documents and the location of military-specic design information
Appendix A
Glossary Contains important ASIC words, phrases, and software tools
iv
Design for Testability
Notational Conventions
Notational Conventions
This document uses the following conventions. t Program listings, program examples, and interactive displays are shown in a special typeface (called courier) similar to a typewriters. Examples use a bold version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3
Here is an example of a system prompt and a command that you might enter:
C: csr -a /user/ti/simuboard/utilities
In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of a directive syntax: .asect
section name, address
.asect is the directive. This directive has two parameters, indicated by section name and address. When you use .asect, the rst parameter must be an actual section name; the second parameter must be an address. t Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify the information within the brackets; you do not enter the brackets themselves. Heres an example of an instruction that has an optional parameter: LALK
16-bit constant [, shift]
The LALK instruction has two parameters. The rst parameter, 16-bit constant, is required. The second parameter, shift, is optional. As this syntax shows, if you use the optional second parameter, you must precede it with a comma.
Information About Cautions and Warnings
Braces ( { and } ) indicate a list. The symbol | (read as or ) separates items within the list. Heres an example of a list: { * | *+ | *- } This provides three choices: *, *+, or *-. Unless the list is enclosed in square brackets, you must choose one item from the list.
Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this directive is: .byte value1 [, ... , valuen] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas.
Information About Cautions and Warnings

This book may contain cautions and warnings.
This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
vi
Related Documentation From Texas Instruments

The following list describes related documents of interest to the Submicron ASIC Products Design for Testability Reference Guide (DFT) and includes corresponding literature numbers. The ASIC TDL 91 Reference, which discusses ASIC TDL 91 version 5.0. The TI Web-based ASIC TDL 91 Reference provides details about a particular tools capabilities. For more information on the Web, contact your TI Customer Design Center representative. The ASIC TDL 91 and Scan Designs Reference, which provides informative application examples on ASIC TDL 91 and scan designs. Refer to the TI web-based ASIC TDL 91 and Scan Designs Reference. The Submicron ASIC Products Design for Testability Application Reports, which provide information on designing with a generic test access port (GTAP) (refer to the Web-based Generic Test Access Port Application Report), on the RAM Built-In Self-Test (refer to the Web-based RAM Built-In Self-Test (BIST) Application Report), and on the multiplexed parallel module test (refer to the Web-based Multiplexed Parallel Module Test Application Report). The Submicron ASIC Products Design Software Manual (DSM): TIDSS Design Flow, which describes the Texas Instruments (TI) Design Support Software (TIDSS), Release 5 series design ow. The Web-based TIDSS Tools Reference gives details about the specic capabilities and features of each TIDSS tool. The Web-based TIDSS Tools Reference, which covers the TIDSS tools in depth and supports releases in the TIDSS series. This manual (TIDSS Design Flow) will often refer you to the TI Web-based TIDSS Tools Reference for details about a particular tools capabilities. For more information on the Web, contact your TI Customer Design Center representative. The Cadence Design Planner Users Guide, which explains how to use the Cadence Design Planner oorplanner in the TI Flow. The Submicron ASIC Products Test Synthesis Users Guide (literature number SRGU002B), which describes the Synopsys Test Compiler, a test tool combining design-for-testability synthesis with automatic test pattern generation. The TGC6000/TEC6000 Web-based Design Rules describes design rules in the ow and provide up-to-date information enabling effective use of tool-specic design rules and the resolution of errors and warnings encountered during the design process.
vii
Submicron ASIC Products Design Software Manual: TIDSS 5.0 Design Flow (literature number SRGU009) takes you through all the design steps needed to hand off a complete and veried design database to Texas Instruments. Submicron ASIC Products Design Software Manual: TIDSS Tools addresses the specics of each TI software tool that you use in designing your submicron application-specic integrated circuit (ASIC). Available on the Web. Contact your TI Customer Design Center. Submicron ASIC Products Design for Testability Reference Guide (literature number SRUU002F) offers guidelines for developing a coherent approach to integrating testability in the design ow. TGC6000/TEC6000 0.18-m CMOS Arrays Macro Library Summary (literature number SRGD005) provides accurate electrical and timing specications for each macro included in the TI TGC6000/TEC6000 family software logic library. TGC6000/TEC6000 Series 0.18-m CMOS Gate Arrays Family Data Sheet (literature number SRGS025A) summarizes electrical, timing, and packaging information for the macros included in the TI TGC6000/TEC60000 Series software logic library, release 1.0. TGC6000/TEC6000 Series 0.18-m CMOS Gate Arrays Library Release 1.0 Release Notes (literature number SRGA027) describes the TGC6000/TEC6000 library release 1.0 for HP and Sun platforms. The library can be distributed on tape, either separately or in conjunction with other library releases and/or releases of Texas Instruments Design Support Software (TIDSS) release 5.0. Submicron ASIC Products TIDSS Release 5.0 Release Notes (literature number SRUA021) describes the Texas Instruments Design Support Software (TIDSS) release 5.0. Submicron ASIC Products Design Kit Installation Notes (literature number SRUU018) contains detailed instructions for installing the TGC6000/ TEC6000 library (and TIDSS, if applicable). Submicron ASIC Products Cadence Design Planner Users Guide (literature number SRSU009) describes the various aspects of the Design Planner oorplanning tool.
viii
If You Need Assistance
If You Need Assistance

If you need assistance or to access information on the Internet/Intranet, contact your local TI Customer Design Center representative.
Trademarks
Advantest is a trademark of Advantest Corporation. ACE, DETECTOR, GOOD, MegaModule, and TI are trademarks of Texas Instruments Incorporated Analyzer, Cadence, Design Planner, Gate Ensemble, LeapFrog, QPlace, SDF, Verilog, Verilog HDL, and Verilog-XL, are trademarks of Cadence Design Systems, Inc. DFTAdvisor, FlexTest, FastScan, Mentor Graphics, and QuickSim II are trademarks of Mentor Graphics Corporation Behavioral Compiler, DC Expert, DC Professional, DesignPower, dont_touch, Power Compiler, Primetime, Synopsys, Synopsys VHDL Compiler, Test Compiler, Test Compiler Plus, VSS, VSS Expert, and VSS Professional are trademarks of Synopsys, Inc. Gemini, IKOS, NSIM, Voyager, and Voyager-FS are trademarks of IKOS Systems, Inc. HP, HP 700, HP 9000, and HP-UX are trademarks of Hewlett-Packard Company IBM is a trademark of International Business Machines Corporation SPARC, SPARC 20, SPARCstations, and UltraSPARC are trademarks of SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc. Solaris, Sun Sun-5, SunOS, and Sun Workstation are trademarks of Sun Microsystems, Inc. Quad Design, and Sunrise are trademarks of Viewlogic Systems, Incorporated, a subsidiary of Synopsys, Inc. Vitesse is a trademark of Vitesse Semiconductor Corporation EMIS is a trademark of Synercom Technology, Inc.
ix
Trademarks
ICRAMBIST and LogicVision are trademarks of LV Software, Inc. Kevlar and Teon are trademarks of E.I. DuPont de Nemours & Company MQUAD is a trademark of OIin Corporation Super-Compact is a trademark of Compact Software, Inc. Design VERIFYer is a trademark of Chrysalis Symbolic Design, Inc. Epilog is a trademark of Nextwave Design Automation, Inc. System Realizer is a trademark of Quickturn Design Systems, Inc.
Contents
1 2
Introduction to Design for Testability
1-1
Reasons for Using Design for Testability -1 The Need for Testability ...................................................................................................-2 Test-Time Cost ................................................................................................................-2 Time-to-Market ................................................................................................................-3 Fault Coverage and Cost of Ownership...........................................................................-5 Developing a Testability Strategy 3-1 Selecting a Technology..................................................................................................3-2 Committing to Testability Design Practices....................................................................3-3 Establishing a Fault-Grade Requirement.......................................................................3-4 Will IEEE Standard 1149.1 Be a System Requirement? ...............................................3-5 Selecting a Testability Approach Based on Gate Density..............................................3-6 Choosing Structured Tools ............................................................................................3-7 Establishing a Diagnostic Pattern Set to Expedite Debug .............................................3-9 Generating High-Fault-Grade Test Patterns ................................................................3-10 Simulating Test Patterns and Timing ...........................................................................3-11 Converting Test Patterns to TDL .................................................................................3-12 Planning for Test Pattern/Logic Revision Compatibility ...............................................3-13 Test Pattern Requirements 4-1 Responsibilities..............................................................................................................4-2 TDL Type Descriptions ..................................................................................................4-3 Ad Hoc Testability Practices 5-1 Logic Design With Testability in Mind ............................................................................5-2 Improving Testability Via Unused Pins ..........................................................................5-3 Using Bidirectional Pins.................................................................................................5-4 Initializing the Circuit to a Known State .........................................................................5-5
xi
Contents
Avoiding Asynchronous Circuitry ...................................................................................5-7 Avoiding Gated Clocks ..................................................................................................5-8 Allowing Internal Clocks to Be Bypassed From Circuits Inputs.....................................5-9 Allowing Counters and Dividers to Be Bypassed ........................................................5-10 Splitting Long Counter Paths .......................................................................................5-11 Multiplexing to Provide Direct Access to Logic ............................................................5-12 Breaking Feedback Paths in Nested Sequential Circuits.............................................5-14 Allowing Redundant Circuitry to Be Tested .................................................................5-15 Watching for Signals That Reconverge .......................................................................5-16 Decoupling Linked Logic Blocks ..................................................................................5-17 Johnson Counter Test Signal Generator .....................................................................5-18 Shift Register Test Signal Generator ...........................................................................5-19 Shift Register Used to Obtain Observability ................................................................5-20 6 Structured Testability Practices 6-1 Structured Approaches to Designing for Testability.......................................................6-2 Clocked Scan Flip-Flop Design .....................................................................................6-3 Multiplexed Flip-Flop Scan Design ................................................................................6-5 Clock Skew and Edge-Triggered Flip-Flop Scan ...........................................................6-7 Clocked LSSD Scan Flip-Flop Design ...........................................................................6-8 Guidelines for Flip-Flop Scan Design ..........................................................................6-10 Scan Path Loading on Critical ac Path ........................................................................6-11 Bus Contention and Scan Testing ...............................................................................6-12 Test-Isolation Modules.................................................................................................6-14 Where Scan Is Not Efcient.........................................................................................6-20 IEEE Standard 1149.1-1990 7-1 Overview........................................................................................................................7-2 Boundary-Scan Architecture .........................................................................................7-3 Generic Test Access Port 8-1 Overview........................................................................................................................8-2 Test Register..................................................................................................................8-3 Test RegisterBit Denitions .......................................................................................8-5 Controller .......................................................................................................................8-7 Communication Protocol ...............................................................................................8-8 Parallel Module Test 9-1
Contents
xii
Contents
Parallel Module Test of MegaModules...........................................................................9-2 MegaModule Test Collar................................................................................................9-4 Single MegaModule PMT I/O Hookup ...........................................................................9-5 PMT Test Bus ................................................................................................................9-6 Multiple MegaModule PMT I/O Hookup.........................................................................9-7 PMT for Analog MegaModules ......................................................................................9-9 In-System Use .............................................................................................................9-21 10 Parametric Measurements 10-1 Overview......................................................................................................................10-2 Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type) ....10-4 Output Voltage Levels (DC_PARA TDL Type) ...........................................................10-10 Three-State High-Impedance Measurements (DC_PARA TDL Type) .......................10-11 Input Current Measurements (DC_PARA TDL Type) ................................................10-12 Quiescent Drain Supply Current (IDDQ TDL Type) ...................................................10-13 Automatic Test Pattern Generation 11-1 Introduction to Automatic Test Pattern Generation ......................................................11-2 Path Sensitization ........................................................................................................11-5 Full-Scan Designs .......................................................................................................11-6 Partial-Scan Designs ...................................................................................................11-7 Testing and Debugging Considerations .......................................................................11-8 Common ATPG Constraints ........................................................................................11-9 Summary ...................................................................................................................11-10 Test Pattern Generation 12-1 Introduction to Testing .................................................................................................12-2 Test Pattern Creation...................................................................................................12-6 TDL Overview............................................................................................................12-13 IEEE Standard 1149.1-Based dc Parametric Testing 13-1 Introduction..................................................................................................................13-2 Boundary-Scan Architecture .......................................................................................13-3 Parametric Measurements Using Boundary-Scan Architecture ................................13-10 Integrating Boundary-Scan Architecture and GTAP ..................................................13-18 Military ASIC 14-1 Military-Specic Design Information ............................................................................14-2 Military ASIC Topics Cross-Reference ........................................................................14-3
11
12
13
14
Contents
xiii
Contents
Glossary Index
1 Index-1
xiv
Figures
21 22 23 24 25 26 31 51 52 53 54 55 56 57 58 59 510 511 512 513 514 515 516 517 518 519 520 521
Fault Grade Versus Development Time ............................................................................-3 Economic Trade-Off for a Testable Design .......................................................................-4 Defect Level Versus Fault Coverage .................................................................................-6 Motorola/Delco Study Results ...........................................................................................-7 ASIC ppm Versus PCB ppm Rate .....................................................................................-8 Cost of Ownership .............................................................................................................-9 Testability Development Flow........................................................................................3-14 Observing an Internal Node.............................................................................................5-3 Test Signal Injection ........................................................................................................5-3 Bidirectional Pins Giving Access to Internal Nodes .........................................................5-4 Uncontrollable State Machine..........................................................................................5-5 Using Clear to Add Controllability ....................................................................................5-6 Add Clock to Asynchronous Latch...................................................................................5-7 Gated Clock and Alternative ............................................................................................5-8 Bypass Internal Clock Generators ...................................................................................5-9 Bypass Counters and Dividers ......................................................................................5-10 Long Counter Path Divided for Testing..........................................................................5-11 Multiplexing an Output Pin to Improve Observability .....................................................5-12 Multiplexing an Input Pin to Improve Controllability .......................................................5-12 Multiplexing Both Inputs and Outputs to Improve Testability.........................................5-13 Example of Unobservable Flip-Flop Outputs .................................................................5-13 Flip-Flop Outputs Made Observable With a Multiplexer ................................................5-13 Nesting of Sequential Circuits........................................................................................5-14 Redundant Circuitry .......................................................................................................5-15 Reconverging Signals....................................................................................................5-16 Decouple Circuit Blocks.................................................................................................5-17 Johnson Counter to Minimize Test Pins ........................................................................5-18 Test Signal Generator Using a Shift Register................................................................5-19
xv
Figures
522 61 62 63 64 65 66 67 68 69 610 611 612 613 614 615 71 72 73 81 82 83 84 91 92 93 94 95 96 97 98 99 910 911 912 913 101
Shift Register Adding Observability to Buried Nodes ....................................................5-20 Clocked Scan Flip-Flop....................................................................................................6-3 Clocked Scan Flip-Flop Circuit Interconnect....................................................................6-4 Multiplexed Scan Flip-Flop ..............................................................................................6-5 Multiplexed Flip-Flop Scan Path ......................................................................................6-5 Clocked LSSD Scan Flip-Flop ........................................................................................6-8 Clocked LSSD Scan Flip-Flop Circuit Interconnect ........................................................6-9 Isolate Scan Path Loading.............................................................................................6-11 Bus Contention Hazard..................................................................................................6-12 Scan 3-State Disabling Logic.........................................................................................6-13 Partition Into Test-Isolation Blocks ................................................................................6-14 Multiple Clocked Scan Flip-Flop Scan Paths.................................................................6-16 Multiple Multiplexed Flip-Flop Scan Paths.....................................................................6-17 Multiple Clocked LSSD Scan Paths...............................................................................6-18 Scan Vectors for Multiple Scan Blocks ..........................................................................6-19 Scan Path Around a Function........................................................................................6-20 Boundary-Scan Architecture............................................................................................7-4 General-Purpose Boundary-Scan Macro.........................................................................7-6 Boundary-Scannable PCB...............................................................................................7-7 GTAP Block Diagram.......................................................................................................8-2 TP000 (Test Register Building Block)..............................................................................8-3 Typical Test-Register Architecture...................................................................................8-4 GTAP-Controller State Transition Diagram .....................................................................8-9 GTAP-Controlled PMT Block Diagram ............................................................................9-3 MegaModule With a Test Collar ......................................................................................9-4 Single MegaModule PMT ................................................................................................9-5 PMT Test Bus Hookup.....................................................................................................9-8 PMT for a Single Analog-to-Digital Converter................................................................9-10 PMT for a Single Video Band Analog-to-Digital Converter ............................................9-11 PMT for Multiple Analog-to-Digital Converters ..............................................................9-13 PMT for Multiple Video Band Analog-to-Digital Converters...........................................9-14 PMT for a Single Video Band Digital-to-Analog Converter ............................................9-16 PMT for Multiple Digital-to-Analog Converters ..............................................................9-17 PMT for Multiple Video Band Digital-to-Analog Converters...........................................9-18 PMT for a Single Differential Amplifier...........................................................................9-19 PMT for Multiple Differential Amplifiers..........................................................................9-20 Clocked NAND Tree Circuit (Dedicated Control Pins)...................................................10-5
Contents
xvi
Figures
102 103 111 112 121 122 123 124 125 126 127 128 129 1210 131 132 133 134 135 136 137 138 139 1310
CMOS ASIC NAND Tree Configurations.......................................................................10-7 Clocked NAND Tree Circuit (Shared Control Pins) .......................................................10-8 Typical Design Flow.......................................................................................................11-3 Typical ATPG Flow ........................................................................................................11-4 Synchronous Pattern for Use During Functional Test ...................................................12-3 ATE Block Diagram .......................................................................................................12-4 Tester Period Slip ..........................................................................................................12-5 Input Delay Groups........................................................................................................12-7 Definition of TDL Clocks ................................................................................................12-8 Minimum Clock Width ....................................................................................................12-9 TDL Output Strobe Placement.....................................................................................12-10 Simulation Tester Loads ..............................................................................................12-11 Waveform Representation of the Sample TDL ............................................................12-15 Relationship Between Test Vectors and Corresponding Logic Waveforms ................12-17 IEEE Standard 1149.1 Hardware Block Diagram ..........................................................13-3 A Simplified View of the Boundary-Scan Register.........................................................13-4 Boundary-Scan Cell.......................................................................................................13-5 TAP Controller State Diagram .......................................................................................13-7 Boundary-Scan Registers and GTAP Test Register Hardware ...................................13-19 GTAP Test Register Architecture ................................................................................13-20 Test Register Load Timing Diagram ............................................................................13-21 TCK-to-Master/Slave Clock Interface Circuit ...............................................................13-21 TDO Input Circuit for Test Activation ...........................................................................13-22 Example TST_ENBL Circuit ........................................................................................13-22
Contents
xvii
Tables
Table
41 81 82 101 102 103 121 131 141
Page
TDL Pattern Set Requirements Summary ................................................................. 4-5 Example Test-Register TP000 Assignments ............................................................. 8-5 Example Test-Register Test-Selection Codes............................................................ 8-6 Toggle States ........................................................................................................... 10-3 VIL/VIH Test Patterns (Dedicated Control Pins) ...................................................... 10-6 VIH_VIL Test Patterns (Shared Control Pins).......................................................... 10-9 Commonly Used TDL Logic State Characters......................................................... 12-15 Parametric Test Resources ................................................................................... 13-10 Military ASIC Topics Cross-Reference ................................................................... 14-4
xviii
Chapter 1
Introduction to Design for Testability
Testability is the concern most often voiced by Texas Instruments (TI) application specic integrated circuit (ASIC) users. This document is intended to consolidate TI policies into a coherent approach to designing for testability. It is not intended as a specication, but as a guide you can use for developing test strategies when designs are being initiated. Adoption of design-for-testability principles early in the design process ensures the maximum testability for the minimum effort. These guidelines emphasize that test is a part of the design ow, not a process that is performed at the end of the design cycle. Designing testability into any circuit affects the hardware to some degree. Additional logic usually must be added. This additional logic increases the amount of silicon required to implement the design. The savings from enhanced testability do not typically show up until the cycle time and cost of testing a circuit and its end system are analyzed. Fault simulation is an important part of designing for testability. This technique enables you to evaluate your test patterns to determine whether these patterns can detect faults. Faults can occur during either the design tooling stage or the circuit fabrication stage. A fault simulator uses fault models, such as a node shorted to power (stuck-at-one) or a node shorted to ground (stuckat-zero), and compares the response of a fault-free circuit with the response of a faulty circuit. If the response of the fault-free circuit is different than the response of the faulty circuit, the test patterns detect the fault.
1-1
By faulting all the nodes in the circuit, the fault simulator produces the test pattern fault coverage. The fault coverage is the percentage of faults detected among the total faults tested. The higher the fault coverage, the better the test pattern separates a faulty circuit from a fault-free circuit. After determining which faults have not been detected by the current set of test patterns, you can generate additional test patterns to detect these faults. The higher the fault coverage of the pattern set (often called fault grade), the greater the probability of obtaining only fault-free circuits. The dc parametric testing ensures that a fault-free circuit conforms to the electrical data sheet. The pattern set for dc parametric testing should provide one hundred percent toggle of all I/Os. The IDDQ (quiescent drain supply current) testing ensures a circuit is free from defects such as resistive bridging or partial gate punch through. Stuck-at-1 or stuck-at-0 often cannot detect defects of these types.
1-2
Chapter 2
Reasons for Using Design for Testability
This chapter explains how design-for-testability principles ultimately save money and time when an ASIC design is created and manufactured.
Topic
Page
The Need for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Test-Time Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Time-to-Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fault Coverage and Cost of Ownership . . . . . . . . . . . . . . . . . . . . 25
2-1
The Need for Testability
2.1
The Need for Testability

Most engineers involved in the design of ASIC devices are familiar with the trade-offs between gate arrays, standard cells, and full custom devices. They are also familiar with the vendor selection process. The aspect of test capability and testability is often overlooked. In the past, testability could be ignored when typical designs were a few thousand gates. These designs were implemented rst and then turned over to a test engineer or to a vendor to force a test program for production. As design complexities increased, this approach to testing became futile. Now, successful high-density ASIC design and manufacturing demand that circuits be designed with testability incorporated into the process. A designer often sees testability as having only a negative impact on performance and area. Although testability imposes additional constraints in the design phase, these constraints are unmanageable only if ignored until the design is completed and testability is handled as a post-design insertion. In fact, the design constraints are overwhelmingly balanced by improved testability, which adds value to the device throughout manufacturing and system life.
2.2
Test-Time Cost
Test cost, as it relates to time, is a simple calculation. Most commercial testers cost between $2 million and $3 million. Under normal circumstances, the tester depreciation, plant, operator, and support personnel costs are between $.10 and $.20 per test second. Brute-force test approaches often generate a large number of test patterns. Because test patterns are run at multiple power supply values and possibly at multiple temperatures, inefcient pattern sets can severely impact the test costs of a complex ASIC device.
2-2
Time-to-Market
2.3
Time-to-Market
Surveys indicate that 40 percent of the development cycle time for an ASIC device is required for test insertion and test pattern generation. This gure is expected to increase as device complexity increases. The intent of a designfor-testability (DFT) strategy is to achieve high-fault-detection test programs in reduced time (Figure 21). The obvious cycle-time reductions result from designed-in testability (elimination of iterative redesigns resulting from poor design practices), and from automatic test pattern generation (ATPG).
Figure 21.
Fault Grade Versus Development Time

100 With DFT Strategies 80
Fault Grade %
60 Without DFT Strategies 40
20
0 Hours Days Weeks Months
Time to Develop Test Patterns
Figure 22 shows the economic relationship between time-to-market and system manufacturing and eld maintenance costs. Point 1 represents the case where market entry timing forces a constraint on the development time. Because 40 percent of this time is expended in inserting testability, the temptation is to rush to market with devices that are not completely testable or tested. The result is higher than desirable manufacturing and eld maintenance cost. Point 2 represents the case where DFT and ATPG techniques are employed to develop devices that are completely tested. This situation allows an economic optimum that is more favorable to long-term manufacturing and eld-maintenance costs.
2-3
Time-to-Market
Figure 22.
Economic Trade-Off for a Testable Design
}
Economic Optimum 1 Cost $ Economic Optimum 2
Without DFT Strategy
With DFT Strategy
Manufacturing and Field Cost Fault Coverage % Development and Time-to-Market Cost
Total Cost
A less obvious result of a DFT strategy is the reduction of debug time. You, as an ASIC designer, must make certain assumptions about system requirements. Often a new device does not work in the system environment and requires debugging. If the device is designed for controllability and observability access, the debugging process is enhanced. Conversely, if these two features are overlooked, debugging and manufacturing can be signicantly harder to accomplish, if not impossible. Oscilloscopes and waveform analyzers are not very effective in debugging systems using complex ASIC devices in a surface-mount environment.
2-4
Fault Coverage and Cost of Ownership
2.4

Figure 22 on page 24 shows the trade-off between time-to-market and manufacturing and eld-maintenance costs. The horizontal factor on this gure is fault coverage. The relationship between fault coverage and devicedefect level is well documented. Figure 23 is a plot of the relationship modelled by T.W. Williams1 for fault coverages of 90 percent or greater. The model developed by Williams is expressed by the following equation:
D = [1 Y
where:
(1 T)
] 100
D = Defect level in percent Y = Theoretical functional process yield T = Fault coverage of the test program used
1. T. W. Williams and N. C. Brown, Defect Level as a Function of Fault Coverage, IEEE Transactions on Computers, C-30(12), December 1981, pp. 987-988.
2-5
Figure 23.
Defect Level Versus Fault Coverage

7 50% 6 5 Defect Level % 4 70% 3 80% 2 90% 1 0 90 50% Process YLD 60% Process YLD 70% Process YLD 80% Process YLD 90% Process YLD 6.7 3.5 91 92 93 94 95 96 97 98 99 100 60%
6.04 5.39 4.74 4.07 3.51 3.02 3.16 2.81 2.47 2.12
3.41 2.73 2.52 2.02 1.77 1.42 0.53 0.42
2.08 1.38 1.52 1.01 1.06 0.71 0.67 0.45
0.89 0 0.51 0 0.36 0 0.22 0
4.98 4.48 4
2.21 1.99 1.77 1.55 1.33 1.11 0.89 1.05 0.94 0.84 0.73 0.63
0.32 0.21 0.11 0
Fault Coverage %
To explore the Williams model briey, assume that the ASIC vendor has a silicon and assembly process yield that is 70 percent. If the fault grade of the test program is also 70 percent, the defect level is projected to be 10.1 percent or 101000 ppm (parts per million) (This is outside the limits of the chart and was calculated.). At a fault grade of 90 percent, the defect level is projected to be 3.5 percent, or 35000 ppm. A study of the model shows that the process yield becomes an insignicant term when the fault coverage of the test program is very close to 100 percent. Motorola and Delco2 performed a study in 1980 that supports the Williams model. Their experimental results are shown in Figure 0-4. A fault coverage of 99.9 percent was required to obtain defect levels in the range of 100 ppm.
2. Harrison, Holzworth, Motz of Delco and Daniels Thomas, Weimann of Motorola, September 1980.
2-6
Figure 24.
Motorola/Delco Study Results
100000 10000 Defect Level ppm
1000
100
10 90 99 Fault Coverage % 99.9
Figure 25 shows the maximum allowable ASIC defect rate to achieve a goal PCB (printed circuit board) defect rate as a function of the number of ASIC devices per board assembly. Note that for multiple-device PCB designs, a goal of 500 ppm requires ASIC defect levels in the range of 100 to 200 ppm.
2-7
Figure 25.
ASIC ppm Versus PCB ppm Rate

600 500 Number of ASICs Per Board 1
ASIC ppm Rate
400 300 2 200 100 0 0 3 4 5 10 20 100 200 300 400 500 600
Goal PCB ppm Rate
The theoretical and experimental studies conclude that a high-fault-grade test pattern set is required for low-defect-level ASIC devices. This type of pattern set is nearly impossible to obtain through manual brute-force means. The requirements for a high-fault-grade pattern set are: t t t ATPG tool Fault grader A testable design that meets the constraints of the ATPG tool
As stated earlier in this document, a design-for-testability strategy has performance and area costs. Now the cost of new tools has been added. Benets such as lower test costs and reduced time-to-market have been mentioned. These benets are real but often hard to quantify. Reduced cost of ownership is another major benet and is easy to quantify. Figure 26 shows what is commonly referred to as the cost-of-ownership order-of-magnitude relationship. It says that each company has a cost associated with nding a defect in a packaged device before it has entered the assembly process. This cost can be calculated easily. The cost of nding a defective device after assembly onto a PCB is an order of magnitude more than it is before assembly. This continues until the cost to discover a defective device in a system at a customers site is three orders of magnitude greater
2-8
than that of discovery before assembly onto a PCB. The lowest cost of ownership is to nd defective units before they are shipped from the vendor.
Figure 26.
Cost of Ownership
Customer Site
System Discovery Site 0
PCB
Package Device
1X
10X
100X
1000X
Cost of Defect Discovery Multiplier
The previous discussions have lead to the conclusion that the lowest cost of ownership can be obtained by providing the ASIC vendor with an efcient high-fault-detection set of test vectors. These DFT methodologies provide lower cost of ownership with the added benet of reducing the time-to-market.
2-9
2-10
Chapter 3
Developing a Testability Strategy
You should now be aware of the benets of having a testable circuit and have a general awareness of testability techniques. This chapter presents a methodology for developing a testability strategy for your circuits. The process involves making decisions based upon your application. The following strategies, listed by section, step you through the process of testability.
Topic
Page
Selecting a Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Committing to Testability Design Practices . . . . . . . . . . . . . . . . . 33 Establishing a Fault-Grade Requirement . . . . . . . . . . . . . . . . . . . 34 Will IEEE Standard 1149.1 Be a System Requirement? . . . . . . . 35 Selecting a Testability Approach Based on Gate Density . . . . . . 36 Choosing Structured Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Establishing a Diagnostic Pattern Set to Expedite Debug . . . . . 39 Generating High-Fault-Grade Test Patterns . . . . . . . . . . . . . . . . . 310 Simulating Test Patterns and Timing . . . . . . . . . . . . . . . . . . . . . . 311 Converting Test Patterns to TDL . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Planning for Test Pattern/Logic Revision Compatibility . . . . . . . 313
3-1
Selecting a Technology
3.1
Selecting a Technology
When selecting a technology or vendor, make sure there is enough performance and gate-count margin to allow the insertion of testability. Make an early recognition that you need a 10 percent ac margin and a 10 percent to 15 percent gate-count margin. An optimized testability library to support techniques such as parallel module test (PMT), scan, and IEEE Standard 1149.1-1990, IEEE Standard Test Access Port (TAP) and Boundary-Scan Architecture (JTAG) can reduce the impact of inserting testability features. Chapter 7, IEEE Standard 1149.1-1990, describes the standard. Failure to allow for technology margins puts you in a continual state of compromise. The result can be a circuit with a low purchase price that has a high cost of ownership through manufacturing because it is untestable.
3-2
Committing to Testability Design Practices
3.2
Committing to Testability Design Practices

Follow the guidelines listed here to ensure sound testability practices: t t Commit to using the testability design practices presented here. Review the testability design practices with the design team before beginning the design. Add a testability commitment to the design requirements documents. Make testability audits part of the design review process.
t t
3-3
Establishing a Fault-Grade Requirement
3.3
Establishing a Fault-Grade Requirement

The fault-grade requirement can usually be provided by the manufacturing or quality organization. Establish this requirement before the rst design review. Add the fault-grade requirement to the design requirements document. This requirement drives many of the decisions that follow in the development of the test strategy. Many companies consider the fault-grade requirement to be an index of device cost of ownership. Failure to achieve it costs prots throughout the lifetime of the device. Therefore, a waiver of the fault-grade requirement should be formal and require management approval.
3-4
Will IEEE Standard 1149.1 Be a System Requirement?
3.4
Will IEEE Standard 1149.1 Be a System Requirement?

When implemented in an ASIC device, IEEE Standard 1149.1 allows measurement of the interconnect between devices on a PCB through a fourpin bus. If IEEE Standard 1149.1 is selected, the four dedicated test pins can be used to control test techniques such as parallel module test and scan. Remember IEEE Standard 1149.1 is not a device test methodology. If there is a design requirement to simplify PCB testing, you should use all the resources available in the instruction register to control testing circuits.
3-5
Selecting a Testability Approach Based on Gate Density
3.5
Selecting a Testability Approach Based on Gate Density

The following strategies can be used to select a testability approach based on gate density. t Designs with fewer than 10K gates Designs with fewer than 10K gates are not generally complex enough to require structured test approaches. The overhead impact is usually too high to justify them. Nonstructured design practices are usually sufcient. Parallel module test should be used to test embedded memories. Structured techniques, such as scan, can reduce test program generation time and allow high fault grades. These benets make scan desirable even on low-density designs. t Designs with more than 10K gates but fewer than 20K gates Structured techniques should be considered for designs in this density range. Nonstructured design practices are probably sufcient for highly combinatorial circuits without memory. Structured approaches should be considered as complexity is increased by the addition of sequential circuits, feedback, and memory. Consider scan for reduced cycle times and high fault grades. t uDesigns with more than 20K gates The complexity of circuits with this density usually requires structured approaches to achieve high fault grades. At this density, it is often hard to control or observe deeply embedded circuits. The overhead associated with structured testability approaches is acceptable at this density.
3-6
Choosing Structured Tools
3.6

Built-in self-test (BIST) or parallel module test (PMT) can be used to test RAM MegaModules. PMT is the most appropriate method for other MegaModules. This method provides the best high fault coverage and diagnostic capability. PMT reduces test time by eliminating the need to propagate test-control signals and circuit-response signals through complex surrounding logic to external pins. Design cycle time is also improved with PMT because TI provides test patterns for MegaModule functions. Scan is the preferred structured approach for sequential logic. The available scan choices are: t t t t t t Clocked scan Multiplexed ip-op scan Level-sensitive scan design (LSSD) Clocked level-sensitive scan design Parallel scan paths Partial scan
The choice between scan approaches is a trade-off between the impact on area and ac performance. The scan approach chosen should be used exclusively. Mixing scan approaches in the same device is not recommended.
3.6.1
Clocked Scan
A clocked scan ip-op has separate clock and data inputs for scan and system-mode operation. It also has separate data outputs for scan and system-mode operation. The clock-to-scanout propagation delay is purposely slowed. This reduces the chance of skew in the scan clock distribution network that could cause timing race conditions in the scan path. The separate scanout output isolates the loading of the scan-path routing from the system mode output. Clocked scan is a suitable choice for partial scan designs. This scan style uses a separate clock for scan and system-mode operation. This clock separation means that nonscan ip-ops are not clocked during the scan operation.
3.6.2
Multiplexed Flip-Flop Scan

A multiplexed ip-op scan element consists of a ip-op with a single clock and a 2:1 multiplexer at the data input. This scan style relies on minimal clock
3-7
skew in the clock distribution network to prevent timing race conditions in the scan path. Multiplexed scan is not a good choice for partial scan designs. This scan style uses a common clock for scan and system-mode operation. This clock sharing means that nonscan ip-op clock inputs must be gated to disable them during the scan operation.
3.6.3
Level-Sensitive Scan Design (LSSD)

Level-sensitive scan design (LSSD) is implemented with a level-sensitive register latch. Nonoverlapping, two-phase clocks are required. This device does not contain hazards or race conditions. The LSSD scan adapts well to partial scan designs.
3.6.4
Clocked Level-Sensitive Scan Design

A clocked LSSD latch has separate clock and data inputs for scan- and system-mode operation. It also has separate data outputs for scan- and system-mode operation. The separate scan outputs isolate the system-mode data output from the scan-mode circuit loads. Clocked LSSD adapts well to partial scan design.
3.6.5
Parallel Scan Paths

The length of scan paths should be considered because of test time. For example, a single path of 2000 scan registers requires 2000 tester periods to load. Four paths of 500 scan registers can be loaded in parallel in 500 tester periods.
3.6.6
Partial Scan
While scan paths can convert sequential circuits into combinatorial circuits for testing, this procedure adds overhead and degrades performance. The ATPG tool may be the driving force in making the scan decision. Partial scan could be a good decision, if you follow good design practices and have an ATPG tool that can handle partial scan. In these cases, scan elements could be omitted from portions of the design that cannot tolerate the performance impact of scan.
3-8
Establishing a Diagnostic Pattern Set to Expedite Debug
3.7
Establishing a Diagnostic Pattern Set to Expedite Debug

Establishing a diagnostic functional pattern set is an important step in decreasing the time-to-market for an ASIC device. The purpose of this pattern set is to isolate circuitry for analysis. The approach varies among types of applications. Key architectural blocks to isolate are memory control, state machines, and bus control. The isolation needs to be sufcient to allow simulation analysis to determine whether a fault is design, test pattern, or fabrication-related. At this point you need to establish whether ac critical path measurements are required as part of the production testing. The ac critical path pattern sets should be chosen based on system requirements.
3-9
Generating High-Fault-Grade Test Patterns
3.8
Generating High-Fault-Grade Test Patterns

The fault grade of a test pattern set determines the best possible quality level attainable with that set of patterns. The development of a high-fault-grade set of test patterns should come in three stages. Stage 1: Develop a set of functional patterns. You should develop these in the logic-simulation stage of design. Added to these are the diagnostic test patterns developed for debug analysis. The functional and diagnostic patterns need to be fault graded. This forms the starting point for automatic test pattern generation (ATPG). Stage 2: Use ATPG for the highest possible fault grade. A high fault grade in a short cycle time is possible if the development team has followed a testability strategy and has complied with the following guidelines: s s s Designed a device with controllability and observability Selected a quality ATPG tool Followed guidelines imposed by the ATPG tool
Stage 3: Generate a dc leakage test. The classic stuck-at fault model is used by the ATPG tool, but it does not represent some types of CMOS faults. The dc leakage testing, often referred to as IDDQ testing, is useful in supplementing stuck-at testing. Implementing IDDQ testing requires a test mode to turn off all circuits that produce dc current, such as pullup and pulldown resistors.
3-10
Simulating Test Patterns and Timing
3.9
Simulating Test Patterns and Timing

Two types of simulation are required during development. Logic simulation veries both functionality and performance of the device. Test pattern simulation produces the information needed to verify the test patterns in a tester environment. Testers are synchronous systems that require all input patterns to be changed at xed points within the test cycle. Normally, with the exception of primary clocks, input signals can change only near the beginning of each test cycle. The duration of the test cycle varies from system to system and determines the upper frequency limit at which a device can be tested. Typically, however, there are other limitations that establish the testing frequency. TI provides a tester constraints table in the test chapter of each productspecic design manual (see Related Documentation From Texas Instruments, p. viii) that summarizes these limitations. Additional requirements include the following: t t t t The tester load must be applied to the output. The tester slew must be applied to the input. Each TDL pattern set must contain initialization vectors. Simulations must be run at both the minimum and the maximum propagation delays in the device macro library. Inputs and outputs must satisfy the test description language (TDL) timing restrictions provided by TI.
3-11
Converting Test Patterns to TDL
3.10
Converting Test Patterns to TDL

The testers are programmed using TDL. TDL is a TI-developed test language used as a source input to program automated test equipment. The TDL contains a set of test vectors. Test vectors dene input signals and expected output signals. Each test vector denes a test period of xed duration. The entire test program denes a set of sequential test periods that perform a logic verication of the device being tested.
3-12
Planning for Test Pattern/Logic Revision Compatibility
3.11

The most frustrating experience is to debug a problem generated by human error. Development is a dynamic process. Make provisions in your testability strategy to ensure that design revisions drive any necessary test program revisions. Functional equivalent design revisions can affect timing and ATPG tool pattern sets. The most common cause of test-program-related problems at ASIC vendors is out-of-date pattern sets.
3-13
Figure 31.
Testability Development Flow

Pick a technology vendor
Commit to good testability design practices Establish a fault-grade requirement Yes IEEE Std 1149.1 required for PCB? No
Review IEEE Std 1149.1
Yes
Density = Gates Gates < 10K No
Yes
10K < Gates < 20K No
Consider Scan
Recommend Scan
Choose structured approach PMT Scan BIST Develop diagnostic pattern sets and locate critical paths Develop high-fault-grade pattern sets Generate test description language
Simulate test patterns and timing Have a system to ensure test patterns are compatible with logic revisions
Minimum time-to-market
3-14
Chapter 4
Test Pattern Requirements
This chapter summarizes the Texas Instruments test pattern requirements.
Topic
Page
Responsibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TDL Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4-1
Responsibilities
4.1
Responsibilities
You have the responsibility to provide a set of required test patterns to TI. These test patterns are used to perform dc parametric testing, logic verication, and propagation delay tests. TI accepts additional usergenerated patterns on a limited basis. The test patterns for handoff to TI must be described in TDL format. TDL stands for test description language and is the test pattern format accepted by TIs internal set of tools. The contents of each TDL set must conform to a set of test ow constraints. See Test Pattern Generation on page 121 for information on test pattern generation details. The designs testability schemes determine which TDL sets are required. Presently, three testability schemes are supported by TI ASIC: t t t Scan TI parallel module test (PMT) for MegaModule testing Built-in self-test (BIST)
A set of TDL types has been dened by TI ASIC to identify the functions of each TDL to the set of internal tools. For example, a TDL set written to facilitate dc parametric and IDDQ tests would be assigned the DC_PARA and IDDQ TDL types.
4-2
TDL Type Descriptions
4.2

The following subsections present the required and optional TDL types for scan, BIST, and PMT types. All TDLs are stand alone (meaning they contain initialization vectors).
4.2.1
Required TDL Pattern Sets

The following three TDL sets are required for each design, regardless of the testability scheme used: DC_PARA TDL used to facilitate dc I/O parametric testing. Each buffer is toggled to all available input and/or output states. To reduce test time, a minimum number of vectors is desired. TDL used to verify the logic function TDL used to facilitate static IDDQ testing
FUNC IDDQ
At least one propagation delay measurement is required per design. The FUNC or DC_PARA TDL can be used to facilitate a propagation delay test by the insertion of an ASIC_TEST statement with the PROP keyword into the test vectors.
4.2.2
TDL Pattern Sets for Scan

Products implementing scan require the following additional TDL sets: SCAN SCANCHK TDL used to verify logic integrity. A SCAN TDL set can replace the requirement for a FUNC TDL set. TDL used to check scan path integrity. Each scan path is checked individually, and a xed set of states is loaded/ unloaded for each scan register.
4.2.3
TDL Pattern Sets for BIST

Products implementing BIST require the following additional TDL set: BIST TDL that executes built-in self-test. If a BIST TDL fails, a DIAGNOST TDL set may be required to identify the root cause of the failure.
4-3
4.2.4
TDL Pattern Sets for PMT

Products that implement PMT have the following additional TDL sets provided by TI. ANALOG_<name> PMT PMTSETUP TDL used to verify analog MegaModule functions TDL used to verify MegaModule logic functions TDL used to initialize the generic test access port (GTAP) controller to select a target MegaModule for test TDL used to validate PMT MegaModule hookup to the package pins. This TDL is not run on the tester (ATE).
PMT_SIM
4.2.5
Optional TDL Pattern Sets

The following are optional TDL sets. BIST_AC TDL used to verify timing requirements. If a BIST_AC TDL fails, a DIAGNOST TDL set may be required to identify the root cause of the failure. TDL that provides traceability of functional failures to specic logic blocks. A DIAGNOST TDL set is applied during nonproduction testing. TDL used to verify timing requirements TDL used to check the GTAP register scan path integrity TDL used to verify timing requirements. Patterns are run at LOGIC VERIFICATION frequencies. All other AT-SPEED constraints apply. TDL used to deactivate the CMOS dc current producers in designs with dc turnoff capability TDL used to facilitate dc input threshold testing. The inputs are tested one at a time by means of a NAND tree or IEEE Std 1149.1. TDL is stand alone. TI will accept a VIH_VIL test waiver instead of a VIH_VIL pattern set.
DIAGNOST
FUNC_AC GTAPCHK SCAN_AC
TURNOFF VIH_VIL
TI uses the customer-provided TDL to automatically generate the tester program. The TDL is rst subjected to a quality check to verify that it conforms
4-4
to the constraints of the test operation. Syntax and conformance to tester constraints are veried by the TI TDL rule checking tool called TDLCHKR. The TDL timing checks are performed on a simulator. The PMT TDL sets are added to the QC-veried customer-generated patterns. The combined pattern sets are then converted to a tester program by a software package called AUTOGEN. Table 41 summarizes the TDL pattern set requirements. Refer to the test chapter of the product-specic design manual to see the test pattern rate and other test constraint data.
Table 41. TDL Pattern Set Requirements Summary

Test Constraint Category Prop Delay Option (see Notes: 1)

TDL Type DC_PARA FUNC IDDQ BIST BIST_AC DIAGNOST FUNC_AC GTAPCHK SCAN SCANCHK SCAN_AC
Required

Optional
dc Parametric and Logic Verication

AtSpeed
N/A
N/A

(see Note

Notes: 2) TURNOFF VIH_VIL

Notes:

1) At least one propagation delay measurement is required per design. The TDL can be used to facilitate a propagation delay test by the insertion of an ASIC_TEST statement with the PROP keyword into the test vectors. Propagation delay measurements are not allowed for at-speed TDL types. 2) The maximum scan frequency is the same as for the logic verication constraints. All other at-speed constraints apply.
4-5
4-6
Chapter 5
Ad Hoc Testability Practices
This chapter describes various ad hoc techniques that can be used to make a design testable.
Topic
Page
Logic Design With Testability in Mind . . . . . . . . . . . . . . . . . . . . . . 52 Improving Testability Via Unused Pins . . . . . . . . . . . . . . . . . . . . . 53 Using Bidirectional Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Initializing the Circuit to a Known State . . . . . . . . . . . . . . . . . . . . 55 Avoiding Asynchronous Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 57 Avoiding Gated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Allowing Internal Clocks to Be Bypassed From Circuits Inputs 59 Allowing Counters and Dividers to Be Bypassed . . . . . . . . . . . . 510 Splitting Long Counter Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Multiplexing to Provide Direct Access to Logic . . . . . . . . . . . . . . 512 Breaking Feedback Paths in Nested Sequential Circuits . . . . . . 514 Allowing Redundant Circuitry to Be Tested . . . . . . . . . . . . . . . . . 515 Watching for Signals That Reconverge . . . . . . . . . . . . . . . . . . . . . 516 Decoupling Linked Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Johnson Counter Test Signal Generator . . . . . . . . . . . . . . . . . . . 518 Shift Register Test Signal Generator . . . . . . . . . . . . . . . . . . . . . . . 519 Shift Register Used to Obtain Observability . . . . . . . . . . . . . . . . 520
5-1
Logic Design With Testability in Mind
5.1
Logic Design With Testability in Mind

Designing for testability refers to a design approach that enables thorough testing of a system with minimal effort and maximum coverage. A circuit is termed testable when the testing effort involved is minimal compared to the design and manufacturing efforts. The key concepts in design for testability (DFT) are controllability and observability. The purpose of the various DFT techniques is to increase the ability to control and observe internal nodes from external inputs and outputs. The states of a circuit buried in logic cannot be easily controlled or observed by external pins. This lack of control makes the generation of test vectors more time consuming and usually results in excessive numbers of test vectors being generated. This problem can be addressed by adding special test pins that increase the controllability or observability of these states. If extra pins are not available, input combinations that cannot occur during normal operation of the circuit can be used to place the circuit in the test mode. On-chip test circuitry can also be used to partition the circuit into logical subsystems that can be tested in parallel. Testing smaller logical subsystems simplies the task of test vector generation. If the logical subsystems operate in parallel, these test vectors can be merged, resulting in reduced test time on the tester. Two basic approaches to testing are prevalent in the industry. The rst approach is categorized as ad hoc and the second as structured. The ad hoc techniques can be applied to a given product, but require that each circuit be examined on an individual basis. The structured techniques follow a design methodology and lend themselves more easily to design automation. Various ad hoc techniques can be applied to ensure that a design is testable. Such techniques essentially improve controllability, observability, and predictability of a design. Some of these techniques are fairly simple and can be implemented with minimum overhead. In addition, they aid in the development and debugging of the circuit and its test program. Brief descriptions of some ad hoc testability guidelines are described in the following sections.
5-2
Improving Testability Via Unused Pins
5.2
Improving Testability Via Unused Pins

Observability of an internal node can be accomplished by connecting the node to an unused package pin (if available), as illustrated in Figure 51.
Figure 51.
Observing an Internal Node

PAD Test Pin
Unused package pins can also be used to control internal nodes that are difcult to access otherwise. The circuit shown in Figure 51 has been modied to allow the injection of test signals (ENABLE high) or to operate normally (ENABLE low). Figure 52 illustrates the recongured circuit.
Figure 52.
Test Signal
Test Signal Injection

PAD
ENABLE
PAD
5-3
Using Bidirectional Pins
5.3
Using Bidirectional Pins

Using bidirectional buffers instead of single-mode input and output buffers increases the effectiveness of the package pins. In Figure 53 data ows from INA to OUTB. In TEST mode (ENABLE high), test data and control signals enter OUTB and test results are read out at INA.
Figure 53.
Bidirectional Pins Giving Access to Internal Nodes
ENABLE Test Data Out Bus INA PAD Core Logic Core Logic PAD Test Data In OUTB
5-4
Initializing the Circuit to a Known State
5.4

The entire circuit must be initializable to a known state, regardless of its current state. To easily predict the output of a circuit, all latches and ip-ops must have set or reset capability. Circuits that never need to be set to a particular state during normal operation (such as frequency dividers) also require a set/reset capability, or must be capable of being initialized through a shift register scan path. The tester needs to know how many pulses to apply before the rst pulse appears on the output, and this depends on the initial state of the circuit. Figure 54 shows a state machine with three states. No combination of select and clock inputs can initialize the circuit to a known state.
Figure 54.
Uncontrollable State Machine

10 D Q QZ D Q 11 QZ 01
CLOCK SELECT Output
By using a ip-op with a clear, as shown in Figure 55, it is possible to force state 00. Successive clock pulses then select states 10, 11, and 01. State verication can be made from this list: State 00Output always 1 State 10Output equals inverse of SELECT State 11Output always 0 State 01Output equals SELECT
5-5
Figure 55.
Using Clear to Add Controllability

00
Q QZ
Q QZ
10
01
11
CLEAR CLOCK SELECT Output
A power-on clear mechanism, which initializes the circuit in the actual system conguration, is not an adequate test initialization implementation. Although this function must also be tested, the tester loses many of its utility programs if initialization is performed only in this manner, and overall testing suffers dramatically. By adding the special set or reset signal (Figure 55), the circuit can be directly set into a known state, and the tester is guaranteed to have the rst pulse appear after a known number of cycles. All of the testers utility programs remain intact.
5-6
Avoiding Asynchronous Circuitry
5.5
Avoiding Asynchronous Circuitry

For asynchronous systems, changes in the output state depend on circuit delays that are a function of wafer processing. Due to the variation in process parameters, there is no guarantee of exactly when an output changes state. It may be at the end of one cycle or at the beginning of another. Because the test vectors must be determined before the test is started, it is very difcult to keep the tester synchronized with the circuit. Therefore, testing asynchronous circuitry is difcult and costly (and in some cases, impossible). In an asynchronous SR latch, such as in Figure 56 a, set and reset signals can change state at any time, causing the output to change state at any time during any period. The output transition is dependent on the delays that create the set and reset signals. Addition of the clock, shown in Figure 56 b, ensures that if the set or reset signal changes state, the output changes only after the next clock transition.
Figure 56.
Add Clock to Asynchronous Latch

(a) S Y
(b) S Y CLOCK Y R
5-7
Avoiding Gated Clocks
5.6
Avoiding Gated Clocks

Gating clocks creates an asynchronous circuit. The extra delay through the gate unsynchronizes the gated clock from the original system clock. Unwanted glitches on the gated clock can be the result, as shown in Figure 57(a). The safest approach is to use an enabled edge-triggered ip-op, as shown in Figure 57(b). The timing for this circuit is more tolerant of propagation delays.
Figure 57.
Gated Clock and Alternative

(a) Gated Clock
Clock
Gate
Gate Delay Second Clock
Gated Clock Ideal Timing Slight Delay in Gate Signal
(b) Edge-Triggered Clock Clock Margin Enable
Output Ideal Timing Slight Delay in Enable
5-8
Allowing Internal Clocks to Be Bypassed From Circuits Inputs
5.7
Allowing Internal Clocks to Be Bypassed From Circuits Inputs

On-chip oscillator circuitry or other periodic pulse generating circuitry makes synchronization of the tester and the circuit very difcult (Figure 58 a). By allowing these clock signals to be bypassed and generated by the tester, the tester is automatically synchronized with the circuit (Figure 58 b). Output the bypassed clock signal as a circuit test.
Figure 58.
Bypass Internal Clock Generators

(a) (b) Oscillator Out Clock Signal
Oscillator
Oscillator Test Clock Test Select M U X Clock Signal
5-9
Allowing Counters and Dividers to Be Bypassed
5.8
Allowing Counters and Dividers to Be Bypassed

Bypassing sequential circuits decreases the number of test vectors required to test the device and reduces the test time. The sequential circuitry is tested once and then is bypassed while the rest of the circuit is being tested. When a divider is used to convert a 1-MHz clock signal to 1 kHz, the tester must apply 1000 test vectors for each 1-kHz pulse (Figure 59a). However, when bypass circuitry is available, the divider can be tested once and then bypassed. The circuitry controlled by the divider can then be tested at a much higher frequency by using a 1-kHz clock directly, reducing test time (Figure 59 b). Output the bypassed counter/divider signal as a circuit test.
Figure 59.
Bypass Counters and Dividers

(a) (b) Divider Out
1-MHz Clock
1000:1 Divider
1-kHz Clock
1-MHz Clock
1000:1 Divider Test Clock Test Select M U X 1-kHz Clock
5-10
Splitting Long Counter Paths
5.9
Splitting Long Counter Paths

Long counter paths should be split into smaller testable modules. For example, a 16-bit counter requires 65 536 test patterns for full functional test. However, the same counter implemented using two 8-bit counters coupled with additional control circuitry, as shown in Figure 510, requires only 259 test patterns. The testing sequence can be performed by following these steps: 1) Clear both counters and enter TEST mode (TEST/NORM = Logic 1). 2) Apply 255 clock pulses; the test pin should be high. 3) Reset TEST/NORM to logic 0 and apply one additional clock pulse; the test pin should now be low, proving correct operation of both counter sections.
Figure 510. Long Counter Path Divided for Testing

TEST/NORM CLK
A1 CLR1
QA1 QB1 QC1 QD1 QA2 QB2 QC2 QD2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2:1 MUX S A B Y A1 CLR1 QA1 QB1 QC1 QD1 QA2 QB2 QC2 QD2 Q8 Q9 QA QB QC QD QE QF Test Pin PAD
A2 RESET CLR2
A2 CLR2
Dual 4-Bit Ripple Counter
Dual 4-Bit Ripple Counter
5-11
Multiplexing to Provide Direct Access to Logic
5.10

In the following examples, test data and test enable signals can come from either external pins or test structures like those previously discussed. In Figure 511, an output multiplexer in normal mode passes data from Logic B to the output. The ENABLE line switches the multiplexer to pass data from Logic A to the output, which provides observability for Logic A.
Figure 511. Multiplexing an Output Pin to Improve Observability

ENABLE S Output A DATA IN PAD Logic A Logic B B 2:1 MUX Y PAD
In Figure 512, a multiplexer gives controllability to Logic B by allowing the input pin DATA to be connected directly to Logic B, bypassing Logic A.
Figure 512. Multiplexing an Input Pin to Improve Controllability

ENABLE S Output A DATA IN PAD Logic A B 2:1 MUX Y Logic B PAD
In Figure 513, testability for both logic blocks is enhanced by using both input and output multiplexing.
5-12
Figure 513. Multiplexing Both Inputs and Outputs to Improve Testability

ENABLE 1 ENABLE 2 S A DATA IN PAD Logic A B 2:1 MUX Logic B B 2:1 MUX Y S Output A Y PAD
Of the three ip-ops shown in Figure 514, only the last ip-op connects to a package pin. If a 4:1 multiplexer is added, as shown in Figure 515, each ip-op output can be connected individually to the output pin.
Figure 514. Example of Unobservable Flip-Flop Outputs

Output Q DATA D QZ D Q QZ D Q QZ PAD
CLRZ RESET CLOCK
CLRZ
CLRZ
Figure 515. Flip-Flop Outputs Made Observable With a Multiplexer

4:1 MUX ENABLE 1 ENABLE 2 A B C0 C1 Q DATA D QZ D Q QZ D Q QZ C2 C3
Output Y PAD
CLRZ RESET CLOCK
CLRZ
CLRZ Hi Lo Tie-Off
5-13
Breaking Feedback Paths in Nested Sequential Circuits
5.11
Breaking Feedback Paths in Nested Sequential Circuits

In sequential circuits, the next state is a function of the present state and current stimulus while the present state is determined by the stimulus applied previously. Therefore, multiple patterns need to be applied to control or observe the sequential circuit. The length of the test pattern increases dramatically if one sequential circuit feeds back to another sequential circuit. This is also known as nesting of sequential circuitry. In Figure 516 a, many vectors are required to stimulate the modules or to pass the response to the rest of the circuit. By partitioning the sequential circuits and breaking the feedback paths, controllability and observability can be improved (Figure 516 b).
Figure 516. Nesting of Sequential Circuits

(a) In Sequential Circuit Sequential Circuit Sequential Circuit Out
(b) In Sequential Circuit MUX Sequential Circuit MUX MUX MUX TEST IN Sequential Circuit MUX Out
5-14
Allowing Redundant Circuitry to Be Tested
5.12
Allowing Redundant Circuitry to Be Tested

Redundant circuitry is often included to improve performance, reliability, or fabrication yields. Access must be provided to allow both portions of circuitry to be tested separately to ensure that they both work. Figure 517 (a and b) shows a circuit with an OR gate conguration on the output. This type of circuit is inherently untestable unless the sections can be individually disabled by adding circuitry. Two test inputs as shown in (b) are required if the two disable signals cannot be derived from logic elsewhere in the core logic. An alternative solution is to eliminate any unnecessary redundant logic.
Figure 517. Redundant Circuitry

(a) Test A Logic A In Logic B Out In Logic B Test B Logic A Out (b)
5-15
Watching for Signals That Reconverge
5.13
Watching for Signals That Reconverge

Signals that fan out in multiple directions from a single source and later reconverge at the inputs to a functional module can create logic hazards and untestable circuits. The circuit shown in Figure 518 a is hazard-free but has an untestable fault. If B and C are both high, the output of G4 remains high regardless of the value of G2. Therefore, a short at the output of G2 is not be detected. By breaking the reconvergent path of the signal A, as shown in Figure 518 b, and by making the test input high, the output of G2 can be tested. This additional circuitry greatly enhances the testability of the circuit.
Figure 518. Reconverging Signals

(a) A G1 A (b) G1
B C
G2
G4
G1+G2+G3
B C
G2
G4
G1+G2+G3
G3 TEST
G3
5-16
Decoupling Linked Logic Blocks
5.14
Decoupling Linked Logic Blocks

Decoupling normally linked logic blocks with AND gates so that each can be tested separately is shown in Figure 519.. Once again, unused package pins may be required to control the signal separation, unless unused states from a decoder are available.
Figure 519. Decouple Circuit Blocks

Module 1 Module 2
CONTROL 1 DEGATE CONTROL 2 Module 3
5-17
Johnson Counter Test Signal Generator
5.15
Johnson Counter Test Signal Generator

The Johnson counter shown in Figure 520 requires only two pins (MCLR and CLK) to give 10 active-low test enable signals (T0Z-T9Z). T0Z stays active during your designs normal operation.
Figure 520. Johnson Counter to Minimize Test Pins

T0Z T1Z T2Z T3Z T4Z T5Z T6Z T7Z T8Z T9Z
Q D QZ CLRZ D
Q QZ CLRZ D
Q QZ CLRZ D
Q QZ CLRZ D
Q QZ CLRZ
CLK MCLR
5-18
Shift Register Test Signal Generator
5.16
Shift Register Test Signal Generator

Three pins (RESETZ, CLOCK, and TESTDATA) control the shift register shown in Figure 521. An 8-stage shift register allows you to insert up to 256 unique codes, which can either be test data or patterns enabling specic tests. Use RESETZ to inhibit the test function.
Figure 521. Test Signal Generator Using a Shift Register

RESETZ CLOCK TESTDATA A CLRZ
QA QB QC QD QE QF QG QH
TESTDATA1 TESTDATA2 TESTDATA3 TESTDATA4 TESTDATA5 TESTDATA6 TESTDATA7 TESTDATA8
8-Bit Parallel-Out Serial Shift Register
5-19
Shift Register Used to Obtain Observability
5.17
Shift Register Used to Obtain Observability

With the addition of an 8-bit shift register, the status of eight internal nodes is transmitted via one output pin, as shown in Figure 522. Because only two internal nodes drive output pins, other internal nodes in the logic are unobservable. A shift register with a length of eight bits can be used to transmit the status of eight shaded internal nodes to the TESTOUT pin. This concept can be expanded to n bits as needed.
Figure 522. Shift Register Adding Observability to Buried Nodes

Hi Lo CLK2 LOAD PAD DATA Module A CLK CKINZ SERIN SHLD A B C D E F G H QH QHZ OUT1
PAD TESTOUT
Module B
Module C
8-Bit Parallel-Out Serial Shift-Register CLK1 Module D PAD OUT2
5-20
Chapter 6
Structured Testability Practices
This chapter discusses the benets and limitations of scan design and presents several scan design approaches.
Topic
Page
Structured Approaches to Designing for Testability . . . . . . . . . . 62 Clocked Scan Flip-Flop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Multiplexed Flip-Flop Scan Design . . . . . . . . . . . . . . . . . . . . . . . . 65 Clock Skew and Edge-Triggered Flip-Flop Scan . . . . . . . . . . . . . 67 Guidelines for Flip-Flop Scan Design . . . . . . . . . . . . . . . . . . . . . . 610 Clocked LSSD Scan Flip-Flop Design . . . . . . . . . . . . . . . . . . . . . . 68 Scan Path Loading on Critical ac Path . . . . . . . . . . . . . . . . . . . . . 611 Bus Contention and Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . 612 Test-Isolation Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 Where Scan Is Not Efcient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
6-1
Structured Approaches to Designing for Testability
6.1
Structured Approaches to Designing for Testability

The introduction to ad hoc approaches discussed the need for observability and controllability. These ad hoc techniques are point solutions. Scan approaches are more structured. The structured scan approach favors design automation and rule checking. There are many varieties of scan design and each has its own impact on the hardware. All of these techniques ease the problem of testability by making the circuit appear to be structured as a combinatorial network. The nature of scan design makes it very easy to control and observe every register/latch (logic storage) element in the circuit. The basic concept involves serially shifting test data into the logic storage elements and scanning out the test results. This allows initialization of all the logic storage elements to desired states and permits the contents of the buried logic storage elements to be examined easily.
6-2
Clocked Scan Flip-Flop Design
6.2

The clocked scan ip-op has separate clock and data inputs for scan-test and system modes, as shown in Figure 61. The ip-op inputs DATA (D) and SCANIN DATA (SD) represent the system and scan-test data inputs. The D input is clocked into the ip-op by CLOCK. The SD input is clocked into the ip-op by SCAN CLOCK. The output (Q) and SCANOUT (SO) outputs are logically equal. The output SO has a weak drive. This results in long clock-toscanout propagation times, reducing the chance of skew in the scan clock distribution network from causing timing race conditions during scan shifting. The SO also isolates the loading of the scan path from the system output Q.
Figure 61.
Clocked Scan Flip-Flop

DATA CLOCK D Q DATA OUT
SCANIN DATA SCAN CLOCK
SD SO SCANOUT
Interconnecting several clocked scan macros gives the circuit a serial scan shift capability that reduces the testing of a sequential circuit to the testing of a combinatorial circuit, as shown in Figure 62. The SO output of one ip-op feeds the SD input of the next ip-op. This is repeated until the scan path is formed. The TI library offers clocked scan ip-op macros.
6-3
Figure 62.
Clocked Scan Flip-Flop Circuit Interconnect
DATA IN
Logic
Logic
Logic
Logic
DATA OUT
SCANIN
SD SO
SD SO
SD SO SCANOUT
CLOCK SCAN CLOCK
The silicon overhead to implement clocked scan is in the range of 5 to 20 percent. Up to three additional pins are required to implement this scan style. Only SCAN CLOCK is required to be dedicated; the remainder of the pins can be shared with primary inputs and outputs.
6-4
Multiplexed Flip-Flop Scan Design
6.3

The multiplexed ip-op scan method is very similar to the clocked-scan approach but differs in the ip-op design. The ip-op has a single CLOCK and a 2:1 multiplexer at the input, as shown in Figure 63. The multiplexer inputs of DATA (D) and SCANIN DATA (SD) represent the system and test data inputs selected by the SCAN ENABLE (SE) input signal. The Q output of one ip-op then feeds the SD input of the next ip-op. This is done until the scan path is formed, as shown in Figure 64. TI offers multiplexed scan ip-op macros.
Figure 63.
Multiplexed Scan Flip-Flop

D SD /1 D 1 MUX S Q DATA OUT
SCAN ENABLE
QZ CLOCK
DATA OUT
Figure 64.
SCANIN
Multiplexed Flip-Flop Scan Path

SCANOUT
DATA IN
Logic
SD D Q SE
Logic
SD D Q SE
Logic
SD D Q SE
Logic
DATA OUT
SCAN ENABLE CLOCK
6-5
There are some disadvantages. Adding logic into the data path limits the speed at which the circuit can be clocked. The hardware overhead is related to the number of registers, because each requires a 2:1 multiplexer. The silicon overhead to implement multiplexed ip-op scan is in the range of 5 to 15 percent. Up to three additional pins are required to implement this type of scan. Only the SCAN ENABLE pin must be dedicated; the remainder of the pins can be shared with primary inputs and outputs.
6-6
Clock Skew and Edge-Triggered Flip-Flop Scan
6.4
Clock Skew and Edge-Triggered Flip-Flop Scan

Edge-triggered ip-op scan relies on minimal clock skew in the clock distribution network. You can inadvertently introduce clock skew, as demonstrated in the following two examples. t You decide to use a clock signal that is the input to a clock distribution macro. This clock signal becomes signicantly skewed relative to the clock signal from the clock distribution macros output. The ATPG tools do not allow gated or internally generated clocks. You can isolate the gated or internally generated clocks with a SCAN clock that meets all the scan rules. Typically, this is done by adding a multiplexer to the clock paths. During normal mode, the multiplexer selects the gated or internally generated clock. This technique meets scan design rules but also introduces clock skew.
If two successive scan path ip-ops have signicantly skewed scan clocks, where the rst scan ip-op is clocked before the second scan ip-op, a timing race condition may exist. The rst scan ip-op captures the next scan data bit using the earlier scan clock, and its Q output changes and races to the second scan ip-op along with the later scan clock. If the scan data arrives rst, this scan data is clocked into both scan ip-ops. The scan data appears to jump across the rst scan ip-op directly into the second scan ip-op on a single scan clock cycle. When this type of jump occurs, the ATPG test patterns interpret it as detecting a stuck-at-fault and reject the circuit. Simulation of the scan shift operation is the only way to verify that scan clock skew does not cause jumping.
6-7
Clocked LSSD Scan Flip-Flop Design
6.5

The clocked LSSD scan ip-op, shown in Figure 61, is a derivative of the clocked scan ip-op. The ip-op inputs DATA (D) and SCANIN DATA (SD) represent the system and scan-test data inputs. The D input is clocked into the ip-op by CLOCK (edge-triggered). The SD input is clocked into the ipop by TMC and TSC (two-phase non-overlapping clocks). The output (Q) and SCANOUT (SQ) outputs are logically equal. The SQ output also isolates the loading of the scan path from the system Q output. The Level-Sensitive Scan Design (LSSD) method is a very well-known approach. LSSD eliminates scan chain race conditions and other possible test problems related to clock skew, rise/fall times, and minimum circuit delays.
Figure 65.
Clocked LSSD Scan Flip-Flop

DATA IN CLOCK SCANIN DATA MASTER SCAN CLOCK SLAVE SCAN CLOCK D > SD TMC TSC SQ SCANOUT Q DATA OUT
Interconnecting several clocked LSSD scan ip-ops gives the circuit a serial shift capability that reduces the testing of a sequential circuit to the testing of a combinatorial circuit, as shown in Figure 66. The SQ output of one ip-op feeds the SD input of the next ip-op. This is repeated until the scan path is formed. The TI library offers clocked LSSD scan ip-op macros.
6-8
Figure 66.
CLOCK
Clocked LSSD Scan Flip-Flop Circuit Interconnect
DATA IN
L O G I C
D > SD TMC TSC
SQ
L O G I C
D > SD TMC TSC
SQ
L O G I C
D > SD TMC TSC
SQ
L O G I C
DATA OUT
SCANIN DATA MASTER SCAN CLOCK SLAVE SCAN CLOCK
SCAN OUT
The silicon overhead to implement clocked LSSD scan is in the range of 5 to 20 percent. Up to four additional pins are required to implement clocked LSSD scan, which can affect the circuit size and package selection. Only the Master Scan Clock and the Slave Scan Clock must be dedicated; the Scanin data and Scanout data can be shared with primary inputs and outputs.
6-9
Guidelines for Flip-Flop Scan Design
6.6
Guidelines for Flip-Flop Scan Design

The following design requirements must be met for successful ip-op-based scan designs: t All stored states must be in scan ip-ops. Cross-coupled latches are not permitted. All ip-ops in a scan path must have the same common clock. No logicgenerated or asynchronous clocks are permitted. One-shot delays and asynchronous timing are not permitted. All logic feedback paths must pass through scan ip-ops. All resettable scan ip-ops must be resettable only via a master or global reset. Resettable ip-ops are not required. Initialization can be accomplished by scanning in the initial state. No race condition may result from the application of a pulse at one external clock input while the other external clock inputs are held inactive and the remaining external inputs are stable.
t t t
Refer to the applicable (TGC2000, TSC4000, etc.) macro library summary for macros that are available to support ip-op-based scan designs.
6-10
Scan Path Loading on Critical ac Path
6.7
Scan Path Loading on Critical ac Path

Some scan implementations route the scan path off the macros signal path. A long scan path on an ac speed-critical node can cause unacceptable delay. The scan path can be separated from the signal path in the following manner. Select a scan element with both true and complementary outputs. In Figure 67, a multiplexed ip-op scan macro is chosen and the speed critical path is the true output. The scanout is taken from the complementary output. An inverter is placed after the complementary output to restore the signal polarity prior to the next scan ip-op on the scan path. Some ATPG software tools can handle scan path inversions, making the addition of the inverter in the scan path to restore polarity unnecessary.
Figure 67.
SCANIN
Isolate Scan Path Loading

SCANOUT
DATA IN
Logic
SD Q D SE QZ
Logic
SD D Q SE QZ
Logic
SD D Q SE QZ
Logic
DATA OUT
SCAN ENABLE CLOCK
6-11
Bus Contention and Scan Testing
6.8

Device damage or data corruption can occur during scan testing as a result of bus contention. The contention can occur when scanning in data through registers that control 3-state drivers on a bus. As data is scanned, the registers probably contain states that force contention. Figure 68 is an example of a circuit containing contention hazards.
Figure 68.
Bus Contention Hazard
SCAN ENABLE A Out
B C D1 D Q SE SD D2 D Q SE SD D3 D Q SE SD SCANOUT
SCANIN CLOCK
Bus contentions can exist if more than one scan register contains a logic 1 during scanin or scanout. The contention hazard must be removed by the addition of 3-state disabling circuitry. The disabling circuitry is activated with a scan-enable signal. This is the same enable signal used to control the multiplexer in the scan ip-op. An LSSD or clocked scan design would need a signal generated off a test-mode pin. Figure 69 shows the circuitry added to eliminate the contention hazard.
6-12
Figure 69.
Scan 3-State Disabling Logic
SCAN ENABLE A Out
B C D1 D Q SE SD D2 D Q SE SD D3 D Q SE SD
Disabling Logic SCANOUT
SCANIN CLOCK
6-13
Test-Isolation Modules
6.9
Full scan techniques provide a straightforward approach to ASIC testing for a high fault grade. For large, register-intensive designs, the full scan technique results in very long scan paths. Multiple scan path designs reduce the costs of test vector generation and fault simulation. Parallel testing of the modules also reduces test time.
6.9.1
Multiple Scan Paths

Parallel scan design is another approach to testing isolated modules. Parallel scan testing includes partitioning the circuit into modules and then testing the modules using scan. There are several ways to partition the circuit as shown in Figure 610.
Figure 610. Partition Into Test-Isolation Blocks
ROM
MegaModule
Serial Peripheral Interface
RAM
System Controller
Serial Communications Interface
Parallel Scan Blocks
The following is a list of suggested partitions: t Partition circuitry between bus interfaces. The bus interface boundary provides a natural partition. Partition stand-alone functions. Large designs are usually designed and simulated in blocks. Often the blocks are designed concurrently by different designers. Extend the block responsibility to include test-vector generation and fault simulation.
6-14
Partition logic to reduce the number of scan macros to fewer than 750 per logic block. This allows parallel testing of multiple paths rather than serial testing of one long path. Parallel test time is determined by the longest path. For this reason, the parallel paths should be of comparable lengths.
In Figure 611, Figure 612, and Figure 613, all the SCANIN and SCANOUT data pins can be multiplexed with other operational functions.
6-15
Figure 611. Multiple Clocked Scan Flip-Flop Scan Paths

Die Boundary SYSTEM CLOCK Global System Clock
SCANIN1
SCANOUT1 Block 1
SCANIN2
SCANOUT2
Block 2
SCANIN3
SCANOUT3
Block 3
SCAN CLOCK
6-16
Figure 612. Multiple Multiplexed Flip-Flop Scan Paths

Die Boundary SYSTEM CLOCK
Global System Clock
SCANIN1
SCANOUT1
Block 1
SCANIN2
SCANOUT2
Block 2
SCANIN3
SCANOUT3
Block 3
SCAN ENABLE
6-17
Figure 613. Multiple Clocked LSSD Scan Paths

Die Boundary SYSTEM CLOCK Global System Clock
SCANIN1
SCANOUT1 Block 1
SCANIN2
SCANOUT2 Block 2
SCANIN3
SCANOUT3 Block 3
2 MASTER SCAN CLOCK SLAVE SCAN CLOCK
6.9.2
Multiple Scan Path Patterns

During testing, the scan data is rst shifted into the device one bit per tester period into the scan path. After the scan data has been shifted into the device,
6-18
the tester then applies the input stimuli and the device under test returns to the normal mode of operation. Afterward, the response of the device is captured and shifted out for comparison. Normally, the scan result is shifting out while the new scan data is shifting in. As stated earlier, the longest scan path determines the length of the scan test vector. Because all the paths are being tested in parallel, it is necessary to add elements for the shorter paths so all vectors are equal in length. Figure 614 is an example of the elements added to the short scan vectors. These elements are dont cares on the inputs and masks on the outputs.
Figure 614. Scan Vectors for Multiple Scan Blocks

SCANIN Vector SCAN PATH 1 SCAN PATH 2 SCAN PATH 3 SCANOUT Vector
HHLLHLLHLLLHLLLHLH010101101101101101
YYYLHLHLHLLHLLHLLH010110110111101MMM
YYYYYYYHLHHLLHLLHL11011101110MMMMMMM
First Bit In Logic One Input = H Logic Zero Input = L Dont Care Input = Y
First Bit Out Logic One Output = 1 Logic Zero Output = 0 Mask Output = M
6-19
Where Scan Is Not Efficient
6.10
Where Scan Is Not Efficient

Although scan, as a structured design approach, is a very powerful methodology, there are certain circuit structures where other test methods such as PMT or BIST are more efcient, for example: t t t t Large macro functions (e.g., microprocessor cores) Compiled cells (e.g., RAMs, ROMs, and ALUs) Register les Any nondigital circuitry
A scan path is often used around these circuit structures to ensure that proper data and control signals are being supplied by surrounding logic. A scan ring is formed by placing a scannable latch or register on all signals entering or leaving the circuit structure (Figure 615).
Figure 615. Scan Path Around a Function

RAM SCAN_ENABLE MUX S DATA OUT Scan Element I I Y DATA OUT SCANOUT
DATA IN Scan Element
DATA IN
SCANIN
ADDRESS Scan Element
ADDRESS
R/W Scan Element
R/W
ENABLE Surrounding Logic In Scan Element
ENABLE Surrounding Logic Out
6-20
Chapter 7
IEEE Standard 1149.1-1990
This chapter explores the IEEE Standard 1149.1-1990 and the applications to testing printed circuit boards in a surface-mount environment.
Topic
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7-1
Overview
7.1
Overview
The IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (JTAG) foreword states, This standard denes a test access port and boundary-scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits. The facilities dened by the standard seek to provide a solution to the problem of testing assembled printed circuit boards and other products based on highly complex digital integrated circuits and high-density surface-mount assembly techniques. They also provide a means of accessing and controlling design-for-testability features built into the digital integrated circuits themselves. Such features might, for example, include internal scan paths and self-test functions as well as other features intended to support service applications in the assembled product. The IEEE Standard 1149.1 is usually applied by system designers. For this reason, system designers have a greater role in dening the specications for ASICs. To ensure that the ASICs work properly with other IEEE Standard 1149.1 test components, you as the ASIC designer must become familiar with this standard.
7-2
Boundary-Scan Architecture
7.2
Figure 71 shows the boundary-scan architecture specied by IEEE Standard1149.1. The boundary-scan architecture uses the following hardware components: t t t t t t Test access port controller (TAP) Instruction register (IR) Boundary-scan register (BSR) Device identication register (IDR) User test data register (UTDR) Bypass register (BR)
Figure 71.
Scan
ASIC Inputs
Boundary
Register
Core Logic
UTDR IDR BR TDI 8-Bit IR TMS TCK TRSTZ
VCC
TDO
TAP
Denotes Optional Structures
ASIC Outputs 7-3
7.2.1
Test Access Port Controller (TAP)

The test access port (TAP) controller integrates instructions on the test-mode select line in accordance with the timing established on TCK. It generates clock and control signals for the rest of the components used to implement IEEE Std 1149.1.
7.2.2
Instruction Register (IR)

The instruction register (IR) allows boundary-scan test instructions to be loaded into the ASIC. The boundary-scan test data registers are addressed via the instruction register.
7.2.3
Boundary-Scan Register (BSR)

The boundary-scan register (BSR) is made up of individual test cells that form the boundary-scan path. These cells form a partition around the device between the I/O cells and the core logic that can be used for a variety of test purposes, including continuity testing of PCB interconnects, I/O sampling, and insertion of known values at I/O points.
7.2.4
Device Identification Register (DIR)

The device identication register (DIR) is an optional register used for a variety of identication purposes, such as a manufacturer ID code, device registration number, or device revision number.
7.2.5
User Test Data Register (UTDR)

The upper test data register (UDTR) is an optional register that allows manufacturers to incorporate design-specic test-related features.
7.2.6
Bypass Register (BR)

The bypass register (BR) is a single-bit register that can be switched into the boundary-scan path so that the ASIC is bypassed during testing. This allows the testing of other boundary-scan compatible ICs more efciently by reducing the total boundary-scan path length to that of the IC under test.
7-4
7.2.7
Boundary-Scan Macro
The boundary-scan macros are placed around the periphery of the die next to the I/O structures. The general-purpose boundary-scan macro has the capability to capture, shift, and update. Figure 72 and Figure 73 depict the boundary-scan circuitry.
Figure 72.
General-Purpose Boundary-Scan Macro

SCANOUT
MODE SIGNAL IN SHIFT/LOAD G1 1 1 1D C1 1D C1
G1 1 1 SIGNAL OUT
SCANIN
CLOCK A
CLOCK B
7-5
Figure 73.
Boundary-Scannable PCB
Boundary-Scan Cell
Serial DATA IN
Serial DATA OUT
Serial Test Interconnect
System Interconnect
7-6
Chapter 8
Generic Test Access Port
This chapter introduces the generic test access port (GTAP), which is the Texas Instruments ASIC test controller. A dedicated implementation example is shown in Part 2 of this book, the Generic Test Access Port Application Report.
Topic
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Test RegisterBit Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8-1
Overview
8.1
Overview
The generic test access port (GTAP) is the TI ASIC test controller. From the device pins, the GTAP can be instructed to enable or disable any combination of the design-for-testability features. Test features are controlled by the GTAP unless another controller is present. The GTAP is designed to consolidate all previous ad hoc ASIC test methods into a single unied test methodology. It is general-purpose, compatible with a wide range of tests, and expandable to accommodate future test needs, hence the name generic. The GTAP is divided into two functions. They are the test register and the GTAP controller. The GTAP block diagram is shown in Figure 81. The GTAP implementation requires one dedicated package pin, four smart control pins, and one smart output pin. Smart pins are pins that have a test function in the test mode and a user-dened function in the normal operating mode. The TEST input to the GTAP controller must be dedicated to the test mode operation. The remaining GTAP controller inputs (SCAN, MCLK, and SCLK) are test-access protocol pins and can be implemented as smart pins. The SCANIN input to the GTAP test register is referred to as the test instruction pin and can be implemented as a smart pin. The SCANOUT output from the GTAP test register can also be implemented as a smart pin.
Figure 81.
GTAP Block Diagram

GTAP TWE GTAP Controller (TP012 or TP0B2) TEST1 TEST2 GTT GST Test Register (TP000s or TP0B0s) SCANOUT
TEST SCAN MCLK SCLK SCANIN
Enable Test Function 1
Enable Test Function 2
...
Enable Test Function N
8-2
Test Register
8.2
Test Register
The test register is an n-bit serial shift register, each bit corresponding to a specic test feature. Each ASIC test is selected by an n-bit code. Thus, the test register can also be interpreted as a test instruction register. It is loaded by shifting in n bits. Its serial nature economizes on ASIC resources (gates and interconnect). The test register is composed of TI TP000 (or TP0B0) macros (shown in Figure 82) daisy-chained together. The TP0B0 is the BiCMOS version of the TP000. The TP0B0 can substitute for the TP000 in the following descriptive sections.
Figure 82.
TP000 (Test Register Building Block)

TP000 or TP0B0 GBUSENZ (LOW)
GTSTEN (TEST1 OR TEST2)
MSEL
Master SCANIN GTT D C Q
Slave D C Q SCANOUT
GST
Figure 83 illustrates how TP000 macros are integrated to form a test register. The TP000 macros are chained together through their SCANIN and SCANOUT signals. The SCANIN of the rst TP000 is connected to an input pin. The SCANOUT of the last TP000 is connected to an output pin. Most of the remaining TP000 input signals (GTT, GST, and GBUSENZ) are connected in parallel. The GTSTEN signals are also connected in parallel but in two groups. These two groups correspond to the test register bit test function, either TEST1 or TEST2. Descriptions of TEST1 and TEST2 are presented later along with the GTAP controller.
8-3
Test Register
Figure 83.
Typical Test-Register Architecture

HIZ MSEL
NORMAL OUT DISABLE
TWE TEST2 TEST1 LOW GST GTT SCANIN PAD GTAP_SCAN_IN TP000 MSEL1 TEST1 TP000 MSEL2 TP000 MSEL3 TP000 MSEL4 TEST2 TP000 MSELn SCANOUT S PAD 1 GTAP_SCAN_OUT 1 2:1 MUX NORMAL OUTPUT DATA
8-4
Test RegisterBit Definitions
8.3

Each test register bit controls an ASIC test feature. TI has identied and optimized a set of test features. Table 81 lists the currently identied test features.
Table 81. Example Test-Register TP000 Assignments

TP000 PWRDN VIH_VIL SRAM_OFF VIH_VIL CLK SELECT HI Z PMT_I/O MSELA Type TEST1 TEST1 TEST1 TEST2 TEST2 TEST2 TEST2 Function Turns off pullups and pulldowns Enables VIH/VIL output Sets SRAMs to standby mode Selects VIH_VIL CLK I/O disable (sets high-impedance) Enables parallel module test datapaths Enables MegaModule #1
MSELN
TEST2
Enables BIST #1
MSELT
TEST2
Expansion
8-5
Table 82 lists the test register codes for selecting an ASIC test. The test register order is arbitrary.
Table 82. Example Test-Register Test-Selection Codes

TEST1 TEST2
ASIC Test PWRDN STATE VIH/VIL_CLK_A VIH/VIL_CLK_B IIH/IIL/IOZ CURRENT PU/PD CURRENT VOL/VOH PMT TEST ENABLE BIST TEST ENABLE EXPANSION
VIH_VIL SRAM CLK PWRDN VIH/VIL OFF SELECT HI Z PMT_I/O MSELA MSELN MSELT 1 0 0 1 0 1 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
8-6
Controller
8.4
Controller
The GTAP controller is the interface between the external device pins and the test register. It also controls test function sequencing via a state machine. Although the test register selects the test to be performed, the GTAP controller enables the selected test. The controller consists of ve device pins: TEST, SCAN, MCLK, SCLK, and SCANIN. Only TEST is dedicated; the rest can have normal input functions but assume GTAP controller input functions when TEST is high.
TEST SCAN
Dedicated test pin (low = normal mode, high = test mode) Shared test pin option. While TEST is low, this pin behaves as a normal input pin. While TEST is high, this pin behaves as a GTAP controller input pin, and low-to-high transitions change the controller state. Shared test pin option. While TEST is low, this pin behaves as a normal input pin. While TEST is high, this pin behaves as a GTAP controller input pin; a low level holds each TP000 master latch, and a high level passes data through each TP000 master latch. Shared test pin option. While TEST is low, this pin behaves as a normal input pin. While TEST is high, this pin behaves as a GTAP controller input pin; a low level holds each TP000 slave latch, and a high level passes data through each TP000 slave latch.
MCLK
SCLK
8-7
Communication Protocol
8.5
As shown in Figure 84, the device enters test mode when you set the dedicated TEST pin high. The controller is in TEST1 state, as shown in Figure 84. The controller can be cycled through the remaining states, WRITE, RESTORE1, TEST2, and RESTORE2, by toggling SCAN low-to-high. At any time, returning TEST pin low exits the test mode. Upon entering test mode (TEST high), any smart-controller I/O signals (excluding TEST) must be internally latched. Thus, the core logic continues to see the last normal pin values. This isolates the core logic from the controller signals. These signals remain latched until TEST returns low. The test port operates in two distinct testing levels, TEST1 and TEST2. These two levels serve to better control the testing environment. TEST1 Very mild test condition. The device state remains unchanged. Minor test functions are enabled, pullup and pulldown macros disabled, and VIH/VIL output enabled. All device pins remain in normal mode. Serious test condition. The device state may change as a result of performing one of these tests. Device pins may be forced to change directions. TEST1 features are also enabled during TEST2. Permits writing to the test register. Only the GTAP I/O pins should be active. All remaining device pins remain in normal mode. Because the shared controller I/O pins were internally latched on entering test mode, loading the test register does not disturb the device state if the normal values are reapplied during the RESTORE1 state. The scanout data from the test register are selected for the output buffer. Permits the shared controller pins to return to normal values without affecting the test register following WRITE state. Permits the shared controller pins to return to normal values without affecting the test register following TEST2 state.
TEST2
WRITE
RESTORE1
RESTORE2
Figure 84 is a state-transition diagram for the GTAP controller.
8-8
Figure 84.
GTAP-Controller State Transition Diagram

Off 0 1 TEST1 0 1 SCAN N L>H Y WRITE 0 1 SCAN N L>H Y RESTORE1 0 1 SCAN L>H Y TEST2 0 1 SCAN L>H Y RESTORE2 0 1 SCAN L>H Y N TEST N TEST N TEST TEST TEST
TEST
8-9
8-10
Chapter 9
Parallel Module Test
This chapter provides an overview of parallel module test (PMT). PMT provides direct access to MegaModules from device pins. See Part 4: Multiplexed Parallel Module Test Application Report for a detailed discussion of PMT. Informative application examples are supplied.
Topic
Page
Parallel Module Test of MegaModules . . . . . . . . . . . . . . . . . . . . . 92 MegaModule Test Collar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Single MegaModule PMT I/O Hookup . . . . . . . . . . . . . . . . . . . . . . 95 PMT Test Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Multiple MegaModule PMT I/O Hookup . . . . . . . . . . . . . . . . . . . . . 97 PMT for Analog MegaModules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 In-System Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
9-1
Parallel Module Test of MegaModules
9.1

TI supplies you with libraries of complex ASIC macro functions, called MegaModules. Examples of MegaModules are RAMs and analog-to-digital converters. You can integrate MegaModules into your logic as easily as simple macros. After fabrication, all ASIC devices must be tested. Testing an embedded MegaModule with functional test vectors can be difcult or impossible. MegaModules can be deeply buried within logic. Many functional test vectors can be required for just one MegaModule access. MegaModules cannot be tested efciently this way. Parallel module test (PMT) is designed to test MegaModules. PMT directly accesses the MegaModules from device pins, bypassing the intermediate logic. PMT permits efcient communication with MegaModules (in parallel as opposed to serial). TI supplies test vectors for its MegaModules. The generic test access port (GTAP) provides the control for PMT (Figure 91). This chapter introduces a generic PMT implementation. A detailed presentation is in Part 4: Multiplexed Parallel Module Test Application Report. Analog MegaModules have some special PMT implementation considerations. These special case implementations of PMT are also presented in this chapter.
9-2
Figure 91.
GTAP-Controlled PMT Block Diagram

GTAP
TEST SCAN MCLK SCLK SCANIN
GTAP Controller (TP012 or TP0B2))
TWE Test Register (TP000s or TP0B0s)
SCANOUT
MegaModule
MegaModule
MegaModule
TEST_INPUT Bus
TEST_OUTPUT Bus
9-3
MegaModule Test Collar
9.2
MegaModule Test Collar

PMT requires that each MegaModule have a test collar. The test collar provides the TEST_INPUT bus interface and it is constructed from library components. Figure 92 shows a 2:1 multiplexer connected to each of the MegaModules inputs. These multiplexers select either the normal or test input signal into the MegaModule. The selection of normal or test mode is controlled by the PMT_IO test signal. Figure 93 shows a single MegaModule PMT implementation.
Figure 92.
MegaModule With a Test Collar

PMT_IO MegaModule
2:1 MUX S NORM_IN TEST_INPUT A B IN
OUT
NORM_OUT TEST_OUT
9-4
Single MegaModule PMT I/O Hookup
9.3
Single MegaModule PMT I/O Hookup

MegaModule TEST_INPUT connections are passed through an input buffer to the B terminal of the MegaModules collar input multiplexer. The input side of a bidirectional buffer can be used as a TEST_INPUT connection if the output portion of the buffer is disabled with the PMT_IO test signal. The interconnect loading of the TEST_INPUT connection can be isolated from the input buffer by an internal buffer as shown in Figure 93. The MegaModule outputs connect to the B terminal of a multiplexer prior to the output buffer. The multiplexer, prior to the output buffer, selects the core logic out or the TEST_OUTPUT, depending on the PMT_IO test signal. Because PMT passes the TEST_INPUT and TEST_OUTPUT signals through the I/O buffers, there are few restrictions on the buffer types that can be used. The GTAP controller inputs cannot be used for PMT TEST_INPUT or TEST_OUTPUT signals.
Figure 93.
Single MegaModule PMT

Normal_Z PMT_IO A B 2:1 MUX S Core Logic Input Buffer
PAD
A B
Y Output Buffer
PAD
2:1 MUX S A B Y MegaModule
TEST_OUTPUT
TEST_INPUT
9-5
PMT Test Bus
9.4
PMT Test Bus

If a device has multiple MegaModules, all TEST_INPUT signals can be bused together. Similarly, all TEST_OUTPUT signals can also be bused together. The devices TEST_INPUT or TEST_OUTPUT bus is as wide as the widest MegaModules TEST_INPUT or TEST_OUTPUT bus, respectively. When connecting two TEST_INPUT/TEST_OUTPUT buses, TI recommends that like signals be bused together. For example, RAM MegaModule TEST_INPUT signals are composed of address, control, and input data. The address signal of one RAM MegaModule should be connected to the address signals of another RAM MegaModule. The selection of the MegaModule under test is controlled by the MSEL test signal. Identical MegaModules should have their outputs hooked to the output bus in a unique order to ensure that the correct MegaModule is being addressed during PMT testing.
9-6
Multiple MegaModule PMT I/O Hookup
9.5

MegaModule TEST_INPUT bus connections are passed through an input buffer to the B terminal of the MegaModules collar input multiplexer. The input side of a bidirectional buffer can be used as a TEST_INPUT connection if the output portion of the buffer is disabled with the PMT_IO test signal. The interconnect loading of the TEST_INPUT connection can be isolated from the input buffer by an internal buffer, as shown in Figure 94. MegaModule outputs connect to the TEST_OUTPUT bus through an internal 3-state inverter. When the MegaModule is deselected, its internal 3-state buffer is placed in the high-impedance mode by MSEL. The polarity of the TEST_OUTPUT bus must be reestablished with an inverter, unless the output buffer is inverting. The multiplexer, prior to the output buffer, selects the core logic out or the TEST_OUTPUT bus depending on the PMT_IO test signal. A bus holder is required on the TEST_OUTPUT bus to keep it from oating during normal operation. Because this type of PMT passes the test buses through the I/O buffers, there are fewer restrictions on the buffer types that can be used with TEST_IN and TEST_OUT. The GTAP controller inputs cannot be used on either test bus.
9-7
Figure 94.
PMT Test Bus Hookup

Normal_Z A B 2:1 MUX S
PMT_IO
PAD Input Buffer
Core Logic
A B
Y Output Buffer
PAD
2:1 MUX TEST_INPUT BUS S A B Y MegaModule 1
MSEL1 TEST_OUTPUT BUS
2:1 MUX S A B Y MegaModule 2
MSEL2
Bus Holder
The following are PMT hookup rules. t A dedicated signal pin is required to initiate the test mode of the operation (TEST signal on the TP012 or TP0B2 GTAP). The TEST pin and the four GTAP controller pins (SCAN, SCANIN, MCLK, and SCLK) are not available for PMT data signals. The IOG12, SW010, and SW012 buffers cannot be used for PMT data signals. VREF pins and bias generator pins cannot be used for PMT data signals. The required maximum number of input test pins on any MegaModule must not exceed the number of available intput buffers on the package minus the ve GTAP pins. The required maximum number of output test pins on any MegaModule must not exceed the number of output buffers available in the package.
t t
9-8
PMT for Analog MegaModules
9.6

PMT implementation for analog MegaModules has one important variation. Analog signals connect directly to the analog MegaModule. Analog input signals pass through analog input macros and connect directly to the MegaModules analog inputs, bypassing the collar. MegaModule analog output signals connect directly to analog output macros. All control signals and nonanalog data signals are implemented using the standard PMT collar and hookup method.
9.6.1
PMT for a Single Analog-to-Digital (A/D) Converter

Figure 95 and Figure 96 show the PMT implementation for single A/D converter MegaModules. With the exception of the AIN signal, all MegaModule TEST_INPUT signal connections are passed through an input buffer to the B terminal of the MegaModules test collar input multiplexers. The MegaModules test collar multiplexers select the core logic in or the TEST_INPUT signal, depending on the PMT_IO test signal. The MegaModules output signals connect to the B terminal of the multiplexers prior to the output buffers. The multiplexers, prior to the output buffers, select the core logic out or the TEST_OUTPUT signal, depending on the PMT_IO test signal. The analog input signals (AIN) pass through analog input buffers (SW010 or IOG12) directly to the A/D MegaModule, bypassing the test collar. The analog input buffers TEST_ENABLE signals are passed through an input buffer to the B terminal of a test collar multiplexer at the analog input buffer. The analog input buffers test collar multiplexer selects the core logic in or the TEST_ENABLE signal, depending on the PMT_IO test signal.
9-9
Figure 95.
PMT for a Single Analog-to-Digital Converter

Core Logic
SW010 PAD S AC810 PAD IOG12 S A B S A B S A B S A B Y Y Y CLRZ S A B Y PAD Y S A B Y PAD AIN D7 A B Y PAD
PAD
D0
PAD
CONVZ SLEEP
PAD
PAD PMT_IO
Normal_Z
A B
9-10
Figure 96.
PMT for a Single Video Band Analog-to-Digital Converter

Core Logic
AC811/812
PAD
S A B S
TESTCLRZ TEST
PAD PAD PAD PAD IOG12 SW010
A B
AIN D7 TDI7
S A B Y PAD
S A B Y PAD
D0 PAD TDI0
S PAD A B Y
Normal_Z A B
PMT_IO
9-11
9.6.2
PMT for Multiple Analog-to-Digital Converters

If the device has multiple A/D converters, busing can be used. All TEST_ENABLE inputs can be bused together. All TEST_INPUT inputs can be bused together. All TEST_OUTPUT outputs can be bused together. A bus holder (PB110) is required for each bit of the TEST_OUTPUT bus. Identical MegaModules should have their outputs hooked to the TEST_OUTPUT bus in a unique order to ensure that the correct MegaModule is being addressed during PMT testing. Figure 97 and Figure 98 are examples of PMT for multiple analog-todigital converters.
9-12
Figure 97.
PMT for Multiple Analog-to-Digital Converters

Core Logic
AC810 S SW010 PAD IOG12 S A B PAD PAD PAD PAD A B PAD S S PAD A B Y A B CLRZ D0 S A Y S A B CONVZ SLEEP Normal_Z A B B Bus Holder AIN D7 Bus Holder Y S A B S A B S SLEEP CONVZ AC810 MSEL2 Bus HoldCLRZ D0 S A Y B PAD A B AIN D7
PAD
MSEL1
S A Y B PAD
PAD
9-13
Figure 98.
PMT for Multiple Video Band Analog-to-Digital Converters

Core Logic
AC811/812 PAD TEST A Y B S S PAD IOG12 SW010 IOG1 A B Y AIN MSEL1 D7 S A Y B S A Y B PAD TESTCLRZ
PAD
PAD PAD TDI7
PAD
D0 PAD TDI0 AC811/812 TEST S A B PAD S A Y B PAD PAD S PAD PMT_IO A Y B TDI0 IOG12 SW010 AIN D7 TDI7 D0 Normal A B Y TESTCLRZ
Bus Hold-
Bus Holder MSEL2
9-14
9.6.3
PMT for a Single Digital-to-Analog Converter

Figure 99 shows the PMT implementation for single D/A converter MegaModules. All MegaModule TEST_INPUT signal connections are passed through an input buffer to the B terminal of the MegaModules test collar multiplexers. The MegaModules test collar multiplexers select the core logic in or the TEST_INPUT signal, depending on the PMT_IO signal. With the exception of the AOUT signal, the MegaModules TEST_OUTPUT signals connect to the B terminal of the multiplexers prior to the output buffers. The multiplexers, prior to the output buffers, select the core logic out or the TEST_OUTPUT signal, depending on the PMT_IO signal. The analog output signal (AOUT) passes directly from the D/A MegaModule to an analog I/O buffer (IOG12). The analog input buffers TEST_ENABLE signals are passed through an input buffer to the B terminal of a test collar multiplexer at the analog input buffer. The analog input buffers test collar multiplexer selects the core logic in or the TEST_ENABLE signal, depending on the PMT_IO signal.
9-15
Figure 99.
PMT for a Single Video Band Digital-to-Analog Converter
DA811 S A PAD B S A B Y PAD AOUT IOG12 PAD
S A B Y Y D7
TDO7
PAD
S A B Y PAD
S A B Y D0
TDO0
PAD
Normal_Z A B
PMT_IO
9.6.4
PMT for Multiple Digital-to-Analog Converters

If the device has multiple D/A converters, busing can be used. All TEST_ENABLE inputs can be bused together. All TEST_INPUT inputs can be bused together. All TEST_OUTPUT outputs can be bused together. A bus holder (PB110) is required for each bit of the TEST_OUTPUT bus. Identical MegaModules should have their outputs hooked to the TEST_OUTPUT bus in a unique order to ensure that the correct MegaModule is being addressed during PMT testing. Figure 910 and Figure 911 are examples of PMT for multiple digital-toanalog converters.
9-16
Figure 910. PMT for Multiple Digital-to-Analog Converters

Core Logic DA810 S PAD A B S PAD AY B S AY B S PAD A B S PAD A B S AY B S A B S PAD AY B S AY B D7 TDO0 S AY B PMT_IO D0 A B TDO7 Bus Holder Y SLEEPZ MSEL2 Bus Holder CLRZ AOUT IOG12 PAD Y D0 DA810 Y D7 S A Y B PAD TDO7 SLEEPZ Y CLRZ AOUT IOG12 PAD
MSEL1
S A Y B PAD
TDO0
9-17
Figure 911. PMT for Multiple Video Band Digital-to-Analog Converters

Core Logic
S A Y B S PAD A Y B
DA811 AOUT MSEL1 S D7 TDO7 A B Y PAD IOG12 PAD
S PAD A B S PAD A Y B S A Y B D7 TDO7 Y D0 TDO0
S A Y B
PAD
DA811 AOUT MSEL2 Bus Holder IOG12 PAD
S A B PMT_IO Y D0 TDO0
Bus Holder
A B
9.6.5
PMT for a Single Differential Amplifier

Figure 912 shows the PMT implementation for a single differential amplier. The MegaModules analog input signals (INP and INM) pass directly through analog I/O (IOG12) buffers into the differential amplier. The MegaModules analog output signal (AOUT) passes directly from the differential amplier to an analog I/O (IOG12) buffer.
9-18
All remaining MegaModule TEST_INPUT signal connections are passed through an input buffer to the B terminal of the MegaModules test collar multiplexers. The MegaModules test collar multiplexers select the core logic in or the TEST_INPUT signals, depending on the PMT_IO test signal.
Figure 912. PMT for a Single Differential Amplier

Core Logic
S A Y B S PAD A Y B
S A Y B
PAD
Bus Holder
A B
9-19
9.6.6
PMT for Multiple Differential Amplifiers

If the device has multiple differential ampliers, busing can be used. All TEST_ENABLE inputs can be bused together. All TEST_INPUT inputs can be bused together. Figure 913 is an example of PMT for multiple differential ampliers.
Figure 913. PMT for Multiple Differential Ampliers

Core Logic
S A Y B S PAD A Y B
S A Y B
PAD
Bus Holder
A B
9-20
In-System Use
9.7
In-System Use
The multiplexed PMT implementation passes all MegaModule test signals through I/O buffers. At-speed operation of these MegaModules through direct access is limited only by the MegaModules capabilities and the performance of the hookup. For this reason, multiplexed PMT ports can be appropriate for in-system functions such as preload or status checks.
9-21
In-System Use
9-22
Chapter 10
Parametric Measurements
This chapter presents dc parametric measurements. Parametric measurements validate conformance to the electrical data sheet.
Topic
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Output Voltage Levels (DC_PARA TDL Type) . . . . . . . . . . . . . . . 1010 Three-State High-Impedance Measurements (DC_PARA TDL Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 Input Current Measurements (DC_PARA TDL Type) . . . . . . . . . 1012 Quiescent Drain Supply Current (IDDQ TDL Type) . . . . . . . . . . 1013
10-1
Overview
10.1
Overview
Parametric testing ensures conformance to the electrical data sheet. It requires functional test patterns to be developed for parametric testing. Parametric test patterns must be simulated to check for accuracy and for circuit hazards such as bus contention. If the circuit has IEEE Standard 1149.1 boundary-scan architecture, the boundary-scan feature should be used to facilitate input threshold, input leakage current, and output voltage level measurements. Most parametric testing pattern sets are assigned the DC_PARA TDL type. The DC_PARA pattern set should provide 100 percent toggle of all I/Os. This means that it drives all outputs to a logic low and a logic high. Bidirectional and 3-state outputs are driven to the high-impedance state. It also drives all inputs to a logic low and a logic high. Parametric testing is completed with the dc current leakage pattern set that is assigned the DC_PARA TDL type and the optional input threshold voltage pattern set that is assigned the VIH_VIL TDL type. The table below gives the required TDL states for the various signal types.
10-2
Overview
Table 101. Toggle States

Signal Type Input with no pullup/pulldown Input with pullup Input with pulldown Negative (101) clocks Positive (010) clocks Push-pull output including ECL and PECL 3-state output with no pullup/pulldown 3-state output with pullup 3-state output with pulldown N-channel open drain output with no pullup/pulldown N-channel open drain with pullup N-channel open drain, BTL/CTL/GTL Bidi (3-state output) with no pullup/pulldown Bidi (3-state output) with pullup Bidi (3-state output) with pulldown Bidi (N-channel open drain) with no pullup/pulldown Bidi (N-channel open drain) with pullup Bidi (BTL/CTL/GTL) Bidi (CML/ECL/PECL) with no pullup/pulldown Required TDL States {L H} {L H | L T} {L H | F H} {C | H} {C | L} {0 1N1} {0 1 Z} {0 1 Z | 0 1 P} {0 1 Z | 0 1 N} {0 Z} {0 Z | 0 P} {01 | 0P} {0 1 L H} { 0 1 L H | 0 1 L T} {0 1 L H | 0 1 F H} {0 L H} {0 L H | 0 L T} {0 L H} {0 1 H L | N1HL}
10-3
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
10.2 Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
VIH_VIL TDLs are optional. Circuits that implement boundary scan can be used to measure VIH and VIL. The SAMPLE/PRELOAD and EXTEST instructions can be used to capture the input logic level. The capture is scanned out for comparison to expected values. Three test patterns are required. They are a safe circuit initialization pattern, an all-inputs-at-VIL pattern (inputs include bidirectionals), and an allinputs-at-VIH pattern. For more information, see Chapter 13, IEEE Standard 1149.1-Based dc Parametric Testing. Circuits that are not IEEE Standard 1149.1-compliant need threshold circuitry to be added. Figure 101 shows the recommended circuitry commonly referred to as a clocked NAND tree. This approach requires the addition of a 2-input NAND gate to every input pin as well as CLK and VIH_VIL OUT pins. The NAND tree provides a purely combinatorial path from all inputs to a single VIH_VIL OUT through a ip-op. Do not use a bidirectional buffer for the VIH_VIL OUT. The rst NAND gate in the tree has one input connected to the high terminal of a tie-off cell. The ip-op at the end of the NAND tree serves to break up a positive feedback loop between an input buffer and the NAND tree output. All the input buffers are driven to VIHmin and VILmax during VIH/VIL testing of the silicon. When the NAND tree output switches, it causes some power bus noise and some input threshold voltage shifting. Sometimes this threshold shifting is sufcient to cause an input buffer to output the opposite state. The input buffer may cause the NAND tree to switch again, completing the positive feedback loop. The positivw feedback loop can also exist between asynchronous inputs and outputs. for this reason, TI recommends that you exclude clocks, resets, presets, and other asynchronous inputs from the NAND-tree circuitry.
10-4
Figure 101. Clocked NAND Tree Circuit (Dedicated Control Pins)

Hi Tie-Off Lo To Functional Logic
IN1
IN2
To Functional Logic
IN3
To Functional Logic
IN4
To Functional Logic
INM-1
INM DTN12 D Q CLK (Dedicated)
To Functional Logic To Functional Logic To Functional Logic PAD (Dedicated) VIH_VIL_TEST_OUT
10-5
The test patterns are specic. The rst pattern consists of VIH threshold voltages on all inputs. The threshold voltages are then applied in accordance with Table 102. A circuit containing M number of input pins needs 2(M+1) test patterns to test both VIH and VIL thresholds.
Table 102. VIL/VIH Test Patterns (Dedicated Control Pins)

Inputs CLK = = . . . 1 = = = = . . . = = IN1 1 0 . . . 0 0 0 0 0 . . . 0 1 IN2 1 1 . . . 0 0 0 0 0 . . . 1 1 ... ... ... ... ... ... ... ... ... ... INM-1 1 1 . . . 1 0 0 0 1 . . . 1 1 INM 1 1 . . . 1 1 0 1 1 . . . 1 1 VIH_VIL OUT M=EVEN 1 0 . . . 1 0 1 0 1 . . . 0 1 M=ODD 0 1 . . . 1 0 1 0 1 . . . 1 0
On designs that have a bidirectional bus, running the normal NAND tree patterns may cause bus conict conditions. This problem can be resolved by placing the TTL or CMOS bidirectional drivers in the high-impedance mode with a HI-Z signal. For ECL bidirectional pins, the Hi-Z signal puts the output driver in the cutoff mode. See Figure 102 for an example. For designs that do not have extra pins available for CLK and VIH_VIL OUT, these signals can be multiplexed with other signal pins. See Figure 103 for an example. The test patterns for the example in Figure 103 must be
10-6
modied and are shown in Table 103. Test pattern generation is simplied if CLK1 is placed on the input whose NAND gate is connected to the tie-off cell. The placement of CLK2 is arbitrary.
Figure 102. CMOS ASIC NAND Tree Congurations

Input Types PAD From NAND Tree or high output of a tie-off macro(TO010) To Functional Logic
PAD VREF PAD PAD
To Functional Logic
To Functional Logic
From Functional Logic PAD From Functional Logic To Functional Logic
From Functional Logic PAD VREF To Functional Logic From Functional Logic
HI-Z (From the GTAP)
To NAND Tree
10-7
Figure 103. Clocked NAND Tree Circuit (Shared Control Pins)

Hi Tie-Off Lo IN1 (Shared CLK1) To Functional Logic MU111 S A B IN2 Y To Functional Logic
IN3
To Functional Logic
IN4
To Functional Logic
INM-1
INM (Shared CLK2) VIL_VIH Clock Select (GTAP)
VIL_VIH Enable (GTAP) From Functional Logic From Functional Logic
To Functional Logic MU111 S A B Y DTN12 D Q Y MU111 S A B Y Shared PAD VIH_VIL_Test_OUT To Functional Logic MU111 S A B 10-8 Design for Testability
Table 103. VIH_VIL Test Patterns (Shared Control Pins)

Inputs VIL_VIH Clock Select L L L . . . L L H . . . H H H CLK1 IN1 = = = . . . = = L . . . L L H CLK2 INM H H H . . . H L = . . . = = = VIH_VIL OUT
IN2 H L L . . . L L L . . . L H H
IN3 H H L . . . L L L . . . H H H
... ... ... ...
INM-1 H H H . . .
M=EVEN 0 1 0 . . . 0 1 0 . . . 0 1 0
M=ODD 1 0 1 . . . 0 1 0 . . . 1 0 1
... ... ...
L L H . . .
... ... ...
H H H
10-9
Output Voltage Levels (DC_PARA TDL Type)
10.3
Output Voltage Levels (DC_PARA TDL Type)

Circuits that implement boundary scan can be used to test output logic levels. The IEEE Standard 1149.1 instructions used are SAMPLE/PRELOAD and EXTEST. Three test patterns are required. They are a safe circuit initialization pattern, an outputs-at-VOL pattern, and an outputs-at-VOH pattern (see Chapter 13, IEEE Standard 1149.1-Based dc Parametric Testing ). If boundary-scan architecture is not used, the VOL/VOH measurement is made from a dc parametric pattern set that drives all outputs to a logic low and a logic high. Be sure to simulate these parametric patterns to verify that all outputs are driven high and low and to avoid circuit hazards such as bus contention.
10-10
Three-State High-Impedance Measurements (DC_PARA TDL Type)
10.4
Three-State High-Impedance Measurements (DC_PARA TDL Type)

Circuits that implement boundary-scan can be used to test 3-state highimpedance outputs. The IEEE Standard 1149.1 instructions used are SAMPLE/PRELOAD and EXTEST. Two test patterns are required. They are a safe circuit initialization pattern and an all-three-state-outputs-disabled pattern (see Chapter 13, IEEE Standard 1149.1-Based dc Parametric Testing ). The same safe circuit initialization pattern set can be used for all input and output parametric measurements using boundary scan. If boundary scan is not used, the high-impedance measurement is made from a functional pattern set that disables all outputs. Be sure to simulate these patterns to verify that all outputs are disabled and to avoid circuit hazards such as bus contention. When pullups or pulldowns are used on your outputs, you will need to supply test patterns to both disable and enable them while the output is highimpedance. Leakage measurements are made when the pullup or pulldown is disabled. DC through current measurements are made when the pullup or pulldown is enabled.
10-11
Input Current Measurements (DC_PARA TDL Type)
10.5
Input Current Measurements (DC_PARA TDL Type)

Circuits that implement boundary scan can be used to test input current. The pattern set must force all inputs to logic 1 and logic 0. Be sure to simulate this pattern set to verify that all inputs are exercised high and low, and to avoid circuit hazards such as bus contention. If boundary scan is not used, the input current measurements are made from a functional pattern set. The pattern set must force all inputs to logic 1 and logic 0. Be sure to simulate this pattern set to verify that all inputs are exercised high and low, and to avoid circuit hazards such as bus contention. When pullups or pulldowns are used on your inputs, you will need to supply test patterns to both disable and enable them. Leakage measurements are made when the pullup or pulldown is disabled. DC through current measurements are made when the pullup or pulldown is disabled.
10-12
Quiescent Drain Supply Current (IDDQ TDL Type)
10.6

The classical stuck-at fault model has been quite successful in detecting shorts and opens. It has been pointed out that the stuck-at model does not represent some types of CMOS faults, most notably threshold drifts and surface contamination. Quiescent drain supply current (IDDQ) testing has proved useful in supplementing stuck-at testing. Excessive CMOS leakage indicates either an existing logical fault or a marginal device that is likely to fail. Test conditions for IDDQ must turn off all circuits that produce dc current in the static state and are assigned the IDDQ TDL type. The circuit design and test pattern must eliminate the following sources of dc current.
10.6.1 Initialize the ASIC to a Sustainable Logic State

For IDDQ testing, the tester pauses at the designated test pattern and measures the power pin current. The pause can last several hundred milliseconds for a production test to several minutes during a debug process. For this reason, the designated IDDQ test vector must permit an indenite pause without damage to the device and maintain the ASIC devices logic initialization.
10.6.2 Eliminate dc Through-Current That Interferes With IDDQ Testing

Disabling the dc through current makes it possible to detect abnormally high current drawn by CMOS faults. Observe the following guidelines to disable dc through-current: t Some macros have a testability pin to disable the dc through-current. Pullups, pulldowns, LVDS buffers, bias generators,and oscillators have the PWRDN pin. Drive the PWRDN signal to disable the dc through current for IDDQ testing. Some macros, such as ECL I/O buffers, cannot disable their dc throughcurrent, but are isolated by a power pin independent of the core logics power pin. This allows IDDQ measurements to be made on the core logic. Floating internal nodes, oating I/O inputs, and internal bus contention cause dc through-current and must be avoided.
10-13
Non-terminated bidirectional buffers (e.g. TTL, PCI, CMOS) must not be masked during an IDDQ test. The tester is disconnected from the pin when an output TDL state (including masks) is specied at an IDDQ test pattern. When the is physically in the high-impedance state, the pin oats and the input buffer draws dc through current.
10.6.3 Identify the IDDQ Test Locations in the TDL

Identify test locations by placing an ASIC_TEST IDDQ statement after each IDDQ test vector. Identify any TDL pattern set containing an IDDQ test with the IDDQ pattern set type.
10-14
Chapter 11
Automatic Test Pattern Generation
Automatic test pattern generation (ATPG) techniques are increasingly being used to create high-fault-coverage test patterns.
Topic
Page
Introduction to Automatic Test Pattern Generation . . . . . . . . . . 112 Path Sensitization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Full-Scan Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Partial-Scan Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Testing and Debugging Considerations . . . . . . . . . . . . . . . . . . . 118 Common ATPG Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
11-1
Introduction to Automatic Test Pattern Generation
11.1

This chapter discusses an increasingly popular test methodology called Automatic Test Pattern Generation (ATPG). It is the intent of this discussion to provide a practical overview of todays circuit environment. Three ATPG approaches for sequential circuits (full scan, partial scan, and nonscan) are discussed. Important testing and debugging implications of using the ATPG approach are also presented. The circuit design environment has evolved dramatically over the past few years, providing computing power and software to aid in almost every phase of the design process. Schematic capture, simulation, test extraction, and layout represent the essential software programs for a complete design system. Semiconductor process technology has kept pace, permitting implementation of extremely complex logic systems on a single chip. This has resulted in an increase in the difculty of chip testing. Much of the added testing difculty is due to higher gate density. Packing more logic onto one circuit greatly increases the gate-to-I/O ratio and decreases the accessibility of that logic. Allowing a reasonable number of I/ O signals to be dedicated for testing can ease the testing process considerably. These test signals can be used to add controllability or observability to the circuit in a variety of ways. For many designs, setting aside the desired number of dedicated test pins is not possible due to pinout constraints. In spite of these obstacles, a complete and efcient test program must be generated. Most often, designers specify a functional simulation, and the test program is automatically extracted from the functional simulation results. Fault grading tools allow you to grade the test program by calculating a fault coverage percentage. You can then add to the test program to increase the fault coverage to an acceptable level. An integrated design environment begins with circuit design entry (as shown in Figure 111) and proceeds with electrical rules checking and simulation. During the design process, it is often necessary to modify the circuit design to correct errors and include enhancements. Once the design has been stabilized, the process of test generation must be accomplished. It is important for testing considerations to be addressed early in the design phase so that test generation becomes a task of implementing the predened testing plan. You should decide on a target percentage for fault coverage as soon as possible, because a high target percentage may require the adoption of certain circuit design methods.
11-2
Figure 111. Typical Design Flow

Circuit Design Entry
Electrical Rules Checking
Simulation
Test Generation
Fault Simulation
Layout
Fabrication
It is possible that, during the ATPG phase, the need for additional test points to achieve the target percentage becomes apparent. (See Chapter , Ad Hoc Testability Practices, and Chapter 6, Structured Testability Practices, for approaches to designing for testability.) If this is the case, the netlist must be modied and resimulated. It is important, in terms of efciency and effectiveness, that the ATPG software be integrated into the design environment. ATPG tools require the circuit description at gate level, all circuit timing information, any pregenerated functional test patterns and any userspecied parameters. The software uses this information to follow a ow similar to that shown in Figure 112.
11-3
Figure 112. Typical ATPG Flow

Check Circuit for Adherence to Any Scan Design Rules Imposed by ATPG Tool
Fault Grade Pregenerated Functional Test Patterns
Select an Undetected Fault
Generate Test Patterns to Detect Fault
Fault Simulation
Eliminate Additionally Detected Faults from Consideration
In this ow, the rst step is to check the circuit for adherence to any designfor-testability rules imposed by the ATPG tool. Fault simulation is then performed with the optional user-generated functional patterns. All faults detected by these patterns are tagged and eliminated from the ATPG process. Any remaining undetected faults are passed to the ATPG algorithm where tests are generated for these faults. Fault simulation is rerun to check the effects of generating the input patterns necessary to check the faults under consideration, and to identify any previously undetected faults that may have been detected by this pattern. Iteration of this process continues until the desired fault coverage is achieved. Fault simulation, as an intermediate step, checks the targeted fault as well as all other undetected faults, thus reducing the number of ATPG iterations.
11-4
Path Sensitization
11.2
Path Sensitization
Test pattern generation programs use a variety of methods to achieve essentially the same test generation capability. The denition of a good test for a fault is an input combination that produces an incorrect output when the fault under consideration is present in the circuit. Thus, the presence of the fault can be observed at the outputs. Path sensitization is one such method of generating a test for a fault. The general procedure is: 1) Select a fault (such as node stuck-at-one). 2) Assign the faulty wire a value opposite to the fault condition (such as ode stuck-at-zero). This allows sensitization for the expected signal. 3) Choose a path from the fault to a circuit output. 4) Sensitize this path by assigning logic values to gate inputs along the path such that the signal is passed to the circuit output. 5) Execute the test to detect the signal by determining the network inputs that produce the desired values on gate inputs along the sensitized path. Some variations of this path sensitization method are used in commercial ATPG programs. All are effective methods for generating tests for faults in most combinatorial circuitry (without reconvergent fanout). However, few tools are effective for ATPG of sequential circuits. This has led to the development of a set of design rules to simplify test generation in sequential circuits. Level-sensitive scan design (LSSD) is one such design methodology that imposes design restrictions that allow the circuit to be forced into a test mode in which the ATPG methods above can be used to generate tests for faults. Another approach is random vector generation. This method has straightforward applications for some combinatorial circuitry but has not been extended effectively to sequential circuitry. Certain combinatorial circuits lend themselves nicely to this approach while others do not. Current ATPG tools are unable to achieve good results on complex designs without DFT features. Most of the commercial, general-purpose ATPG tools use scan techniques. Scan techniques fall into two broad categories: full scan and partial scan.
11-5
Full-Scan Designs
11.3
Full-Scan Designs
By far the most popular ATPG methodology uses a full-scan approach. This calls for rigid design rules to be followed that allow the circuit to be placed in a test mode in which all logic storage elements are connected as shift registers, breaking up the combinatorial circuitry. When this method is used, the circuit is placed in the test mode and a test pattern is shifted in, thereby dening all internal storage states. The circuit is then taken out of the test mode and operated for a known number of system clock cycles. The circuit is again placed in the test mode and the internal storage states are shifted out for comparison to an ATPG-generated signature. It is argued that full-scan designs are both easily tested and more likely to be correct the rst time. Some ATPG tools work only on full-scan designs.
11-6
Partial-Scan Designs
11.4
Partial-Scan Designs
Partial scan is a technique where only some of the logic storage elements (those in the most difcult to test areas) are made scannable. This approach has fewer design restrictions. Some ATPG tools support partial scan and they can also be used on full-scan designs. Partial-scan ATPG tools can help you determine where scan elements are required. Because such modications are not acceptable in every design, it is essential that these tools are used by you, the designer, and not by the ASIC vendor.
11-7
Testing and Debugging Considerations
11.5
Testing and Debugging Considerations

Several types of problems can cause a semiconductor circuit to fail. These include logic design and layout errors as well as mask and wafer fabrication defects. When performing test pattern generation, you must rst determine the strategy of testing for all possible problems. It is very important to remember that ATPG patterns should only be used to test for random faults relating to the manufacturing process. Although ATPG patterns may be an efcient tool for indicating the presence of a defect, they generally provide little information relative to the nature and location of the defect. Consequently, ATPG patterns alone are seldom useful if you are involved in the debugging process. Most ATPG packages provide a crossreference listing that shows which faults are detected in each vector. This information may be of little use, however, because many faults often are detected in each vector and isolating the specic fault may be impossible. A straightforward method of avoiding debugging and pattern-length problems is to begin the test program with a thorough functional test. Most ATPG systems accept manually generated pattern inputs. In this way, a fault grade of the functional patterns can be done before proceeding with automatic test pattern generation. ATPG patterns can then be added to increase the fault coverage to an acceptable level.
11-8
Common ATPG Constraints
11.6
Common ATPG Constraints

The following constraints are common to most ATPG tools. t All clocks must be controlled externally (no gated or logic-generated clocks). No combinatorial-feedback loops No asynchronous timing Scan-compatible sequential elements are used.
t t t
11-9
Summary
11.7
Summary
When embarking on an ATPG methodology, you must consider many aspects of the total design environment, such as: t t t Integration of the ATPG tool into the design environment Adherence to circuit design rules pertaining to the ATPG tool Maintaining a functional test generation plan for debugging and critical path testing
Consideration of all these items before adopting any particular ATPG implementation should minimize any problems that might occur later.
11-10
Chapter 12
Test Pattern Generation
This chapter discusses test pattern generation. Test patterns must operate on automated test equipment (ATE).
Topic
Page
Introduction to Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Test Pattern Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 TDL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
12-1
Introduction to Testing
12.1
A logic truth table is used to verify the logic behavior of an integrated circuit and thereby check for the presence of manufacturing defects. This truth table is referred to as a test pattern, and a test vector is dened as a line in the truth table. Logic simulators are used to explore the Boolean and timing responses of a circuit by applying a user-dened set of input stimuli. If you have done a good job, the set of input stimuli can be used to control and observe the behavior of all nodes in the circuit. Automated test equipment (ATE) used to screen integrated circuits does not have the same features as the logic simulator. Access to internal nodes is not possible, and propagation delays need to be measured from inputs to outputs of the device. Testing a chip is performed by applying binary patterns (input vectors) to stimulate the logic inputs and then comparing the output response to the values predicted by simulation. In general, the phase relationship and sequence of input stimuli applied to an integrated circuit to test the functionality and performance of the device are somewhat different than the simulation patterns used to verify the logic design. These differences are due mostly to the inherent characteristics of testing equipment used to evaluate logic devices. For this reason, test patterns must be simulated using conditions consistent with ATE capabilities. ATEs are synchronous systems. Described simply, an ATE operates in a periodic fashion. Input signals change at designated points within the test period. Output signals are strobed at designated points in the period. Figure 0-1 is a diagram of the phase relationship of input and output data with respect to the test period for a sample test pattern. The TI test utilities assume a data input, a clock, then a strobe for the test signal sequence. All test period timing is referenced to the beginning of the period (to).
12-2
Figure 121. Synchronous Pattern for Use During Functional Test

to Data Input to to to to to
Primary Clock
Output
Strobe Test Period
Each vector applied to the device under test (DUT) is stored in the ATE pattern memory. If the number of test vectors exceeds the ATE pattern memory capacity, two or more memory reloads from disk would be required, greatly increasing the test time. Minimizing the number of test vectors is desirable not only to reduce the test run time, but also to reduce simulation and fault grading times. The number of primary clocks and strobe times that can be applied to the DUT is a function of the number of timing generators available in the ATE. By programming these timing generators, you can select multiple clocks or strobe timing relationships with respect to the test period. Figure 122 shows a simplied block diagram of an ATE.
12-3
Figure 122. ATE Block Diagram

Data Control Structures
Logic Control
IN5
IN4
IN3
IN2
IN1
CLK2
Input Timing Data Input and Clock Pattern Data CC OO Output LLIIIIIUU KKNNNNNTT Pattern Data 121234512 SETR P := CCHHLLHAA; SETR P := CCLHLHL11; Strobe SETR P := CCHLHHH1Z; Enable SETR P := CCHHLLH10; Timing Test Patterns (TDL Data)
OUT1
OUT2
DUT
Test Data Compared Pass -1
The minimum duration of the test period varies from system to system and determines the frequency range at which a device can be tested. Typically, however, there are other constraints that require the testing frequency to be much lower than the capability of the tester. A major factor inuencing testing is called period slip. In some cases, the exact time in which the output signal becomes valid is not critical to the system operation. It is very important to the ATE. Testing systems compare the output states to the expected responses on a period-by-period basis by activating strobe signals (Figure 121 and Figure 122) which, in turn, enable a set of comparators connected to the output channels. If output responses slip from one test period to the next, the device fails even though it may be fully functional at the system level (see Figure 123). In order to minimize this problem, functionality of devices is veried at a relatively low
12-4
CLK1
frequency. (High-frequency testingcalled at-speed can be performed if care is taken to mask the strobe for the slipped periods.) The placement of output strobes is described in a later section.
Figure 123. Tester Period Slip

Based on Expecting a High Logic Output Pass Output Signal at Min Delay
Output Signal at Max Delay
Fail
Strobe Test Period N Test Period N+1
Properly constructed test patterns should contain input signals and expected output responses as observed during simulation. For any circuit containing sequential logic, test patterns consist of two parts: 1) An initialization step to set external and internal nodes, including memory elements, from an unknown state to a known state by exercising the device clock, data, reset, or scan pins. 2) The actual test vectors used to stimulate input and output pins. If a device contains internal 3-state buses, you must arrange the enable logic so that the buses are always driven (not left in the high-impedance state). A bus holder cell prevents bus oating by maintaining the last state on the bus in a way similar to a latch. Furthermore, internal bus contention must be avoided to ensure the device initialization is not upset by noise resulting from the contention.
12-5
Test Pattern Creation
12.2

The TI ATE program generation software uses Test Description Language (TDL) as an input. The TDL le contains a set of test vectors and timing information. Test vectors dene input signals and expected output signals for a test period of xed duration. The entire test pattern denes a set of sequential test periods that perform a logic verication test on the device being tested. Before TDL can be generated, the following concepts and limitations must be understood and applied when setting up the simulation runs for the functional and scan tests. These concepts include input delay groups, clocks, and output strobe groups.
12.2.1 Input Delay Group

An input delay group is a set of input signals that transition at the same time. Every input or bidirectional signal must be assigned to one, and only one, input delay group. Figure 124 illustrates the relationship between the input delay groups and the test period.
12-6
Figure 124. Input Delay Groups

Test Period Input Delay Group 1 Minimum Delay
Input Delay Group 2
Input Delay Group 3
Input Delay Group 4
Input Delay Group N
12.2.2 TDL Clocks

Input signals dened as clocks must be assigned to an input delay group programmed as a return-to-zero or a return-to-one signal. A clock signal is a complete pulse within a test period. Figure 125 shows two examples of input clocks along with the corresponding TDL clock statements (CLOCK). Each clock signal can be programmed to occur zero or one time per test period.
Maximum Delay
A delay group can be assigned either a return-to-complement (clock) or a nonreturn-to-complement signal. Input signals other than clocks can have either zero or one transition within a test period. All transitions of the input delay groups must occur no earlier than the specied minimum or later than the specied maximum delay time after the beginning of a test period. The dened timing for input delay groups may not change within any particular test pattern set. The input signal capabilities for each tester are specied in the design manual for the gate array family.
12-7
Figure 125. Denition of TDL Clocks

to Active State Test Period to Rest State Test Period to
(HOLD0) (HOLD1) Delay Return-to-Zero (10 ns) (11.5 ns) Width
Leading Edge Delay Trailing Edge Delay CLOCK VAR = CLK1, PATTERN = 010, HOLD0 = 10 NS, HOLD1 = 11.5 NS; to Active State Test Period (HOLD1) (HOLD0) Delay Return-to-One (10 ns) (11.5 ns) Width to Rest State Test Period
Leading Edge Delay Trailing Edge Delay CLOCK VAR = CLK2, PATTERN = 101, HOLD0 = 11.5 NS, HOLD1 = 10 NS;
Pattern 010 denes a return-to-zero pulse. Pattern 101 denes a return-toone pulse. HOLD0 is the time the signal is held low and HOLD1 is the time the signal is held high. Figure 126 depicts the minimum clock width.
12-8
Figure 126. Minimum Clock Width

(a) Within a Test Period to Test Period to Test Period to
Minimum Clock Pulse Width
(b) Between Test Periods to Test Period to Test Period to
Minimum Clock Pulse Width
12.2.3 Output Strobe Groups

The outputs of the device are sampled at a specied time into the test period. An output strobe group is a set of outputs that are sampled at the same time. Figure 127 shows the restrictions on the output strobe timing. Output transitions must not occur in this window. The dened delay for an output strobe group may not change within a test pattern set. Strobe capabilities for each tester are specied in the design manual for the gate array family.
12-9
Figure 127. TDL Output Strobe Placement

to Test Period Strobe Window Output Max Output Delay Min Output Delay to
Strobe Offset
Strobe
12.2.4 Special Test Precautions

The product-specic design manuals present the rules to ensure proper testing. These include: t Rules to prevent contention between TTL/CMOS bidirectional buffers and the tester Rules to prevent sampling a 3-state or bidirectional buffer before it has had time to settle
12.2.5 ATE Loads

ATE loads must be applied to the output during simulation. Figure 128 illustrates ATE loads to be used.
12-10
Figure 128. Simulation Tester Loads

CMOS, PCI, etc From Output under Test Test Point GTL, PECL, etc From Output under Test 50 W Test Point
C = 45 pF for V-Series = 75 pF for T3320/T3340
Termination Voltage
12.2.6 ATE Input Slews

ATE slews must be applied to the input during simulation.
12.2.7 Performance Test Procedures

In addition to the standard low-speed functional testing, TDL can be used to make dynamic tests.
At-Speed Testing
The capabilities for each tester are specied in the design manual for the gate array family.
Setup and Hold Testing

Setup and hold verication is performed by proper selection of input signal delays in FUNC_AC, SCAN_AC, and BIST_AC TDL pattern types.
Pin-to-Pin Testing
Critical timing can be veried by making pin-to-pin propagation delay measurements. Keywords can be inserted into the TDL ASIC_TEST statement to dene a test to be included in the test program. Propagation delay measurements have the following capabilities: t Delay from one package pin to another (input-to-output or output-tooutput). Pass or fail using max values Delay from a clock edge to an output. Pass or fail using max values
12-11
Guard-banding the limits are automatically done at test to account for tester accuracy.
Minimum delays are not generally tested. Minimum testing is done on a special request basis.
12-12
TDL Overview
12.3
TDL Overview
All test patterns must be cycle-based with synchronous clocks.
Cycle-based means that:

t t The test vector timing is based on a xed-length repeating cycle. Input changes and output strobes occur at the same offset in each cycle.
Synchronous clocks means that all clock periods are multiples of the cycle time. Example 0-1 shows three common TDL statements.
Example 121. Three TDL Statements

TDL_VERSION:= ASIC_TDL_91 ASIC_TITLE = LIBRARY_TYPE CUSTOMER TI_PART_NUMBER PATTERN_SET_NAME PATTERN_SET_TYPE REVISION DATE 4.3; = TsC4000, = Ardee, = f123456, = tdl0, = FUNC, iddq, = 1.00, = 9/27/96;
CONNECT P, VAR=(IN[1],CLK,OUT[1]), BIDI[1]), DEFPIN=(IN2, IN, INOUT); PERIOD = 200NS; DELAY VAR = (IN[1], BIDI[1], OFFSET = 20NS; CLOCK VAR=CLK, HOLD0 = 35NS, HOLD1 = 25NS, PATTERN= 010; STROBE VAR = (OUT[1], BIDI[1]), OFFSET = 190NS; ASIC_BIDI_CTRL = enables_net, TYPE = CONTROL, POLARITY=H VAR = (BIDI[1]); THRU_CURRENT = NET enablez_net, OFF_WHEN=H VAR=(IN[1]); THRU_CURRENT = DATA=UNKNOWN, VAR= (IN[1]); (*$ end of header and timing section, start of pattern data section *) SETR P:=TLC0M; (*$ vector 0 *) SETR P:=THC10; (*$ vector 1 *) THRU_CURRENT = DATA = OFF, VAR = (IN[1]); ASIC_TEST = IDDQ; ASIC_TEST = PROP FROM = CLK, CLKEDGE = LEADING, TO = OUT[1], MAX = 50NS, REJECT = NO; END;
TDL_VERSION refers to the TDL specication version you have used. The PATTERN_SET_NAME must begin with an alphabetic character and not exceed eight characters in length.
12-13
TDL Overview
The PATTERN_SET_TYPE eld identies the TDLs function(s). The CONNECT statement lists all the signal names and the order in which they appear in the SETR statements. The PERIOD, DELAY, CLOCK, and STROBE statements provide the timing data. The SETR statement denes the logic state data. For logic state denitions, refer to Table 0-1. The ASIC_BIDI_CTRL statement documents the bidirectional control signal information for the TDL2simulator tools. This statement causes the TDL2simulator tools to automatically trace on the internal net that determines the direction for the named bidirectional I/O signals. The THRU_CURRENT statement documents whether the bond pad dc through current for an I/O is on, off, or unknown. This statement is required for DC_PARA and IDDQ TDLs and is commonly associated with I/Os that are connected to pullup or pulldown macros. The IDDQ statement species the test vector used to measure the quiescent power pin current. The PROP statement measures the time difference between a transition on the FROM signal to a transition on the TO signal. Place an ASIC_TEST statement after the SETR statement that facilitates the test. Figure 129 shows the corresponding waveform representation of the sample TDL.
12-14
TDL Overview
Figure 129. Waveform Representation of the Sample TDL

t0 t0 Test Period 1 = 200 ns H t0
Offset = 20 ns IN[1] L Offset = 35 ns CLK Pulse Width = 25 ns OUT[1] 0
OUT[1] STROBE Strobe Offset = 190 ns
Table 121. Commonly Used TDL Logic State Characters

Character L H C Y 0 1 Z M Direction Input Input Input Input Output Output Output Outout Logic State (Tester Perspective) Drive low Drive high Drive pulse Dont care Expect low Expect high Expect high-impedance state Mask (dont care)
12.3.1 TDL Example

A portion of a TDL le containing one initialization vector and four test vectors is shown in Example 122. The patterns are dened by the character strings
12-15
TDL Overview
enclosed in single quotes. There are seven inputs (CLOCK, IN1-1N6) and four outputs (OUT1-OUT4).
Example 122. TDL File Example

(*$ (*$ (*$ (*$ (*$ SETR SETR SETR SETR SETR C *) L OOOO*) O IIIIII UUUU*) C NNNNNN TTTT*) K 123456 1234*) P:=TL_YYYYYY_MMMM; P:=TC_HHHLLL_MMMM; P:=TC_HLHLHH_1100; P:=TC_LHLHHL_1Z00; P:=TC_LHLHHL_1011;
Figure 0-10 shows the relationship between the set of test vectors and the corresponding logic waveforms.
12-16
TDL Overview
Figure 1210. Relationship Between Test Vectors and Corresponding Logic Waveforms
CLOCK IN1 IN2 IN3 IN4 IN5 IN6 OUT1 OUT2 OUT3 OUT4
SETR P:=TL_Y Y Y Y Y Y_M M M M: SETR P:=TC_H H H L L L_M M M M: SETR P:=TC_H L H L H H_1 1 0 0: SETR P:=TC_L L L H H L_1 Z 0 0: SETR P:=TC_L H H L L H_1 0 1 1:
12.3.2 Specifying Propagation Delay Measurements in TDL

Keywords can be inserted into the ASIC_TEST statement to dene propagation delay tests. The statement with keywords is placed following the test vector for which the measurement is to be performed. Propagation delay measurements are made with the format in Example 123.
CLOCK IN1 IN2 IN3 IN4 IN5 IN6 OUT1 OUT2 OUT3 OUT4
12-17
TDL Overview
Example 123. TDL Used to Specify Propagation Delay Measurements

ASIC_TEST =PROP FROM=<SIGNAL NAME>,TO=<SIGNAL NAME> [,CLKEDGE=<CLOCK EDGE>],MAX=<VALUE>[,MIN=<VALUE>], REJECT = <YES/NO>; Required keywords: PROP FROM TO MAX REJECT Indicates a propagation delay test is to be performed Indicates the input signal Indicates the output signal Indicates the maximum limit Indicates whether to reject a device having a measured value outside the min or max limits. A YES value causes rejection. A NO value allows the test to be made but does not reject devices measuring outside the limits. Optional keywords:
CLKEDGE
Is required if the FROM signal is a clock. The two values for this parameter are LEADING and TRAILING. LEADING indicates the positive-going edge of a 010 clock or the negative-going edge of a 101 clock. TRAILING indicates the negative-going edge of a 010 clock or the positive-going edge of a 101 clock.
MIN
Indicates minimum limits. Minimum limit testing is performed only by special request. Keyword elds can be in any order. If the timing elds require more than one line, each line must be terminated with a comma (,). The last line must end with a double quote and semicolon (;). As shown in Example 124, the ASIC_TEST statement means that you should measure the propagation delay on the preceding pattern, from pin IN1 to pin OUT1, with a maximum limit of 85 ns.
Example 124. Propagation Delay Measurement

(*$ (*$ (*$ (*$ O *) ICU *) NLT *) 1K1 *)
SETR P:TLCO;
12-18
TDL Overview
SETR P:THC1; ASIC_TEST=PROP FROM=IN1,TO=OUT1,MAX=85NS, REJECT=YES;
If the input signal is a clock, the edge must be specied. See Example 0-5 for the specication of a clock-to-output measurement.
Example 125. Clock-to-Output Measurement

ASIC_TEST = PROP FROM=CLK,TO=OUT1,MAX=55NS, CLKEDGE=LEADING,REJECT=NO;
12.3.3 Scan TDL

During functional testing, TDL denes conditions for all signal pins on a device. During the serial load and unload of a scan path, the only input data pins that are driven by changing data are the scanin pins. The only output or bidirectional pins that are unmasked are the scanout pins. Clock pins are also active. The functional TDL, which describes the conditions for all signal pins in every cycle, contains a massive amount of redundant information. TDL can describe just the nonredundant information. It minimizes the le size and vector processing costs. Additional statements used are: PATH This statement denes the scanin and scanout pins for a particular scan path. A scanin pin must be an input (IN). A scanout pin must be an output (OUT). Bidirectional pins (INOUT) can be used for either scanin or scanout, but this is not recommended because it requires extra circuitry. This statement is used to provide values for all pins prior to a SCAN statement. The scan pin values in the SCAN statement take precedence over the SET statement values. The pin values dened in the SET statement are not applied until the SCAN statement is executed. The SCAN statement indicates that scanning is to be performed using the scan pin values, described by SCAN_IN and SCAN_OUT. The number of scan cycles is determined by the loop_count parameter. Example 126 uses the previously listed TDL statements.
SET
SCAN
Example 126. Scan TDL Example

CONNECT P,VAR=(IN1,IN2,IN3,IN4,ACLOCK, BCLOCK,CCLOCK, SCANIN1,SCANOUT1,OUT1,OUT2,OUT3,OUT4), DEFPIN=(IN 8,OUT 5); PERIOD=200NS; STROBEVAR=(OUT1,OUT2,OUT3,OUT4,SCANOUT),OFFSET=190NS;
12-19
TDL Overview
DELAY CLOCK VAR=(IN1,IN2,IN3,IN4,SCANIN1),OFFSET= 5NS, CLOCK VAR=(ACLOCK,CLOCK),HOLD0=30NS,HOLD1=10NS,PATTERN=010; CLOCK VAR=(BCLOCK),HOLD0=10NS,HOLD1=10NS,PATTERN=010; PATHSCAN1,VAR=(SCANIN1,SCANOUT1), VAR=(R1.sd,R2.sd,R3.sd,R4.sd), CONFIG=LTTTTT; SETRP := TYYYY_LLL_YM_MMMM; SET P := THHHH_CCL_LM_MMMM; SCAN FOR 4, SCAN_IN SCAN1:= TLHLH;
SCAN_OUT SCAN1:= T0111; END_SCAN;
Example 0-7 shows the scan vectors from Example 0-6 written in functional TDL format. Notice how the redundant information expands the vectors.
Example 127. Scan Vectors in Functional TDL Format

SETR P := TYYYY_LLL_YM_MMMM; SETR P := THHHH_CCL_L0_MMMM; SETR P := THHHH_CCL_H1_MMMM; SETR P := THHHH_CCL_L1_MMMM; SETR P := THHHH_CCL_H1_MMMM;
12.3.4 Specifying IDDQ Measurements in TDL

Keywords can be inserted into the ASIC_TEST statement to dene quiescent power supply current measurements. The statement with keywords is placed following the test vector for which the measurement is to be performed. Quiescent power supply current measurements are made with the following format.
ASIC_TEST = IDDQ; ASIC_TEST = IDDQ MIN = <value>, MAX = <value>;
Required keyword: IDDQ Indicates an IDDQ test is to be performed Optional keywords:
12-20
TDL Overview
MIN MAX
<value> species the minimum allowed IDDQ value. <value> follows the usual conventions for current specications. <value> species the maximum allowed IDDQ value. <value> follows the usual conventions for current specications. If no limits are included, the IDDQ defaults for the given technology type are used. The IDDQ ASIC_TEST statement can be inserted in multiple locations in the TDL. For more reference material on the test program generation, refer to the following sources: t t t Part 2 of this document, the Generic Test Access Port Application Report Part 5 of this document, the ASIC TDL 91 Reference Guide Part 6 of this document, the ASIC TDL 91 and Scan Designs Reference Guide
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TDL Overview
12-22
Chapter 13
IEEE Standard 1149.1-Based dc Parametric Testing
This chapter proposes performing ASIC dc parametric tests using IEEE Standard 1149.1-1990. Two IEEE Standard 1149.1 congurations are presented: t t Standard Test Access Port Generic Test Access Port (GTAP)
The standard test access port works on all IEEE Standard 1149.1 devices. The GTAP conguration requires additional circuitry for improved dc parametric test capabilities.
Topic
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Parametric Measurements Using Boundary-Scan Architecture 1310 Integrating Boundary-Scan Architecture and GTAP . . . . . . . . . 1318
13-1
Introduction
13.1
Introduction
The IEEE Standard 1149.1-1990 denes a standard test access port and boundary-scan architecture. This circuitry is primarily intended to test system interconnect. All device I/O pins can be made observable and controllable respectively through boundary-scan cells. The IEEE Standard 1149.1 can independently control the device I/O pins to send/receive test signals to and from other IEEE Standard 1149.1 devices to test the interconnect. This capability can also be used for dc parametric testing. For example, by applying test patterns to the input pins and observing these pins with IEEE Standard 1149, a VIH/VIL test can be made. Also, a VOH/VOL test can be made by driving test patterns from the output pins with IEEE Standard 1149.1 and capturing the output pin values with IC automated test equipment (ATE). The IEEE Standard 1149.1 has limited provisions for device internal testing as well. The boundary-scan cells on the I/O pins can also drive test patterns into the device and capture the devices response to the test patterns, respectively. In addition to this capability, new capabilities can be integrated into the boundary-scan architecture through user-dened test data registers. Examples of test data registers are internal scan paths.
13-2
13.2
The boundary-scan architecture (see Figure 0-1) consists of four dedicated test pins: Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS) and Test Clock (TCK). An optional Test Reset (TRST) pin is permitted. The boundary-scan register surrounds the core logic (see Figure 0-2), and all device I/O signals must pass through a boundary-scan cell (BSC). The boundary-scan operations are programmed through the instruction register.
Figure 131. IEEE Standard 1149.1 Hardware Block Diagram

Boundary-Scan Register
Device Identication Register * TDI Test Data Register * MUX TDO
Bypass Register
Instruction Register
* Note: Optional
Instruction Decode
TMS TAP Controller TCK
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Figure 132. A Simplied View of the Boundary-Scan Register

PU/PD SO Input Pin PU/PD SO Input Pin PU/PD PU/PD SO Input Pin PU/PD SO Input Pin PI SI PO PI SO PU/PD SO PI SI PO PI SO SI PO BUF Input/ Output Pin SI PO PI SI PO On-Chip System Logic SI PI SO PO BUF 3-State Output Pin PI SI PO PI SO SI PO PI SI PO PI SO SI PO 2-State Output Pin
SCAN IN
SCAN OUT
A 1-bit bypass register is required to put the test circuit in a bypass mode. Boundary-scan permits optional circuits such as a device ID register, and user-dened test data registers. All communication with the boundary-scan registers is serial through the TDI/TDO pins. The test access port (TAP) is a 16-state controller. The TAP is controlled via the TMS/TCK pins. Refer to the IEEE Standard 1149.1 for a more complete description of this circuit.
13-4
13.2.1 Boundary-Scan Cell

The boundary-scan cell (BSC) is the basic element of the boundary-scan register. Each I/O port is connected through a BSC. Thus the I/O port can be made observable and controllable. Each BSC consists of two 2:1 multiplexers and two ip-ops (see Figure 132 and Figure 133). All port signals must pass through MUX2 via the signal in/signal out paths. All remaining BSC signals come from the Test Access Port (TAP) or connect to neighboring BSCs. REG1 is sometimes referred to as the capture ip-op, because it is clocked on the rising edge of TCK during the Capture-DR TAP state. REG2 is sometimes referred to as the update ip-op, because it is clocked on the falling edge of TCK during the Update-DR TAP state. The controls for MUX1 and MUX2 are decoded from the instruction register contents. Figure 133.
MODE
Boundary-Scan Cell
MUX2 G1
SIGNAL IN
1 Y 1 MUX1
SIGNAL OUT
SHIFT/LOAD
G1
SCANOUT
1 SCANIN 1 Y
REG1 1D C1 Q
REG2 1D C1 Q REG1 or REG2 may be implemented as latches
CLOCK A
CLOCK B
13.2.2 Test Access Port

The TAP is the interface to the IEEE Standard 1149.1 circuitry. The TAP is a 16-state controller that uses a serial communication protocol. The TAP can change state on each rising edge of TCK depending on the value of TMS and the current TAP state. Figure 134 illustrates the 16 TAP controller states. On power up, the TAP can be in any state. Holding TMS high and applying ve
13-5
rising edges on TCK guarantees that the TAP is in the Test-Logic-Reset state regardless of the original state. The TAP controller consists of two major state groups: Data Register (DR) and Instruction Register (IR). These two groups are functionally identical. The IR state group handles sampling (Capture-IR), loading/unloading (Shift-IR), and activating (Update-IR) the instruction register. The DR state group performs the same functions but for all other registers, i.e., boundary-scan, device ID, test data register, etc. The instruction register contents select the specic DR register. Only during the Shift-DR and Shift-IR states are the TDI and TDO pins used for shifting in/out register data. All shifting is done synchronous to the TCK clock. During all other states, the TDO pin is in highimpedance mode.
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Figure 134. TAP Controller State Diagram

1 Test-Logic-Reset 0
Run-Test/Idle
Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
Select-IR-Scan 0 1 Capture-IR 0
Shift-IR 1
Exit1-IR 0
Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0
The value shown adjacent to each state transition in Figure 13 4 represents the signal present at TMS at the time of a rising edge of TCK.
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13.2.3 Boundary-Scan Instructions

Boundary-scan instructions predene several special instruction register values known as public instructions. The instruction register contents are decoded by instruction decode logic, and the appropriate data register is connected between the TDI and TDO pins. The instruction decode logic may also generate other control signals associated with an instruction. An instruction is loaded by the following steps: 1) Move the TAP to the Shift-IR state. 2) Set the TDI pin to the rst IR bit value. 3) Toggle TCK from low to high. 4) Repeat steps 2 and 3 for each successive IR bit. 5) Move the TAP to the Exit1-IR state. 6) Move the TAP to the Update-IR state. Upon entering the Shift-IR state, the instruction register is automatically connected to the TDI/TDO pins. Shifting in a new instruction actually loads the capture portion of the instruction register. Upon entering the Update-IR state, the next high-to-low TCK clock edge transfers the new instruction from the capture to the update portion of the instruction register, where the new instruction goes into effect. Until then, the old instruction is still in effect. Two public instructions are SAMPLE/PRELOAD and EXTEST. All boundaryscan-compatible devices support these two public instructions. These instructions are useful for dc parametric testing.
13.2.4 Boundary-Scan Instruction: SAMPLE/PRELOAD

The SAMPLE/PRELOAD instruction permits taking a snapshot of the device I/O activity in the boundary-scan register (BSR) and shifting out the data, both without interfering with normal device operations. This instruction also permits preloading the BSR update ip-ops with an arbitrary value for use by another instruction. This instruction selects the boundary-scan register to be connected between the TDI and TDO pins. The SAMPLE operation occurs during the Capture-DR state and the next rising edge of TCK. All I/O data is captured in the BSR capture ip-ops from where it is serially shifted to the TDO pin on the rising edge of TCK during the Shift-DR states. PRELOAD data can be simultaneously shifted in with the
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shift out. The PRELOAD data is loaded into the BSR update ip-ops during the Update-DR state and the next falling edge of TCK. The binary value for the SAMPLE/PRELOAD instruction is user-denable.
13.2.5 Boundary-Scan Instruction: EXTEST

The EXTEST instruction is designed to test external chip circuitry. The output BSCs update ip-op controls the device output pins. The input pins are observable by the input BSCs capture ip-ops. During the Capture-DR state and the next rising edge of TCK, all input signals are clocked into the capture ip-ops. Captured data is shifted out, and new output data (similar to PRELOAD data) is shifted in on the rising edge of TCK during the Shift-DR state. The new output is loaded into the update ip-op during the Update-DR state and the next falling edge of TCK. The binary value for the EXTEST instruction is all zeros.
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Parametric Measurements Using Boundary-Scan Architecture
13.3

This section describes the procedure to perform dc parametric measurements on an ASIC device with IEEE Standard 1149.1 boundaryscan architecture. The basic circuits facilitate several of these measurements directly (i.e., VIH/VIL and VOH/VOL). Several measurements (IDDQ, IIH/IIL, and IOZ) require the control of nonboundary-scan features (i.e., SRAM standby mode and dc through-current cells). These controls must be provided by some other means. Table 0-1 lists the dc parametric measurements and the required device resources.
Table 131. Parametric Test Resources

Interface Parametric Tests VIH/VIL VOH/VOL IDDQ IIH/IIL IOZ VIH/VIL and VOH/ VOL (TAP pins)
Note:
TAP
BSR
SRAM Standby
dc Through Current
Test Vectors

Device initialization can require both boundary-scan and test vectors.
13.3.1 VIH/VIL Test

The VIH/VIL test comprises the following steps. Step 1: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (i.e., prevent bus contention). Step 2: Set all bidirectional pins to input mode.
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1) Load SAMPLE/PRELOAD instruction. 2) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DRShift-DR 3) Serially apply boundary-scan register data to the TDI pin and clock each bit with the rising edge of TCK. The boundary-scan register data must force all bidirectional pins to input mode. 4) Transition TAP through the following states: Exit1-DRUpdate-DRSelect-DR-ScanSelect-IR-Scan 5) Load EXTEST instruction. Step 3: Apply a broadside VIH test pattern (all inputs high) to device. Step 4: Capture the VIH input pin signals. Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DR Step 5: Scan out the captured VIH data. 1) Transition TAP through the following states: Capture-DRShift-DR 2) Set TMS low. 3) Serially reapply boundary-scan register data to the TDI pin and clock each bit with the rising edge of TCK. The boundary-scan register data must force all bidirectional pins to input mode. Serially verify each value on the TDO pin. 4) Transition TAP through the following states: Exit1-DRUpdate-DR Step 6: Apply a broadside VIL (all inputs low) test pattern to device. Step 7: Capture the VIL input pin signals. Transition TAP through the following states: Update-DRSelect -DR-ScanCapture-DR Step 8: Scan out the captured VIL data. 1) Transition TAP through the following states: Capture-DRShift-DR 2) Set TMS low.
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3) Serially reapply boundary-scan register data to TDI pin and clock each bit with the rising edge of TCK. The boundary-scan register data must force all bidirectional pins to input mode. Serially verify each value on the TDO pin. 4) Transition TAP through the following states: Exit-DRUpdate-DR Step 9: For Schmitt-trigger inputs, repeat VIH test (Step 3 through Step 5). Step 10: Reset the TAP. Transition TAP through the following states: Update-DRSelect-DR-ScanSelect-IR-Scan Test-Logic-Reset
13.3.2 VOH/VOL Test

The VOH/VOL test comprises the following steps. Step 1: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (i.e., prevent bus contention). Step 2: Set all 3-state and bidirectional pins to output mode and VOH pattern (all outputs high). 1) Load SAMPLE/PRELOAD instruction. 2) Transition TAP through the following states: Update-IRSelect-DR-Scan Capture-DRShift-DR 3) Serially apply boundary-scan register data to the TDI pin and clock each bit with the rising edge of TCK. The boundary-scan register data must force all 3-state and bidirectional pins to output mode. All output pins should have VOH values. 4) Transition TAP through the following states: Exit1-DRUpdate-DRSelect-DR-ScanSelect-IR-Scan 5) Load EXTEST instruction. Step 3: Measure the VOH values at each output pin with the ATE.
13-12 Design for Testability
Step 4: Set all 3-state and bidirectional pins to output mode and VOL pattern (all outputs low). 1) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DRShift-DR 2) Serially apply boundary-scan register data to the TDI pin and clock each bit with the rising edge of TCK. The boundary-scan register data must force all 3-state and bidirectional pins to output mode. All output pins should have VOL values. 3) Transition TAP through the following states: Exit1-DRUpdate-DR Step 5: Measure the VOL values at each output pin with the ATE. Step 6: Reset the TAP. Transition TAP through the following states: UpdateDRSelect-DR-ScanSelect-IR-Scan Test-Logic-Reset
13.3.3 IDDQ Test

The IDDQ test comprises the following steps. Step 1: Set ATE for an IDDQ test. All output and bidirectional pins are unloaded. Step 2: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (that is, prevent bus contention). Step 3: Force SRAMs into standby mode by whatever means have been provided. Usually, normal vectors are required to disable the SRAMs. Step 4: Apply customer-provided test vectors to device, stopping at the vector of interest.
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Step 5: Turn off through-current devices (pullups and pulldowns) by whatever means have been provided. Sometimes, a device pin is dedicated for turning off these through-current devices. Step 6: :Measure IDDQ at the VCC pin. Step 7: Repeat Step 4 through Step 6 for all vectors of interest. Care must be taken so that the SRAMs are never turned on.
Boundary-scan instructions are not involved in the IDDQ test.
13.3.4 IIH/IIL Test

The IIH/IIL test comprises the following steps. Step 1: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (i.e., prevent bus contention). Step 2: Set all bidirectional pins to input mode. 1) Load SAMPLE/PRELOAD instruction. 2) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DR Shift-DR 3) Serially apply boundary-scan register data to TDI pin and clock each bit with rising edge of TCK. The boundary-scan register data must force all bidirectional pins to input mode. 4) Transition TAP through the following states: Exit1-DRUpdate-DRSelect-DR-ScanSelect-IR-Scan 5) Load EXTEST instruction. Step 3: Apply a broadside IIH/IIL test pattern (alternating highs and lows on adjacent device pins) to the device. This pattern is designed to
13-14
detect pin-to-pin leakage. For differential input pins, apply VIH to one input and VIL to the other. Step 4: Turn off through-current devices (pullups and pulldowns) by whatever means have been provided. Sometimes, a device pin is dedicated for turning off these through-current devices. Step 5: Measure IIH/IIL leakage current at each input pin with the ATE. Step 6: Repeat Step 3 through Step 5 using complement of original IIH/IIL test pattern. Step 7: Repeat Step 3 through Step 6 but with through-current devices left on to measure bias current. Step 8: Reset the TAP. Transition TAP through the following states: Update-IRSelect-DR-ScanSelect-IR-Scan Test-Logic-Reset
13.3.5 IOZ Test

The IOZ test comprises the following steps. Step 1: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (i.e., prevent bus contention). Step 2: Set all bidirectional pins to input mode and all 3-state output buffers to high-impedance state. 1) Load SAMPLE/PRELOAD instruction. 2) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DRShift-DR 3) Serially apply boundary-scan register data to TDI pin and clock each bit with the rising edge of TCK. The boundary-scan register data must force all bidirectional pins to output mode. All 3-state output pins should be in high-impedance state.
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4) Transition TAP through the following states: Exit1-DRUpdate-DRSelect-DR-ScanSelect-IR-Scan 5) Load EXTEST instruction. Step 1: Turn off through-current devices (pullups and pulldowns) by whatever means have been provided. Sometimes, a device pin is dedicated for turning off these through-current devices. Step 2: Measure IOZ leakage current at each 3-state output pin with the ATE. Step 3: Repeat Step 3 through Step 4 but with through-current devices left on to measure pullup/pulldown current. Step 4: Reset the TAP. Transition TAP through the following states: Update-IRSelect-DR-ScanSelect-IR-Scan Test-Logic-Reset
13.3.6 VIH/VIL and VOH/VOL Test on TAP Pins

The test access port (TAP) signals consist of three input signals (TMS, TCK, and TDI), one output signal (TDO), and one optional input signal (TRST). Unlike all other device pins, the TAP pins are excluded from the boundaryscan register. A different approach is required for dc parametric tests on TAP signals. The TAP signals are tested indirectly. The input signals are manipulated to produce a predictable and unique output signal. If the expected output occurs, then the input must have been received correctly. All input and output signals experience both logic highs and lows. Step 1: Initialize the TAP controller to the Test-Logic-Reset state. Hold TMS to a logic high while toggling TCK with ve rising edges. TMS is always loaded on the rising edge to TCK. Step 2: Step the TAP controller to the Shift-IR state with the following TMS sequence, 0-1-1-0-0. The TDO output should be in high-impedance state during this sequence. The last rising edge of TCK (1) loads the instruction registers two least signicant bits (LSBs) with 01 where 1 is the LSB (closest to TDO) and (2) enables the TDO output. The latter event indicates entry into Shift-IR state (see Note). For this to occur, the TMS and TCK must have successfully decoded logic highs and logic lows. This indirectly conrms TMS and TCK VIH/VIL capability.
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The Shift-DR state also enables the TDO output. However, the Shift-DR state cannot be arrived at following a TMS sequence of 0-1-1-0-0. If TMS fails VIH/VIL, then it would decode 1-1-1-1-1 or 0-0-0-0-0, neither of which could arrive at Shift-DR or Shift-IR state.
Step 3: The TAP controller stays in Shift-IR state while TMS is held to logic low. For the n-bit instruction register, apply n TCK clock pulses to shift out the instruction register. The rst two bits shifted out should be a logic high followed by a logic low. These two output bits constitute the TDO VOH/VOL test. Simultaneously, the rst two bits shifted in should be a logic high followed by a logic low. Step 4: Apply two more TCK clocks. The next TDO values should be a logic high followed by a logic low. These bits are a result of the rst two bits shifted in. This event indirectly conrms TDI VIH/VIL capability. Step 5: If the optional TRSTZ signal is present, it should be held at a logic high until now. Set TRSTZ to a logic low. The TAP controller should be asynchronously reset from Shift-IR to Test-Logic-Reset state. This would be detectable when TDO returns to high-impedance state. Therefore, TRSTZ passes VIH/VIL.
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Integrating Boundary-Scan Architecture and GTAP
13.4

Boundary-scan architecture and TAP simplify making some dc parametric tests (VIH/VIL and VOH/VOL). However other dc parametric tests still require additional hardware support (IDDQ, IIH/IIL, and IOZ). This last group of tests requires turning off through-current macros and putting SRAMs in a standby mode that must be controlled outside boundary-scan control. There is no standard way of controlling through-current macros and SRAMs. This section proposes one way to integrate all dc parametric testing under a centralized boundary-scan control. The generic test access port (GTAP) is a TI ASIC test controller. The GTAP is designed to ease dc parametric testing in addition to other functions. The GTAP consists of a state-machine controller and a GTAP test register. If a device adheres to IEEE Std 1149.1, the GTAP controller is not necessary. The TAP controller becomes the primary test access port. The GTAP test register can be integrated into the boundary-scan architecture as a test data register. Refer to Figure 135.
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Figure 135. Boundary-Scan Registers and GTAP Test Register Hardware

Boundary-Scan Register
Device Identication Register *
TDI
TP000
TP000
TP000
TP000
MUX
TDO
GTAP Test Register Bypass Register
Instruction Register
TEST_REG Instruction Decode
TMS TAP Controller TCK * Note: Optional
Shift_DR Run-Test/Idle
13.4.1 Boundary-Scan Private Instruction: TEST_REG

A private instruction, TEST_REG, permits access with the GTAP Test Register. TEST_REG is a user-dened instruction. Upon loading this instruction, the GTAP test register is connected between the TDI and TDO pins. This instruction also partially enables the GTAP test register contents.
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13.4.2 GTAP Test Register

The GTAP test register consists of multiple TP000 macros connected as a scan path. Refer to Figure 0-6. All clock signals (GTT and GST) and enable signals (GTSTEN and GBUSENZ) are connected in parallel. The SCANOUT signal of one TP000 is connected to the SCANIN of the next, thus forming a scan path. The MSEL output signal is connected to a test feature associated with that TP000. A ip-op is required to synchronize TDI data into the GTAP test register.
Figure 136. GTAP Test Register Architecture

TST_ENBL LOW G C1 C2 SI SO GZ GTT GST G C1 C2 SI SO GZ G C1 C2 SI SO GZ GTT GST G C1 C2 SI SO TDO GZ
GTT GST TDI TCK D Q
GTT GST TDIQ
GTT GST
TP000
TP000
TP000
TP000
MSEL1
MSEL2
MSEL3
MSELn
The TP000 macros use two-phase nonoverlapping clocks (GTT/GST). Figure 137 illustrates TCK timing along with the required TP000 clock timing. The TCK is an edge-triggered clock. An edge-triggered-to-two-phase nonoverlapping clock generator circuit is required. Figure 138 illustrates one possible circuit implementation. Shift-DR is a signal representing whether the TAP is in the Shift-DR state. TEST_REG is a signal decoded from the instruction register decode logic. It represents when the TEST_REG private instruction is loaded into the instruction register.
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Figure 137. Test Register Load Timing Diagram

TCK
TDI
TDIQ
GTT
GST
Figure 138. TCK-to-Master/Slave Clock Interface Circuit

TEST_REG AN310 Shift-DR TCK IV110 D Q Shift-DRQ 3-Input AND Gate 2-Phase Clock Gener. CK120 GTT GST
13.4.3 Test Activation Control Pin (Optional)

A device-pin, test-activation control signal facilitates efcient dc parametric testing. This signal permits test features to be activated/deactivated easily without the time-consuming process of scanning in new instructions. This also simplies test vector generation, because the test control is simplied. Both test time and test costs are saved. The Test Data Output (TDO) pin can be used as an external test activation control to facilitate fast dc parametric testing (i.e., ICCQ testing). According to
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IEEE Standard 1149.1 Rule 3.5.1b, The TDO driver shall be set to its inactive drive state except when the scanning of data is in progress. An optional pullup may be required for the TDO pin to ensure no accidental activations (see Figure 139 and Figure 1310).
Figure 139. TDO Input Circuit for Test Activation

SCAN_ENBL
From TAP Controller
PAD
TDO
To TST_ENBL Circuit
Figure 1310. Example TST_ENBL Circuit

TEST_REG
Run-Test/Idle 3-Input AND Gate
TST_ENBL
TDO
The GTAP test registers selected test features can be activated for dc parametric testing under the following conditions: t t t EST_REG is current instruction. TAP Controller is in Run-Test/Idle state. TDO pin is forced low.
Alternatively, an unused or shared input device pin can be dedicated for this function. Some devices may not have any unused pins. Also, sharing a pin is device-specic. By using the TDO pin (which always exists), integration into the TI ow is simplied. This proposal assumes adoption of test activation control via the TDO pin.
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13.4.4 Parametric Measurements Using Boundary-Scan Architecture and GTAP Test Register
The IDDQ and IOZ tests are different when the GTAP test register is included. The other tests are the same as without the GTAP test register.
VIH/VIL Test
The VIH/VIL test is the same as for the boundary-scan architecture without the GTAP test register.
VOH/VOL Test
The VOH/VOL test is the same as for the boundary-scan architecture without the GTAP test register.
IDDQ Test
The IDDQ test comprises the following steps. Step 1: Set ATE for an IDDQ test. All output and bidirectional pins are unloaded. Step 2: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (i.e., prevent bus contention). Step 3: Initialize the GTAP test register. 1) Load TAP controller with TEST_REG private instruction. 2) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DRShift-DR 3) Serially apply GTAP test register data to the TDI pin and clock each bit with the rising edge of TCK. The GTAP test register data is programmed to force SRAMs into standby mode and turn off through-current macros. 4) Transition TAP through the following states: Exit1-DRUpdate-DRRun-Test/Idle
13-23
5) Upon leaving the Shift-DR TAP state, force the TDO pin high. Step 4: Apply customer-provided test vectors to device, stopping at vector of interest. Step 5: Force SRAMs into standby mode and turn off through-current devices (pullups and pulldowns) by forcing the TDO pin low. Step 6: Measure IDDQ at VCC pin. Step 7: Return SRAMs and through-current devices to their normal states by forcing the TDO pin high. Step 8: Repeat Step 4 through Step 6 for all vectors of interest. Step 9: Reset the TAP. Transition TAP through the following states: Select-DR-ScanSelect-IR-ScanTest-Logic-Reset
IIH/IIL Test
The IIH/IIL test is the same as for the boundary-scan architecture without the GTAP test register.
IOZ Test
The IOZ test comprises the following steps. Step 1: Initialize the device for test. 1) Apply power to the device under test. 2) Initialize the TAP controller by setting TMS to a logic high and toggling TCK with ve rising clock edges. 3) Apply sufcient normal vectors to prevent device states that may harm the device (that is, prevent bus contention). Step 2: Initialize the GTAP test register. 1) Load TAP controller with TEST_REG private instruction. 2) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DRShift-DR 3) Serially apply GTAP test register data to TDI pin and clock each bit with rising edge of TCK. The GTAP test register data is programmed to turn off through-current macros.
13-24
4) Transition TAP through the following states: Exit1-DRUpdate-DRRun-Test/Idle 5) Upon leaving the Shift-DR TAP state, force the TDO pin high. Step 3: Set all bidirectional pins to input mode and all 3-state output buffers to high-impedance state. 1) Load SAMPLE/PRELOAD instruction (refer to instructions). 2) Transition TAP through the following states: Update-IRSelect-DR-ScanCapture-DRShift-DR 3) Serially apply boundary-scan register data to TDI pin and clock each bit with rising edge of TCK. The boundary-scan register data must force all bidirectional pins to output mode. All 3-state output pins should be in high-impedance state. 4) Transition TAP through the following states: Exit1-DRUpdate-DRSelect-DR-ScanSelect-IR-Scan 5) Load EXTEST instruction. Step 4: Turn off through-current devices (pullups and pulldowns) by forcing the TDO pin low. Step 5: Measure IOZ leakage current at each 3-state output pin with the ATE. Step 6: Return through-current devices to their normal states by forcing the TDO pin high. Step 7: Repeat Step 3 through Step 6 but with through-current devices left on to measure pullup/pulldown current. Step 8: Reset the TAP. Transition TAP through the following states: Select-DR-ScanSelect-IR-ScanTest-Logic-Reset
13.4.5 VIH/VIL and VOH/VOL Test on TAP Pins

The VIH/VIL and VOH/VOL tests are the same as for the boundary-scan architecture without the GTAP test register. Same as for boundary-scan architecture without GTAP test register.
13-25
13-26
Chapter 14
Military ASIC
This chapter summarizes military ASIC documents and the location of military-specic design information. This additional military-specic information is necessary to complete a military design.
Topic
Page
Military-Specic Design Information . . . . . . . . . . . . . . . . . . . . . . 142 Military ASIC Topics Cross-Reference . . . . . . . . . . . . . . . . . . . . 143
14-1
Military-Specific Design Information
14.1
Military-Specific Design Information

Although the information provided in submicron ASIC documentation applies to military designs as well as commercial, the following documents contain additional information specic to military designs. These military-specic documents should be considered the primary sources of information for military designs. t Military family data sheets that contain product and macro library descriptions, an overview of the design ow and tools, and a summary of the product families. The Military ASIC Design/Test Guidelines document that contains the following additional information needed to complete a military ASIC design: s Design guidelines
s s s s s
Output buffer selection Pullup/pulldown input macros Power pin requirements Power estimation Package pin placement
s s s s s s s
Handoff requirements Military standards compliance Test application notes Test strategy considerations Tester constraints Military ASIC dc parametric application notes Prototype and production testing
Military designs are currently supported in a variety of packages. The package availability/offering to support military designs is continually being updated and expanded. A TI representative can supply you with the current status and availability of specic packages.
14-2
Military ASIC Topics Cross-Reference
14.2
Military ASIC Topics Cross-Reference

Table 141 provides a cross-reference of the most common ASIC design topics and their applicable documents. The table indicates summary and detailed information.
Table 141. Military ASIC Topics Cross-Reference 1

Submicron ASIC Documents 2 Military-Specic Military ASIC Topics Product description Macro library description Ratings, conditions, and characteristics Power estimation Package drawings and characteristics Design considerations for packaging Detailed macro tables VCC, temperature, and process multipliers Gate array design practices Design ow and handoff requirements Design for testability Test pattern requirements TI Design Environment (TIDE) Datapath and memory compiler (ACE) Floorplanning (CHIPS) Digital PLL application note Symbols and denitions
Notes:
FDS S S D D
MADG
MLS DM DSM DFT ACE CHIPS TSG MDF S S D D D D D D D D D
D D
D S D D S S S S S S S D D D D S
D D S S D S S D D D D D D D D D D D D D S
1) S = Summary information, D = Detailed information 2) Refer to the Preface for a list of submicron ASIC documents.
Legend:
FDS MADG MLS DM DSM DFT ACE CHIPS TSG MDF
BiCMOS and CMOS Family Data Sheets Military ASIC Designers Guide BiCMOS and CMOS Arrays Macro Library Summaries BiCMOS and CMOS Design Manuals Design Software Manual Design for Testability Reference Guide ASIC Compiler Environment Users Guide CHIPS Reference Guide Test Synthesis Users Guide Mentor Design Flow Users Guide
Military ASIC
14-3
14-4
Appendix A
Glossary
A
ACE: ASIC Compiler Environment. The graphical user interface delivery mechanism for submicron gate-array memory compiler elements. ASIC: Application Specic Integrated Circuit. A device designed for a user application, usually by the user. asynchronous logic: A collection of logic elements with the signal timing entirely dependent on the propagation delay of all elements in the signal path. The resulting signal ow timing changes with variations in process control, temperature, and power-supply voltage. ASIC TDL 91: An improved TI TDL format that supports both narrow and wide (SCAN) TDL. Narrow TDL lists the ATE state for all pins in every cycle. Wide or SCAN TDL allows a description of only nonredundant ATE states and pins. ATE: Automated Test Equipment. Machines used to test silicon. ATPG: Automatic Test Pattern Generation. A process by which the vectors required to produce a high-fault coverage for a design are generated by a program. These tools generally require scans in synchronous designs and assume certain scan rules. at-speed testing: Refers to test vectors that target the detection of delay faults. The term usually apllies to test vectors that operate at design frequency or that validate setup conditions. AUTOGEN: A TI software tool that compiles an automated test equipment program (ATE) program from TDL. Automatic Test Pattern Generation: A methodology, using software tools, to generate test patterns. Test patterns attempt to control and observe each circuit node using a stuck-at model.
B
back annotation: The process of updating the design database with actual interconnect delays (as opposed to estimations by design CAD software). The actual delays are calculated after placement and routing, when exact interconnect lengths are known. BIST: Built-In Self-Test. The capability of a product to carry out a functional test of itself. Some support from external equipment may be required. BIST usually involves special hardware in the product to generate input stimuli and to analyze test responses. block: A group of interconnected cells. May contain instances of other blocks. BNF: Backus Naur Form. A description of ASIC TDL 91. BTL: Backplane Transceiver Logic. A form of transmission line driver and receiver circuitry specied by IEEE Std 1149.1. bus: A data distribution path that typically has multiple data receivers and can have multiple data sources. Bus structures must be driven by threestate drivers. The drivers must be capable of disconnecting from the bus, and only one such source can be active at one time. bus contention: If more than one bus driver is active with conicting output levels at the same time, neither driver may be able to assert a true logic level on the bus line. The result could be excessive drive current, undened logic levels, and possible device failure. bus holder: A logic device that prevents a bus from oating if all bus drivers are placed into the high-impedance state. It maintains the last logic state.
C
cell: An individual component of a library (typically a logic gate; for example, a NA210 2-input NAND gate). See macro. CHIPS: Comprehensive Hierarchical Physical Synthesis. TIs submicron gate-array oorplanning tool designed to improve design cycle time by decreasing layout iterations. Includes PRELUDE delay estimation capabilities plus full graphic oorplanning. circuit initialization: A sequence of stimuli that sets internal nodes of a circuit to a predictable known state.
clock skew: The difference in clock edge timing across the chip. Loading and interconnect capacitance cause the active clock edge to be delayed, possibly disrupting critical circuit timing. clocked scan: An edge-triggered scan methodology. The clocked scan ipop has separate clock and data inputs for scan- and system-mode operation. CMOS: Complementary Metal Oxide Semiconductor. A form of digital logic that has the characteristics of low power consumption, wide power supply range, and high noise immunity. combinational fault: A functional fault whose effect on the behavior of the circuit is not affected by the sequence of the input stimuli. controllability: The ability of a node to be established at specic logic states by applying stimuli to the circuits externally accessible nodes. core logic: All logic functions except I/O buffers are core logic. critical path: Any path with special timing requirements.
CTL: CMOS Transceiver Logic. A form of transmission-line driver and receiver circuitry. These circuits allow CMOS devices to communicate in a low-noise, terminated-transmission-line environment.
D
delay fault: A fault in a circuit that causes failure to meet ac specications but might not cause functional failure. design-for-testability feature: Lets you specify a list of placement rules describing the connectivity of any logic path you want to group. design requirements document: A document to guide the product development that states the goals of the design. This type of document usually includes functional description, performance goals, cost goals, testability goals, and quality goals. detectable fault: A functional fault for which a test pattern can be created that always causes the effects of the fault to be observable at an externally accessible node. detected fault: A functional fault that causes effects that are observed at an externally accessible node when the circuit is exercised by the existing test pattern.
Glossary
DFT: Design for Testability. A design goal requiring that each node be both observable and controllable. Failure to achieve this design goal can compromise quality assurance.
E
ECL: Emitter-Coupled Logic. A nonsaturating form of digital logic that eliminates transistor storage time as a speed-limiting characteristic, permitting very-high-speed operation.
F
fault: A defect that can cause a failure in the circuit operation/timing. fault detectability ratio: The ratio of detectable faults to the sum of detectable and undetectable faults. fault grade: A measurement of the efciency of test vectors to detect manufacturing defects in silicon. The fault-grade value is usually presented as a percentage of the stuck-at faults that can be identied using those test vectors. fault grading: The process of determining the test pattern fault coverage of a circuit. fault-tolerant design: A design approach to enhance the ability of a circuit to remain operational after the occurrence of a fault. Fault-tolerance design techniques can impact fault detection. oating bus: Any bus line not driven by an active device is free to assume any voltage level. Circuits with inputs connected to this bus may draw excessive current or otherwise malfunction. oating input: The input of a macro can assume an undened voltage level if it is not driven to a dened logic level. Circuits with oating inputs can draw excessive current or otherwise malfunction. functional fault: A fault that causes improper logical operation of a circuit.
G
GTAP: Generic Test Access Port. The TI ASIC test controller. The GTAP can be instructed to enable or disable any combination of DFT features.
I
I/O: Input/Output. An input/output or bidirectional buffer cell used to connect design interface signals directly to package pins. ICCQ: IDDQ: A TI term for IDDQ. See IDDQ. DC leakage testing looks for abnormally high VCC current that indicates a logic or process defect. Test conditions for IDDQ testing must turn off all circuits that produce dc current in the static state.
J
JTAG: Joint Test Action Group. 1) Committee that established the test access port (TAP) and boundary-scan architecture dened in IEEE Standard 1149.1-1990. 2) Common name for IEEE Std1149.1-1990.
L
LSSD: Level-Sensitive Scan Design. A scan methodology. It is a technique where all logic storage elements in a device are chained together in a dual mode. The rst mode is the normal operation of the device where clocks allow the storage of data in normal system operation. In the second mode, master and slave clocks are used to shift data in and out of the device for testing purposes.
M
MegaModule: ter les. High-complexity macros such as SRAMs, FIFOs, and regis-
multiplexed ip-op scan: Multiplexed ip-op scan design is a scan methodology. It is a technique where all logic storage elements in a device are chained together in a dual mode. A 2:1 multiplexer is placed at the input of the logic storage elements. The rst mode is the normal operation of the device where the multiplexer allows the storage of data in normal system operation. In the second mode, the multiplexer allows the shifting of data in for test purposes. netlist: A description of a logic circuit that names the macros used and describes their interconnection.
Glossary
node: The end-point of a branch in a network or a point at which two or more branches meet.
O
observability: The ability to determine the logic states of an internal circuit node at the circuits externally accessible nodes. open circuit fault: A fault in a circuit that alters the number of nodes by breaking a node into two or more nodes.
P
parametric fault: A fault in a circuit that causes failure to meet ac or dc specications but might not cause functional failure. parametric test: These are electrical tests that evaluate parameters such as dc and ac electrical characteristics ( VIH, IDDQ, VOH, tpd, etc. ). PECL: Pseudo ECL. Logic that is implemented to operate with standard 5V VCC and GND power supplies. PMT: Parallel Module Test. A system of additional logic built into MegaModules for the purpose of enhancing the testability of the circuitry. Package input and output pins are multiplexed with internal test circuitry to minimize the need for package pins dedicated to testing. prelayout simulation: Accomplished as part of verication that the design meets design specications. To be effective, simulation must include circuit evaluation using both minimum and maximum propagation delays. The only unknown is actual interconnect capacitance. Interconnect capacitance is estimated by the design CAD software to give an assumed value.
R
redundant circuit: Deliberate duplication of logical functions to create backup functions that enhance performance or reliability of operation. RTL: Register Transfer Level. A subset of behavioral modeling constructs that can be used to model a circuit at the level of data owing between a set of registers. This level of abstraction typically contains little timing information, except references to a set of clock edges and features.
S
scan path: A shift register made up of the logic storage elements (standalone bit-storage devices). In test mode, the storage elements are connected in a shift register. During normal operation they carry out their normal system functions. The scan path is used to shift test data into the logic storage elements for controllability and to shift out test response data for observability. sequential fault: A functional fault whose effect on the behavior of the circuit is affected by the sequence of the input stimuli. short circuit fault: A fault in a circuit that alters the number of nodes by connecting two or more nodes together. simulation: The process of using workstation software to exercise a logic design. When properly done, simulation veries both circuit timing and logic functionality. state machine: A logic block that can assume any of several output logic states in response to input stimuli. Each logic state is uniquely determined from the previous state and the previous input. stuck-at-0 fault: A fault in a digital circuit characterized by a node remaining at a logic low (0) state regardless of changes in input stimuli. stuck-at-1 fault: A fault in a digital circuit characterized by a node remaining at a logic high (1) state regardless of changes in input stimuli. synchronous logic: Any group of logic storage elements through which the signal ow timing is controlled by the system clock. Clock signals cause data signals to advance from one logic storage element to the next, one element at a time. The resulting signal ow is thus made predictable.
T
testable: An electronic circuit is testable if test patterns can be generated, evaluated, and applied in such a way as to satisfy predened levels of performance dened in terms of fault-detection, fault-location, and testapplication criteria, within a predened cost-budget and timescale. TDL:
Test Description Language. A TI language dening test stimuli as a series of input values and expected output values. The TDL le serves as a source le to program the automated testers used for production test.
Glossary
test pattern: A set of test vectors. test pattern fault coverage: The ratio of the total number of detected faults to the total number of detectable faults. test program: A test pattern and instructions suitable for use on automated test equipment (ATE). A test program can be used to perform functional and parametric (ac, dc, or other) tests. test vector: A single instance of input stimuli and expected output responses.
U
undetectable fault: A functional fault for which no set of functional test vectors can be created that can guarantee that the effects of the fault are observable at an externally accessible node. undetected fault: A functional fault that causes effects that are not observed at an externally accessible node when the circuit is exercised by the existing test pattern.
V
VCC: Positive supply voltage or the voltage required across supply and ground terminals of a TTL or CMOS integrated circuit Positive supply voltage or the voltage required across supply and VSS terminals of a CMOS integrated circuit Ground terminal of a CMOS integrated circuit
VDD:
VSS:
Index
$ 1-2 ( ) 1-2 ) keyword fields end with 12-18 , 1-2 . 1-2 _ 1-2 1-2 0 TDL character 12-15 1 TDL character 12-15
A
ac critical paths pattern sets 3-9 scan path loading on 6-11 ac margin 3-2 ACE defined 1 activating, IR, updateIR group does 13-6 ad hoc tests 5-1 asynchronous circuits 5-7 bidirectional buffers 5-4 counters 5-10 dividers 5-10 gated clocks 5-8 internal clocks 5-9 internal node observability 5-3 Johnson counter test signal generator 5-18 known states 5-5 logic blocks 5-17
long counter chains 5-11 multiplexing direct access to logic 5-12 nesting sequential circuits 5-14 reconverging signals 5-16 redundant circuits 5-15 shift registers observability obtained from 5-20 test signal generator 5-19 structured vs 5-2 analog MegaModules 9-9 ANALOG TDL described 4-4 analogtodigital converter PMT I/O hookup 9-9, 9-12 application specific integrated circuit 1-2 approaches to testability 5-2 area vs testability -2 arithmetic logic units structured design approach not suited for 6-20 ASIC defined 1 ASIC Compiler Environment defined 1 ASIC compiler environment 1-2 ASIC TDL 91 1-2 defined 1 ASIC test controller 1-2 ASIC tests 8-6 ASIC_TEST ICCQ 10-14 ASIC_TEST statements pintopin testing and 12-11 propagation delay test specifications in 12-17 quiescent power supply current measurements specified in 12-20
Index
asynchronous circuits avoiding 5-7 gating clocks create 5-8 asynchronous clocks not in scan path flipflops 6-10 asynchronous logic defined 1 asynchronous timing as ATPG constraint 11-9 ATE block diagram 12-4 defined 1 loads 12-10 simulation example 12-11 logic simulator vs 12-2 pattern memory, DUT vectors stored in 12-3 test patterns operate on 12-1 ATPG 11-1 clock skew and 6-7 constraints 11-9 cycletime reduction from -3 debugging considerations 11-8 defined 1 design flow typical 11-4 highfaultgrade test patterns and 3-10 introduction 11-2 path sensitization 11-5 scan designs 11-7 full 11-6 summary 11-10 testing considerations 11-8 tool -8 atspeed testing 4-4, 4-5, 12-5, 12-11 AUTOGEN defined 1 PMT TDL sets converted by 4-5 automated test equipment 1-2 automatic test pattern generation 1-2 defined 1 automation, design structured approach favors 6-2
B
back annotation defined 2 backplane transceiver logic 1-2 Backus Naur Form 1-2 BiCMOS, TP0B0 macro 8-3 bidirectional buffers test contention and 12-10 bidirectional buses normal NAND tree patterns cause bus conflicts 10-6 bidirectional pins 1-2 internal access with 5-4 BIST defined 2 TDL pattern sets for 4-3 BIST TDL 4-3 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 BIST TEST ENABLE, ASIC test 8-6 BIST_AC TDL described 4-4 setup and hold testing and 12-11 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 bit definitions for test register 8-5 block defined 2 block diagrams ATE 12-4 GTAP 8-2 GTAPcontrolled PMT 9-3 IEEE Standard 1149.1 hardware 13-3 BNF defined 2 boundary-scan architecture 13-10 boundaryscan architecture 3-2, 7-2, 7-4, 10-12, 13-3, 13-5, 13-7, 13-8, 13-9, 13-10, 1312, 13-13, 13-14, 13-15, 13-16, 13-18, 13-19, 13-20, 13-21, 13-22, 13-23 boundaryscan cell 1-2, 13-5 boundaryscan instructions 13-8, 13-9, 13-14 boundaryscan macros 7-5, 7-6, 7-7
Index
Index
boundaryscan registers 1-2 BR described 7-5 BSC example 13-5 I/O signals pass through 13-3 BSR dc parametric test resources 13-10 described 7-5 GTAP test register and hardware, example 13-19 public instructions and 13-8 view of, simplified 13-4 BTL defined 2 builtinself test 1-2 bus defined 2 bus contentions avoiding 12-5 bidirectional bus running normal NAND tree patterns may cause 10-6 defined 2 internal avoid 10-13 parametric test patterns and 10-2 removing 6-12 scan testing and 6-12 bus floating preventing 12-5 bus holders defined 2 bus interface boundary 6-14 bypass counters 5-10 bypass dividers 5-10 bypass register 7-5
C
C TDL character 12-15 captureIR group sampling done by 13-6
cautions information about vi cells 1-2 defined 2 characters simulator mapping 1-2 CHIPS defined 2 circuit testable described 5-2 circuit design typical flow ATPG 11-4 circuit initialization 5-5 defined 2 clear mechanism controllability added with 5-6 CLKEDGE keywords 12-18 CLOCK 6-5 shift register and 5-19 clock edge to output pintopin testing of 12-12 clock inputs circuit initialization to known state and 5-5 clocked scan flipflops 6-3 clock signals GTAP test registers and 13-20 TDL 12-7 width, minimum illustrated 12-9 clock skew defined 3 edgetriggered flipflop scan and 6-7 CLOCK statements TDL 12-7 Clocked LSSD scan flip-flop circuit interconnect illustrated 6-9 illustrated 6-8 clocked NAND tree input threshold voltage levels tested with 10-4 illustrated 10-5 shared control pins
Index
Index
illustrated 10-8 TGC1000 configurations illustrated 10-7 TGC2000 configurations illustrated 10-7 clocked scan 3-7 defined 3 clocked scan flipflop scan designs 6-3 macros, TI offers 6-3 clocked scan flipflop scan designs multiple scan chains illustrated 6-16 clocks 1-2 adding to asynchronous latch 5-7 constraints ATPG 11-9 flipflop scan design and 6-10 clocktooutput measurements 12-19 CMOS defined 3 CMOS transceiver logic 1-2 combinational fault defined 3 commas (,) keyword fields separated by 12-18 compatibility planning for 3-13 compiled cells structured approach not suited for 6-20 complementary metal oxide semiconductor 1-2 Comprehensive Hierarchical Physical Synthesis defined 2 constraints ATPG 11-9 contact ix contentions 1-2 tester vs TTL/CMOS bidirectional buffers 1210 control pins dedicated clocked NAND tree circuit illustrated 10-5 voltage level test patterns 10-6 shared
clocked NAND tree circuit illustrated 10-8 voltage level test patterns illustrated 10-9 controllability adding with clear mechanism 5-6 debugging time and -4 defined 3 of I/O ports, via BSC 13-5 of logic multiplexing improves 5-12 scan designs and 6-2 test vector generation and 5-2 controller 1-2 generic test access port communication protocol 8-8 core logic defined 3 costofownership -8 costs 1-2 of ownership -5 faultgrade requirements as part of 3-4 illustrated -9 tradeoffs -4 counters bypassing 5-10 critical path defined 3 crosscoupled latches 6-10 CTL defined 3
D
DATA 6-3, 6-5 data corruption bus contention causes 6-12 data inputs clocked scan flipflops 6-3 data register TAP group 13-6 dc leakage current
Index
Index
measuring 10-13 dc leakage test 1-2, 3-10 dc parametric measurements 10-1 input current 10-12 input threshold voltage levels using clocked NAND tree 10-4 leakage current 10-13 output voltage levels 10-10 overview 10-2 threestate highimpedance 10-11 using boundary-scan architecture resources 13-10 using boundaryscan architecture GTAP and test activation control pin
TDO input circuit for 13-22 TST_ENBL circuit 13-22

test register
architecture example 13-20 load time diagram 13-21

using boundaryscan architecture 13-10 using boundaryscan architecture GTAP and hardware registers 13-19 integrating 13-18 private instruction TEST_REG 13-19 test activation control pin 13-21 test register 13-20, 13-23 dc parametric testing 1-2, 4-2, 13-1 boundaryscan architecture 13-3, 13-5, 13-7, 13-8, 13-9 hardware block diagram 13-3 introduction 13-2 resources for 13-10 TGC1000 requirements 4-5 TGC2000 requirements 4-5 dc parametric tests using boundaryscan architecture IDDQ 13-13 IIH/IIL 13-14 IOZ 13-15 VIH/VIL 13-10 VIH/VIL and VOH/VOL (TAP pins) 13-16 VOH/VOL 13-12 dc threshold testing
VIH-VIL TDL for 4-4 dc through current dc parametric test resources 13-10 DC_PARA TDL described 4-3 output voltage levels 10-10 parametric test pattern sets assigned to 10-2 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 threestate highimpedance measurements 1011 debugging ATPG considerations 11-8 diagnostic pattern sets, establishing for 3-9 time design for testability impact on -4 decoupling linked logic blocks 5-17 defect levels ASIC PPM vs PCB PPM rates illustrated -8 fault coverage vs -5 for PCB designs -7 highfaultgrade test pattern set for low -8 Motorola, Delco study results -6 Williams model -5 delay fault defined 3 delays minimum not tested 12-12 Delco Williams study supported by study from -6 design practices committing to for DFT strategy development 3-3 reasons for using -1 design automation structured approach favors 6-2 Design Automation Division 1-2 Design Flow Users Guide vii design help ix Design Requirements Document defined 3
Index
Index
faultgrade requirements inclusion in 3-4 designfortestability feature defined 3 detectable fault defined 3 detected fault defined 3 development cycle timetomarket and -3 development time fault grade vs illustrated -3 device identification register 7-5 device under test vectors applied to stored in ATE pattern memory 12-3 devices damage to bus contention causes 6-12 initialization dc parametric test resources and 13-10 pin test activation 13-21 TDO input circuit for example 13-22 TST_ENBL circuit example 13-22 DFT concepts key 5-2 defined 4 economic tradeoffs for -4 feature defined 3 flow, typical 11-3 ATPG 11-4 GTAP 8-1 logic design, keeping in mind 5-2 militaryspecific information 14-1, 14-3 purpose 5-2 reasons for using -1 fault coverage -5 introduction -1 ownership cost -5 testability needed -2 testtime costs -2
timetomarket -3 scan designs 6-1 strategy development 3-1 committing to 3-3 compatibility planning for 3-13 diagnostic pattern set, creating 3-9 faultgrade requirements establishing 3-4 flowchart 3-14 gate density as base for 3-6 highfaultgrade test patterns, generating 3-10 IEEE Std 1149.1 as system requirement 3-5 structured tools choosing 3-7 technology, selecting 3-2 test patterns converting to TDL 3-12 simulations 3-11 timing patterns, simulating 3-11 structured approaches 6-2 DIAGNOST TDL described 4-4 if BIST TDL fails 4-3 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 diagnostics pattern set establishment for debugging 3-9 differential amplifier PMT I/O hookup 9-18, 9-19 digitaltoanalog converter PMT I/O hookup 9-15, 9-16 direct access to logic multiplexing provides 5-12 directconnect PMT 1-2 dividers bypassing 5-10 documentation militaryspecific ASIC 14-3 double quotes () keyword fields end with 12-18 DR TAP group 13-6 duration
Index
Index
minimum of test periods 12-4 DUT vectors applied to stored in ATE pattern memory 12-3
E
ECL defined 4 economics 1-2 tradeoffs -2, -4 edgetriggered clocks 5-8 edgetriggered flipflop scan designs 6-7 efficiency scan designs not noted for 6-20 embedded memories PMT tests 3-6 emittercoupled logic 1-2 EXPANSION ASIC test 8-6 external chip circuitry EXTEST instruction designed to test 13-9 EXTEST instructions 13-9 input threshold voltage levels checked using clocked NAND tree 10-4 output voltage levels 10-10 threestate highimpedance measurements and 10-11
F
falltime measurements 1-2 fault defined 4 fault coverage described 1-2 determining target 11-2 device defect level vs -5 Motorola Delco study results -6 tradeoffs -4 fault detectability ratio
defined 4 fault grade 1-2 defined 4 development time vs illustrated -3 requirements establishing as part of DFT strategy development 3-4 fault grader -8 fault grading defined 4 fault simulation 1-1 multiple scan chain designs and 6-14 faulttolerant design 4 feedback loops combinatorial as ATPG constraints 11-9 feedback paths breaking in nested sequential circuits 5-14 scan flipflops and 6-10 field maintenance costs fault coverage and -5 flipflop outputs 5-13 flipflop scan designs 5-5, 6-3, 6-5, 6-7, 6-10 floating bus defined 4 floating I/O inputs avoid 10-13 floating input defined 4 floating internal nodes avoid 10-13 frequency dividers 5-5 FROM keywords 12-18 full scan designs 11-6 FUNC TDL described 4-3 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 FUNC_AC TDL described 4-4 setup and hold testing and 12-11 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5
Index
Index
functional fault defined 4
G
gate density DFT strategy development based on 3-6 gatecount margin 3-2 gated clocks avoiding 5-8 GBUSENZ signals 13-20 generating test patterns 12-1 ATE block diagram 12-4 creating 12-6 input delay groups 12-6 illustrated 12-7
TDL
example 12-15 propagation delay measurements specifying, in TDL 12-17 quiescent current measurements 12-20 scan 12-19
TDL clocks 12-7
ATE loads 12-10 simulation 12-11 definition example 12-8 output strobe groups 12-9 placement, illustrated 1210
synchronous pattern use example 12-3 tester priod slip 12-5 generic test access port 1-2 GTAP 1-2, 8-1 block diagram 8-2 defined 4 integrating with boundaryscan architecture 13-18, 1319, 13-20, 13-21, 13-22, 13-23 overview 8-2 PMT control block diagram 9-3 controlled by 9-2 PMTSETUP TDL initializes 4-4 Test Register 13-20 and boundaryscan registers 13-19 architecture example 13-20 load timing diagram 13-21 TEST_REG instruction and 13-19 Test Registers 8-3 GTAP controller 8-7 multiplexed PMT I/O hookups and 9-7 state transition diagram 8-9 GTAPCHK TDL described 4-4 scan path integrity verified by 4-4 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 GTSTEN signals 13-20 guidelines for flipflop scan designs 6-10
H
H TDL character 12-15 hardware design testability affects on 1-1 overhead for multiplexed flipflop scan designs 6-6 help with designs ix HI Z ASIC test selection codes 8-6
performance test procedures

12-11
test precautions special 12-10 width, minimum example 12-9

introduction 12-2
Index
Index
TP000 bit assignments 8-5 highfrequency testing 12-5 hookup analogtodigital converter multiple PMT I/Os 9-12 single PMT I/O 9-9 differential amplifier multiple PMT I/O 9-19 single PMT I/O 9-18 digitaltoanalog converter multiple PMT I/O 9-16 single PMT I/O 9-15 multiple MegaModule PMT I/O 9-7 single MegaModule PMT I/O 9-5
I
I/O defined 5 I/O buffers multiplexed PMT and 9-7 I/O ports BSC connects 13-5 ICC TDL TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 ICCQ defined 5 keywords 12-20 IDDQ defined 5 test location and pattern set identification 1014 IDDQ TDL described 4-3 IDDQ test 1-2, 13-10, 13-13 location and pattern set identification 10-14 using boundaryscan architecture and GTAP test register 13-23 IDR described 7-5 IEEE Standard 1149.1 1-2, 7-1 boundaryscan architecture 7-3, 7-4 circuit not adhering to
threshold circuitry needs to be added to 10-4 dc parametric measurements 10-2 using boundary-scan architecture 13-10 using boundaryscan architecture 13-10, 1318, 13-19, 13-20, 13-21, 13-22, 1323 dc parametric testing based on 13-1 boundaryscan architecture 13-3, 13-5, 13-7, 13-8, 13-9 hardware block diagram 13-3 introduction 13-2 dc parametric tests using boundaryscan architecture 13-10, 1312, 13-13, 13-14, 13-15, 13-16 DFT strategy development requirement 3-5 output voltage levels testing and 10-10 overview 7-2 threestate highimpedance measurements and 10-11 IEEE Standard Test Access Port and BoundaryScan Architecture (JTAG) 1-2 IIH/IIL test 13-10, 13-14 using boundaryscan architecture and GTAP test register 13-24 IIH/IIL/IOZ CURRENT ASIC test 8-6 initializing circuit to known state 5-5 flipflop scan designs and 6-10 input current 10-12 measuring 10-12 input delay groups test period relationship to 12-6 illustrated 12-6 input signals delays setup and hold verification of 12-11 FROM keyword indicates 12-18 input delay group is set of 12-6 test vectors define 12-6 input threshold voltage levels clocked NAND tree for testing 10-4 illustrated 10-5 shared control pins illustrated 10-8 TGC1000 configurations 10-7
Index
Index
TGC2000 configurations 10-7 input/output defined 5 instruction register 1-2 instructions loading 13-8 internal clocks bypassing 5-9 internal nodes bidirectional pins give access to 5-4 observability via unused pins 5-3 introduction 1-1 inverter isolating scan chain loading with 6-11 IOZ test 13-10, 13-15 using boundaryscan architecture and GTAP test register 13-24 IR boundaryscan operations programmed through 13-3 described 7-5 TAP group 13-6
J
Johnson counter test signal generator 5-18 Joint Test Action Group 1-2 JTAG 3-2 defined 5
L
L TDL character 12-15 latches set, reset capabilities needed for circuit initialization 5-5 layout errors failures and 11-8 leakage current 10-13 levelsensitive scan design 1-2
linked logic blocks uncoupling 5-17 load timing test register diagram 13-21 loading IR shiftIR group does 13-6 logic adding 1-1 compatibility planning for 3-13 direct access multiplexing provides 5-12 redundant removing 5-15 logic blocks linked decoupling 5-17 logic design failures based on 11-8 logic feedback paths scan flipflops and 6-10 logic functions FUNC TDL verifies 4-3 PMT TDL verifies 4-4 logic integrity SCAN TDL verifies 4-3 logic simulation 3-11 logic simulator ATE vs 12-2 logic verification responsibilities for 4-2 SCAN_AC TDL and 4-4 TGC1000 TDL pattern set requirements 4-5 TGC2000 TDL pattern set requirements 4-5 logic waveforms test vectors and corresponding 12-17 long counter chains 5-11 long scan chains multiple scan chains vs 6-14 separating from signal path 6-11 LSSD 3-8 ATPG and 11-5
Index
10
Index
defined 5 multiple clocked scan chains illustrated 6-18 LSSD scan flip-flop design 6-8
M
M TDL character 12-15 macro functions structured approach not suited for 6-20 macros 1-2 clocked scan flipflop 6-3 multiplexed flipflop scan design 6-5 MagaModules test collar 9-4 mask fabrication defects failures and 11-8 MAX keywords 12-18, 12-21 MCLK GTAP controller pin 8-7 measurements parametric 10-1 input current 10-12 input threshold voltage levels using clocked NAND tree 10-4 leakage current 10-13 output voltage levels 10-10 overview 10-2 threestate highimpedance 10-11 MegaModule PMT I/O hookup 9-5, 9-7, 9-9, 9-12, 9-15, 916, 9-18, 9-19 MegaModules defined 5 described 9-2 logic functions tested by PMT TDL 4-4 multiplexed PMT insystem use 9-21 rules 9-8 PMT I/O hookup 9-5, 9-7 PMT test for 9-2
PMT_SIM TDL verifies PMT hookup to package pins 4-4 memories embedded PMT tests 3-6 memory PMT collar 1-2 military ASIC 14-1 topic crossreference table 14-3 MIN keywords 12-18, 12-21 modules testisolation 6-14 Motorola Williams study supported by study from -6 MSELA ASIC test selection codes 8-6 TP000 bit assignments 8-5 MSELN ASIC test selection codes 8-6 TP000 bit assignments 8-5 MSELT ASIC test selection codes 8-6 TP000 bit assignments 8-5 multiplexed flipflop scan 3-7, 6-5, 6-6, 5 multiplexed flipflop scan designs 6-17 multiplexed PMT 1-2 multiplexing direct access to logic provided by 5-12
N
nesting sequential circuits feedback paths in breaking 5-14 netlist defined 5 node defined 6 nondigital circuitry structured approach not suited for 6-20 notational conventions v
Index
11
Index
O
observability debugging time and -4 defined 6 of I/O ports, via BSC 13-5 of internal nodes improving via unused pins 5-3 of logic multiplexing improves 5-12 scan designs and 6-2 shift register used to obtain 5-20 test vector generation and 5-2 onchip oscillator circuitry 5-9 open circuit fault defined 6 oscillators PWRDN pin 10-13 oscilloscopes ineffective in debugging ASIC systems -4 output signals test vectors define 12-6 TO keyword indicates 12-18 output strobe groups test pattern generation and 12-9 placement example 12-10 precautions special 12-10 output voltage levels testing 10-10 overhead for clocked scan flipflop designs 6-4 for multiplexed flipflop scan designs 6-6 overview ATPG 11-2 GTAP 8-2 IEEE Standard 1149.1 7-2 parametric measurements 10-2 PMT 9-1 TDL 12-13 test pattern generation 12-2 ownership costs -5 illustrated -9
P
package pins pintopin testing of 12-11 parallel module test 1-2 parallel scan chains 3-8 parallel scan designs 6-14 parallel testing 6-14 time determined by longest chain 6-15 parametric fault defined 6 parametric measurements 10-1 input current 10-12 input threshold voltage levels using clocked NAND tree 10-4 leakage current 10-13 output voltage levels 10-10 overview 10-2 threestate highimpedance 10-11 parametric test defined 6 partial scan 3-8 partial scans designs 11-7 partitioning circuits in multiple scan chains 6-14 path sensitization ATPG and 11-5 PATH statements description 12-19 pattern sets diagnostic establishing 3-9 parallel module tests 4-4 scan 4-3 pattern statements IDDQ 10-14 PCB boundaryscannable 7-7 costofownership orderofmagnitude relationship for -8 defect rates for -7 ASIC PPM vs illustrated -8
Index
12
Index
IEEE Standard 1149.1 and 7-1 IEEE Standard1149.1 and 3-5 PECL defined 6 performance TDL test procedures 12-11 atspeed testing 12-11 pintopin testing 12-11 setup and hold testing 12-11 testability and -2 period slip described 12-4 tester example 12-5 pins 1-2 TDL defines conditions for signal 12-19 unused testability improved via 5-3 pintopin testing 12-11 PMT 1-2, 9-1 analog MegaModules 9-9 analogtodigital I/O hookup 9-9, 9-12 defined 6 DFT strategy development and 3-2 differential amplifier I/O hookup 9-18, 9-19 digitaltoanalog I/O hookup 9-15, 9-16 embedded memories tested with 3-6 MagaModules 9-2 multiple MegaModule I/O hookup 9-7 multiplexed insystem use 9-21 rules 9-8 single MegaModule I/O hookup 9-5 TDL pattern sets for 4-4 test bus 9-6 PMT TDL described 4-4 PMT TEST ENABLE ASIC test 8-6 PMT_I/O ASIC test selection codes 8-6 TP000 bit assignments 8-5 PMT_SIM TDL described 4-4 PMTSETUP TDL
described 4-4 power supply quiescent current measurements ASIC_TEST statements define 12-20 predictability of designs 5-2 prelayout simulation defined 6 preload multiplexed PMT appropriate for 9-21 PRELOAD instructions 13-8 printed circuit boards 1-2 private instructions TEST_REG 13-19 process yields in Williams model -5 PROP keywords 12-18 propagation delay tests 1-2 edgetriggered clock and 5-8 measurements example 12-18 one needed per design 4-3 pintopin testing verifies 12-11 PROP keyword indicates 12-18 responsibilities for 4-2 specifying measurements in TDL 12-17 TGC1000 TDL pattern set requirements 4-5 TGC2000 TDL pattern set requirements 4-5 pseudo ECL 1-2 PU/PD CURRENT ASIC test 8-6 public instructions 13-8 pulldown macros PWRDN pin 10-13 pullup macros PWRDN pin 10-13 pulsegenerating circuitry 5-9 PWRDN ASIC test selection codes 8-6 TP000 bit assignments 8-5 PWRDN pin 10-13 PWRDN STATE ASIC test 8-6
Index
13
Index
Q
quiescent power supply current measurements ASIC_TEST statement defines 12-20
TDLCHKR a tool for 4-4 rules multiplexed PMT 9-8 precautions for test pattern creation 12-10
R
random access memory structured approaches not suited for 6-20 random vector generation ATPG 11-5 read only memory structured design approach not suited for 6-20 reconverging signals watching for 5-16 redundant logic defined 6 testing 5-15 register files structured approach not suited for 6-20 register transfer level defined 6 registers 1-2 as overhead for multiplexed flipflop scan designs 6-6 REJECT keywords 12-18 reset capabilities initializing circuit to known state requires, for latches, flipflops 5-5 RESETZ shift register and 5-19 RESTORE1 test condition 8-8 RESTORE2 test condition 8-8 review process design DFT strategy development and 3-4 risetime measurement 1-2 RTL defined 6 rule checking structured approach favors 6-2
S
safe circuit initialization pattern 10-4, 10-10, 1011 SAMPLE/PRELOAD instructions 13-8 input threshold voltage levels checked using clocked NAND tree 10-4 output voltage levels 10-10 threestate highimpedance measurements and 10-11 sampling IR captureIR group does 13-6 SCAN GTAP controller pin 8-7 scan 3-7 DFT strategy development and 3-2 sequential logic tested best with 3-7 scan chains parallel 3-8 SCAN CLOCK 6-3, 6-4 clock skew and 6-7 scan designs 1-2, 6-1 bus contention scan testing and 6-12 clocked scan flipflop 6-3 edgetriggered flipflop 6-7 flipflop guidelines 6-10 inefficiencies in certain structures 6-20 multiplexed flipflop 6-5 parallel 6-14 partial ATPG and 11-7 scan path loading on critical ac path 6-11 structured approaches 6-2 testisolation modules 6-14 SCAN ENABLE 6-5, 6-6
Index
14
Index
scan macros partitioning logic reduces number of 6-15 scan paths defined 7 flipflops 6-7 flipflops in 6-10 integrity GTAPCHK TDL checks 4-4 SCANCHK TDL checks 4-3 inversions 6-11 isolating loading with inverter illustrated 6-11 loading on critical ac paths 6-11 multiple as testisolatable modules 6-14 clocked scan flipflop scan designs 6-16 LSSD illustrated 6-18 multiplexed flipflop scan designs 6-17 patterns 6-18 test patterns, multiple 6-18 scan rings 6-20 SCAN statements description 12-19 SCAN TDL described 4-3 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 scan testing bus contention and 6-12 SCAN_AC TDL described 4-4 setup and hold testing and 12-11 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 SCANCHK TDL described 4-3 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 SCANIN DATA 6-3, 6-5 SCANOUT 6-3 SCLK GTAP controller pin 8-7
select inputs circuit initialization to known state and 5-5 semicolon ( 12-18 sequential circuits bypassing 5-10 nests breaking feedback paths in 5-14 sequential fault defined 7 sequential logic scan approach best for testing 3-7 serial shift register test register is 8-3 set capabilities initializing circuit to known state requires, for latches, flipflops 5-5 SET statements description 12-19 setup and hold testing 12-11 shift registers observability obtained by using 5-20 scan chain circuit initialization to known state and 5-5 serial test register is 8-3 test signal generator 5-19 shiftIR group loading done by 13-6 short circuit fault defined 7 signal generators test Johnson counter 5-18 shift register 5-19 signals paths long scan chains separating from 6-11 reconverging 5-16 separating unused pins control 5-17 types TDL toggle states required for various 10-3 silicon
Index
15
Index
overhead for clocked scan flipflop designs 6-4 for multiplexed flipflop scan designs 6-6 simulations ATE loads and 12-10 example 12-11 defined 7 test pattern 3-11 skew, scan 1-2 slave clock interface circuit TCKtoMaster 13-21 splitting long counter chains 5-11 SR 1-2 SRAM MegaModules 9-2 SRAM OFF ASIC test selection codes 8-6 SRAM standby dc parametric test resources 13-10 SRAM_OFF TP000 bit assignments 8-5 SRL 1-2 state machine controllability using clear to add illustrated 5-6 defined 7 state machines uncontrollable illustrated 5-5 state transition diagram GTAP controller 8-9 states initializing circuit to known 5-5 static testing ICC TDL facilitates 4-3 status check multiplexed PMT appropriate for 9-21 strategies for testability, developing 3-1 commitment to design practices 3-3 compatibility planning 3-13 diagnostic pattern set for debugging 3-9
faultgrade requirements 3-4 flowchart 3-14 gatedensity approach 3-6 highfaultgrade test pattern generation 3-10 IEEE Std 1149.1 as system requirement 3-5 structured tool selection 3-7 technology selection 3-2 test patterns converting to TDL 3-12 timing simulations 3-11 structured testing ad hoc vs 5-2 structured tools choosing 3-7 clocked scan 3-7 LSSD 3-8 multiplexed flipflop scan 3-7 parallel scan chains 3-8 partial scan 3-8 scan designs 6-2 stuckat0fault 7 stuckat1fault 7 surface contamination circuit dc leakage current measuring for 10-13 synchronous logic defined 7 synchronous systems ATEs are 12-2 system designers IEEE Standard 1149.1 effect on 7-2
T
TAP 1-2 boundaryscan architecture 13-5 controller 7-4 dc parametric test resources 13-10 described 13-4 DFT strategy development and 3-2 IEEE Standard 1149.1 and 7-2 state diagram 13-7
Index
16
Index
TCK boundaryscan architecture test pin 13-3 to Master slave clock interface circuit 13-21 TDI boundaryscan architecture test pin 13-3 TDL 1-2 BIST_AC pattern types 12-11 clocks 12-7 definition example 12-8 width minimum illustrated 12-9 defined 7 example 12-15 FUNC_AC pattern types 12-11 IDDQ location 10-14 propagation delay measurements specifying 12-17 quiescent power supply current measurements defined in 12-20 scan 12-19 example 12-19 vectors 12-20 SCAN_AC pattern types 12-11 simulation timing and 3-11 test pattern created by 12-6 ATE loads 12-10 simulation example 12-11 clocks 12-7 input delay group 12-6 output strobe groups 12-9 placement example 12-10
BIST 4-3 pattern sets
required by all 4-3

PMT 4-4 scan 4-3 TDLCHKR rule checker 4-4 TDO pins as test activation control pin 13-21 example 13-22 boundaryscan architecture test pin 13-3 technologies selecting, for DFT strategy development 3-2 TEST GTAP controller pin 8-7 test access port 1-2 test access port controller 1-2 test activation control pin 13-21 TDO input circuit for example 13-22 TST_ENBL circuit example 13-22 test bus PMT 9-6 test capability overlooked in design process -2 Test Clock boundaryscan architecture test pin 13-3 test collar MegaModule 9-4 test controller 1-2 Test Data In boundaryscan architecture test pin 13-3 Test Data Out boundaryscan architecture test pin 13-3 test description language 1-2 test insertion timetomarket and -3 Test Mode Select boundaryscan architecture test pin 13-3 test pattern fault coverage 1-2 defined 8 test pattern sets BIST 4-3
performance test procedures 12-11 precautions special 12-10 test patterns converting to 3-12 handing off to TI in 4-2 toggle states required for signal types 10-2 types described 4-3
Index
17
Index
output strobe groups and 12-9 TDL requirements for 4-3 test patterns compatibility planning for 3-13 converting to TDL 3-12 dc parametric measurements and 10-2 defect levels and -8 defined 8 fault grade vs development time and illustrated -3 for MegaModules, TI provides 3-7 for threshold voltage measurements dedicated control pins 10-6 shared control pins 10-9 generating 12-1 ATE block diagram 12-4 development cycle time and -3 introduction 12-2 path sensitization 11-5 synchronous pattern for use during functional test example 12-3 TDL ATE loads simulation example 12-11
special 12-10
tester period slip 12-5 handing off to TI in TDL format 4-2 highfault grade 11-1 highfaultgrade 3-10 requirements 4-1 responsibilities for providing 4-2 scan path multiple 6-18 simulations 3-11 TDL type descriptions 4-3 test costs and -2 timing 3-11 test periods duration of minimum 12-4 input delay group relationship to illustrated 12-7 test pins boundaryscan architecture 13-3 test procedures performance TDL 12-11 atspeed testing 12-11 pintopin testing 12-11 setup and hold testing 12-11 test program defined 8 test register 8-3 architecture typical illustrated 8-4 bit definitions 8-5 building block illustrated 8-3 described 8-3 test selection codes 8-6 Test Reset boundaryscan architecture test pin 13-3 test selection codes for test register 8-6 test signal generators Johnson counter 5-18
creates 12-6 example 12-15 input delay groups 12-6 output strobe groups 12-9 performance test procedures 12-11 propagation delay measurements, specifying 12-17 quiescent power supply current measurements defined in 12-20 scan 12-19 example 12-19 vectors 12-20 TDLs create ATE loads 12-10 clocks 12-7 output strobe groups
placement example 12-10

precautions
Index
18
Index
shift registers 5-19 test signals injecting 5-3 test vectors 1-2 corresponding logic waveforms and 12-17 dc parametric test resources 13-10 defined 8 described 12-2 DFT and 5-2 input signals defined by 12-6 multiple scan chain designs and 6-14 numbers of minimizing 12-3 output signals defined by 12-6 propagation delay measurements specifying, in ASIC_TEST statements 12-17 quiescent power supply current measurements specifying 12-20 TDL contains 3-12 TEST_REG instructions 13-19 TEST1 test condition 8-8 test register codes 8-6 TP000 bit assignments 8-5 TEST2 test condition 8-8 test register codes 8-6 TP000 bit assignments 8-5 testability ad hoc schemes 5-1 asynchronous circuits 5-7 bidirectional buffers 5-4 counter chains 5-11 counters 5-10 dividers 5-10 gated clocks 5-8 internal clocks 5-9 internal node observability 5-3 Johnson counter test signal generator 5-18 known states 5-5 logic blocks 5-17 multiplexing direct access to logic 5-12 nesting sequential circuits 5-14 reconverging signals 5-16 redundant circuits 5-15
shift register observability obtained from 5-20 shift registers test signal generator 5-19 area impact and -2 introduction 1-1 of logic multiplexing improves 5-13 overlooked, in design process -2 performance impact and -2 principles, applying early in process 1-1 scan designs and 6-2 schemes 1-2 structured 6-1 approaches to 6-2 bus contention scan testing and 6-12 clocked scan flipflop 6-3 edgetriggered flipflop 6-7 flipflop scan design 6-10 LSSD 6-8 multiplexed flipflop 6-5 scan path loading on critical ac path 6-11 scan paths 6-20 testisolatable modules 6-14 testisolation modules multiple scan paths patterns 6-18 testisolation modules 6-14 structured tools choosing 3-7 clocked scan 3-7 LSSD 3-8 multiplexed flipflop scan 3-7 parallel scan chains 3-8 partial scan 3-8 testable defined 7 TESTDATA shift register and 5-19 testers commercial -2 constraints 3-11 described 3-11
Index
19
Index
TTL/CMOS bidirectional buffers vs contentions 12-10 testing approaches to 5-2 ATPG considerations 11-8 chips how done 12-2 introduction to 12-2 parallel 6-14 period slip and 12-4 TESTOUT pin 5-20 tests costs -8 testtime costs -2 TGC1000 NAND tree configurations illustrated 10-7 TGC2000 NAND tree configurations illustrated 10-7 threestate disabling logic 6-12 threestate highimpedance measurements 10-11 threestate logic 12-10 threshold circuitry adding, to circuits not adhering to IEEE Standard 1149.1 10-4 threshold drifts circuit dc leakage current measuring 10-13 TI Customer Design Center, contacting ix time test costs -2 timetomarket -3, -5, -8, 3-9 timing 1-2 BIST_AC TDL verifies requirements 4-4 checks TDLCHKR and 4-4 FUNC_AC TDL verifies requirements 4-4 gated clocks vs edgetriggered clocks 5-8 generators clock, strobe times and 12-3 race conditions in edgetriggered flipflop scan designs 6-7 SCAN_AC TDL verifies requirements 4-4 TMS
boundaryscan architecture test pin 13-3 TO keywords 12-18 toggle states required, for TDL states, for various signal files 10-3 tools design costs and -8 TP000 bit definitions for 8-5 macros GTAP test registers consist of 13-20 test register composed of 8-3 test register building block illustrated 8-3 TP0B0 test register composed of 8-3 trademarks ix tradeoffs -2, -4, -5, -6 TRST boundaryscan architecture test pin 13-3 truth tables 1-2 described 12-2 TST_ENBL circuit as test activation control pin example 13-22 TURNOFF TDL described 4-4 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5
U
undetectable fault defined 8 undetected fault defined 8 unloading IR shiftIR group does 13-6 updateIR group activating IR done by 13-6 user test data register 7-5
Index
20
Index
UTDR described 7-5
W
wafer fabrication defects failures and 11-8 warnings information about vi waveform analyzers ineffective in debugging ASIC systems -4 Williams fault coverage model -5 Motorola, Delco study supports -6 WRITE test condition 8-8
V
vendors design process and -2 VIH/VIL and VOH/VIL test (TAP pins) 13-10 VIH/VIL and VOH/VOL test (TAP pins) 13-16 using boundaryscan architecture and GTAP test register 13-26 VIH/VIL test 13-10 ASIC test selection codes 8-6 using boundaryscan architecture and GTAP test register 13-23 VIH/VIL_CLK_A ASIC test 8-6 VIH/VIL_CLK_B ASIC test 8-6 VIH_VIL TP000 bit assignments 8-5 VIH_VIL CLK SELECT ASIC test selection codes 8-6 TP000 bit assignments 8-5 VIH_VIL TDL described 4-4 input threshold voltage levels 10-4 parametric testing and 10-2 TGC1000 pattern set requirements 4-5 TGC2000 pattern set requirements 4-5 VOH/VOL test 13-10, 13-12 using boundaryscan architecture and GTAP test register 13-23 VOL/VOH ASIC test 8-6 voltage level measurements 10-1 input current 10-12 input threshold using clocked NAND tree 10-4 leakage current 10-13 output 10-10 overview 10-2 threestate highimpedance 10-11
Y
Y TDL character 12-15
Z
Z TDL character 12-15
Index
21
Index
Index
22
Index
Index
23
Index
Index
24
Index
Index
25
Index
Index
26
Index
Index
27
Index
Index
28
Index
Index
29
Index
Index
30
Index
Index
31
Index
Index
32
Index
Index
33
Index
Index
34
Index
Index
35
Index
Index
36
Appendix A
Glossary
A
ACE: ASIC Compiler Environment. The graphical user interface delivery mechanism for submicron gate-array memory compiler elements. ASIC: Application Specic Integrated Circuit. A device designed for a user application, usually by the user. asynchronous logic: A collection of logic elements with the signal timing entirely dependent on the propagation delay of all elements in the signal path. The resulting signal ow timing changes with variations in process control, temperature, and power-supply voltage. ASIC TDL 91: An improved TI TDL format that supports both narrow and wide (SCAN) TDL. Narrow TDL lists the ATE state for all pins in every cycle. Wide or SCAN TDL allows a description of only nonredundant ATE states and pins. ATE: Automated Test Equipment. Machines used to test silicon. ATPG: Automatic Test Pattern Generation. A process by which the vectors required to produce a high-fault coverage for a design are generated by a program. These tools generally require scans in synchronous designs and assume certain scan rules. at-speed testing: Refers to test vectors that target the detection of delay faults. The term usually apllies to test vectors that operate at design frequency or that validate setup conditions. AUTOGEN: A TI software tool that compiles an automated test equipment program (ATE) program from TDL. Automatic Test Pattern Generation: A methodology, using software tools, to generate test patterns. Test patterns attempt to control and observe each circuit node using a stuck-at model.
B
back annotation: The process of updating the design database with actual interconnect delays (as opposed to estimations by design CAD software). The actual delays are calculated after placement and routing, when exact interconnect lengths are known. BIST: Built-In Self-Test. The capability of a product to carry out a functional test of itself. Some support from external equipment may be required. BIST usually involves special hardware in the product to generate input stimuli and to analyze test responses. block: A group of interconnected cells. May contain instances of other blocks. BNF: Backus Naur Form. A description of ASIC TDL 91. BTL: Backplane Transceiver Logic. A form of transmission line driver and receiver circuitry specied by IEEE Std 1149.1. bus: A data distribution path that typically has multiple data receivers and can have multiple data sources. Bus structures must be driven by threestate drivers. The drivers must be capable of disconnecting from the bus, and only one such source can be active at one time. bus contention: If more than one bus driver is active with conicting output levels at the same time, neither driver may be able to assert a true logic level on the bus line. The result could be excessive drive current, undened logic levels, and possible device failure. bus holder: A logic device that prevents a bus from oating if all bus drivers are placed into the high-impedance state. It maintains the last logic state.
C
cell: An individual component of a library (typically a logic gate; for example, a NA210 2-input NAND gate). See macro. CHIPS: Comprehensive Hierarchical Physical Synthesis. TIs submicron gate-array oorplanning tool designed to improve design cycle time by decreasing layout iterations. Includes PRELUDE delay estimation capabilities plus full graphic oorplanning. circuit initialization: A sequence of stimuli that sets internal nodes of a circuit to a predictable known state.
clock skew: The difference in clock edge timing across the chip. Loading and interconnect capacitance cause the active clock edge to be delayed, possibly disrupting critical circuit timing. clocked scan: An edge-triggered scan methodology. The clocked scan ipop has separate clock and data inputs for scan- and system-mode operation. CMOS: Complementary Metal Oxide Semiconductor. A form of digital logic that has the characteristics of low power consumption, wide power supply range, and high noise immunity. combinational fault: A functional fault whose effect on the behavior of the circuit is not affected by the sequence of the input stimuli. controllability: The ability of a node to be established at specic logic states by applying stimuli to the circuits externally accessible nodes. core logic: All logic functions except I/O buffers are core logic. critical path: Any path with special timing requirements.
CTL: CMOS Transceiver Logic. A form of transmission-line driver and receiver circuitry. These circuits allow CMOS devices to communicate in a low-noise, terminated-transmission-line environment.
D
delay fault: A fault in a circuit that causes failure to meet ac specications but might not cause functional failure. design-for-testability feature: Lets you specify a list of placement rules describing the connectivity of any logic path you want to group. design requirements document: A document to guide the product development that states the goals of the design. This type of document usually includes functional description, performance goals, cost goals, testability goals, and quality goals. detectable fault: A functional fault for which a test pattern can be created that always causes the effects of the fault to be observable at an externally accessible node. detected fault: A functional fault that causes effects that are observed at an externally accessible node when the circuit is exercised by the existing test pattern.
Glossary
DFT: Design for Testability. A design goal requiring that each node be both observable and controllable. Failure to achieve this design goal can compromise quality assurance.
E
ECL: Emitter-Coupled Logic. A nonsaturating form of digital logic that eliminates transistor storage time as a speed-limiting characteristic, permitting very-high-speed operation.
F
fault: A defect that can cause a failure in the circuit operation/timing. fault detectability ratio: The ratio of detectable faults to the sum of detectable and undetectable faults. fault grade: A measurement of the efciency of test vectors to detect manufacturing defects in silicon. The fault-grade value is usually presented as a percentage of the stuck-at faults that can be identied using those test vectors. fault grading: The process of determining the test pattern fault coverage of a circuit. fault-tolerant design: A design approach to enhance the ability of a circuit to remain operational after the occurrence of a fault. Fault-tolerance design techniques can impact fault detection. oating bus: Any bus line not driven by an active device is free to assume any voltage level. Circuits with inputs connected to this bus may draw excessive current or otherwise malfunction. oating input: The input of a macro can assume an undened voltage level if it is not driven to a dened logic level. Circuits with oating inputs can draw excessive current or otherwise malfunction. functional fault: A fault that causes improper logical operation of a circuit.
G
GTAP: Generic Test Access Port. The TI ASIC test controller. The GTAP can be instructed to enable or disable any combination of DFT features.
I
I/O: Input/Output. An input/output or bidirectional buffer cell used to connect design interface signals directly to package pins. ICCQ: IDDQ: A TI term for IDDQ. See IDDQ. DC leakage testing looks for abnormally high VCC current that indicates a logic or process defect. Test conditions for IDDQ testing must turn off all circuits that produce dc current in the static state.
J
JTAG: Joint Test Action Group. 1) Committee that established the test access port (TAP) and boundary-scan architecture dened in IEEE Standard 1149.1-1990. 2) Common name for IEEE Std1149.1-1990.
L
LSSD: Level-Sensitive Scan Design. A scan methodology. It is a technique where all logic storage elements in a device are chained together in a dual mode. The rst mode is the normal operation of the device where clocks allow the storage of data in normal system operation. In the second mode, master and slave clocks are used to shift data in and out of the device for testing purposes.
M
MegaModule: ter les. High-complexity macros such as SRAMs, FIFOs, and regis-
multiplexed ip-op scan: Multiplexed ip-op scan design is a scan methodology. It is a technique where all logic storage elements in a device are chained together in a dual mode. A 2:1 multiplexer is placed at the input of the logic storage elements. The rst mode is the normal operation of the device where the multiplexer allows the storage of data in normal system operation. In the second mode, the multiplexer allows the shifting of data in for test purposes. netlist: A description of a logic circuit that names the macros used and describes their interconnection.
Glossary
node: The end-point of a branch in a network or a point at which two or more branches meet.
O
observability: The ability to determine the logic states of an internal circuit node at the circuits externally accessible nodes. open circuit fault: A fault in a circuit that alters the number of nodes by breaking a node into two or more nodes.
P
parametric fault: A fault in a circuit that causes failure to meet ac or dc specications but might not cause functional failure. parametric test: These are electrical tests that evaluate parameters such as dc and ac electrical characteristics ( VIH, IDDQ, VOH, tpd, etc. ). PECL: Pseudo ECL. Logic that is implemented to operate with standard 5V VCC and GND power supplies. PMT: Parallel Module Test. A system of additional logic built into MegaModules for the purpose of enhancing the testability of the circuitry. Package input and output pins are multiplexed with internal test circuitry to minimize the need for package pins dedicated to testing. prelayout simulation: Accomplished as part of verication that the design meets design specications. To be effective, simulation must include circuit evaluation using both minimum and maximum propagation delays. The only unknown is actual interconnect capacitance. Interconnect capacitance is estimated by the design CAD software to give an assumed value.
R
redundant circuit: Deliberate duplication of logical functions to create backup functions that enhance performance or reliability of operation. RTL: Register Transfer Level. A subset of behavioral modeling constructs that can be used to model a circuit at the level of data owing between a set of registers. This level of abstraction typically contains little timing information, except references to a set of clock edges and features.
S
scan path: A shift register made up of the logic storage elements (standalone bit-storage devices). In test mode, the storage elements are connected in a shift register. During normal operation they carry out their normal system functions. The scan path is used to shift test data into the logic storage elements for controllability and to shift out test response data for observability. sequential fault: A functional fault whose effect on the behavior of the circuit is affected by the sequence of the input stimuli. short circuit fault: A fault in a circuit that alters the number of nodes by connecting two or more nodes together. simulation: The process of using workstation software to exercise a logic design. When properly done, simulation veries both circuit timing and logic functionality. state machine: A logic block that can assume any of several output logic states in response to input stimuli. Each logic state is uniquely determined from the previous state and the previous input. stuck-at-0 fault: A fault in a digital circuit characterized by a node remaining at a logic low (0) state regardless of changes in input stimuli. stuck-at-1 fault: A fault in a digital circuit characterized by a node remaining at a logic high (1) state regardless of changes in input stimuli. synchronous logic: Any group of logic storage elements through which the signal ow timing is controlled by the system clock. Clock signals cause data signals to advance from one logic storage element to the next, one element at a time. The resulting signal ow is thus made predictable.
T
testable: An electronic circuit is testable if test patterns can be generated, evaluated, and applied in such a way as to satisfy predened levels of performance dened in terms of fault-detection, fault-location, and testapplication criteria, within a predened cost-budget and timescale. TDL:
Test Description Language. A TI language dening test stimuli as a series of input values and expected output values. The TDL le serves as a source le to program the automated testers used for production test.
Glossary
test pattern: A set of test vectors. test pattern fault coverage: The ratio of the total number of detected faults to the total number of detectable faults. test program: A test pattern and instructions suitable for use on automated test equipment (ATE). A test program can be used to perform functional and parametric (ac, dc, or other) tests. test vector: A single instance of input stimuli and expected output responses.
U
undetectable fault: A functional fault for which no set of functional test vectors can be created that can guarantee that the effects of the fault are observable at an externally accessible node. undetected fault: A functional fault that causes effects that are not observed at an externally accessible node when the circuit is exercised by the existing test pattern.
V
VCC: Positive supply voltage or the voltage required across supply and ground terminals of a TTL or CMOS integrated circuit Positive supply voltage or the voltage required across supply and VSS terminals of a CMOS integrated circuit Ground terminal of a CMOS integrated circuit
VDD:
VSS:

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Preface

Read This First

About This Manual

How to Use This Manual

How to Use This Manual

Glossary Contains important ASIC words, phrases, and software tools

Design for Testability

section name, address

16-bit constant [, shift]

Information About Cautions and Warnings

Information About Cautions and Warnings

Design for Testability

Related Documentation From Texas Instruments

Related Documentation From Texas Instruments

Related Documentation From Texas Instruments

Design for Testability

If You Need Assistance

If You Need Assistance

Design for Testability

Introduction to Design for Testability

Design for Testability

Introduction to Design for Testability

Design for Testability

Reasons for Using Design for Testability

The Need for Testability

The Need for Testability

Design for Testability

Fault Grade Versus Development Time

60 Without DFT Strategies 40

0 Hours Days Weeks Months

Time to Develop Test Patterns

Reasons for Using Design for Testability

Economic Trade-Off for a Testable Design

Without DFT Strategy

With DFT Strategy

Design for Testability

Fault Coverage and Cost of Ownership

Fault Coverage and Cost of Ownership

Reasons for Using Design for Testability

Fault Coverage and Cost of Ownership

Defect Level Versus Fault Coverage

3.41 2.73 2.52 2.02 1.77 1.42 0.53 0.42

2.08 1.38 1.52 1.01 1.06 0.71 0.67 0.45

0.89 0 0.51 0 0.36 0 0.22 0

0.32 0.21 0.11 0

Design for Testability

Fault Coverage and Cost of Ownership

Motorola/Delco Study Results

100000 10000 Defect Level ppm

10 90 99 Fault Coverage % 99.9

Reasons for Using Design for Testability

Fault Coverage and Cost of Ownership

ASIC ppm Versus PCB ppm Rate

ASIC ppm Rate

Goal PCB ppm Rate

Design for Testability

Fault Coverage and Cost of Ownership

System Discovery Site 0

Cost of Defect Discovery Multiplier

Reasons for Using Design for Testability

Fault Coverage and Cost of Ownership

Design for Testability