Welcome to Scribd. Sign in or start your free trial to enjoy unlimited e-books, audiobooks & documents.Find out more
Download
Standard view
Full view
of .
Look up keyword
Like this
24Activity
0 of .
Results for:
No results containing your search query
P. 1
Wipro FPGA Design Flow

Wipro FPGA Design Flow

Ratings:

5.0

(1)
|Views: 894|Likes:
Published by api-26783388

More info:

Published by: api-26783388 on Oct 17, 2008
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

03/18/2014

pdf

text

original

EagleWision FPGA Design
Flow
Wipro Technologies
Innovative Solutions, Quality Leadership
\u00a9 Wipro Technologies
Page :
EagleWison FPGA Design Flow
The FPGA Design Flow is given in the figure below.
:
02of 07
\u00a9 Wipro Technologies
Page :
\u00a9 Wipro Technologies
Page : 03 of 07
Architecture
WIPRO's FPGA Design Centre leverages on domain expertise in telecommunica
tions, networking and embedded systems, to define the functional architecture of

the design. This, coupled with the FPGA /ASIC Design expertise, enables the team
to come out with efficient optimized architecture, which can easily fit into the se
lected FPGA, meeting the timing and other criteria).

Key aspects of this phase include:
!Architectural simulations for proof of concept, performance evaluation and to
gather data for functional definition of architecture and/or high level design
definition
!Definition of FPGA architecture: Data and Control Flow, On-chip buses, Buffering
strategies, Register implementation, clocking and synchronization schemes, IO
definition, functional / physical partitioning, integration of soft/hard IP blocks.
EagleWise ASIC Design Handbook along with ETCH (Early Timing Closure
Hacker.) & FACT (FPGA Area Closure Tracker focusing on Architecture/Design
Optimization techniques catering to FPGA Designs)enables \u201cbest practices\u201d

framework by capturing guidelines on Architecture, design partitioning, RTL coding, low power designs, high performance designs etc. These guidelines enable the chosen architecture to achieve the performance goals with no or

minimum number of iterations.
Part Selection & I/O Planning
Part Selection & I/O Planning at this early stage (after the Architecture phase)
provides necessary input for the board design so that the system design can
proceed parallel.
Key aspects of this phase include:
!Selecting the FPGA device based on Systematic approach. FPGA Device Selection
Guide provides set of guidelines and considerations
!FACT Methodology for controllability over FPGA resources right from architecture

stage. It provides a comprehensive set of area estimation guidelines coupled with a tracker to control FPGA area within budget. It aids the designer with an exhaustive collection of area optimization techniques

!Assigning the I/Os, obeying the electrical DRC and to ease out the Board Layout.
I/O Planning makes use of in-house tools to generate top level RTL with dummy
logic and vendor specific tools, to do the pin assignments and DRC checking.
!Based on the pin assignment, FPGA Schematic Part Symbols are generated
automatically using in-house scripts.
FPGA Configuration Strategy is planned as per the system requirement.
EagleWision FPGA Design Flow
Back to FPGA Design flow

Activity (24)

You've already reviewed this. Edit your review.
1 hundred reads
1 thousand reads
mualos liked this
krishna_p_n liked this
krishna_p_n liked this
rakesh0072 liked this
amittewarii liked this
ajaysimha.vlsi liked this
Ishwar Mathapati liked this
ppxddk liked this

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->