Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword
Like this
7Activity
0 of .
Results for:
No results containing your search query
P. 1
m

m

Ratings:

5.0

(1)
|Views: 1,207|Likes:
Published by api-3704956

More info:

Published by: api-3704956 on Oct 17, 2008
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

03/18/2014

pdf

text

original

 
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABADM.Tech. DIGITAL SYSTEMS & COMPUTER ELECTRONICS 2005/06COURSE STRUCTURE---------------------------------------------------------------------------------------------------------Course No. Subject Contact Hrs. / wk.FIRST SEMESTER
Digital System Design 4VLSI Technology & Design 4Digital Data Communications 4Neural Networks and Applications 4
Elective –I
4Advanced Operating SystemsArtificial IntelligenceNetwork Security and Cryptography
Elective –II
4Advanced Computer ArchitectureHigh Performance TCP/IP NetworksLow Power VLSI DesignHDL Laboratory 3------------------------------------------------------------------------------------------------------------
SECOND SEMESTER
Design of Fault Tolerant Systems 4Image Processing 4Speech Processing
 
4Embedded and Real Time systems 4
Elective-III
4CMOS Analog & Mixed Signal DesignHigh Speed NetworksDSP Processors and Architectures
Elective-IV
4Wireless Communications and NetworksAlgorithms for VLSI Design AutomationSystem Modeling & SimulationSignal Processing Laboratory 3------------------------------------------------------------------------------------------------------------
THIRD & FOURTH SEMESTERS
SEMINARPROJECT
 
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABADM.Tech.(DSCE) I Semester 2005/06DIGITAL SYSTEM DESIGN
 
UNIT I
DESIGN OF DIGITAL SYSTEMS: ASM charts, Hardware description language and control sequence method,Reduction of state tables, state assignments.
UNIT II
SEQUENTIAL CIRCUIT DESIGN: design of Iterative circuits, design of sequential circuits using ROMs and PLAs,sequential circuit design using CPLD, FPGAs.
UNIT III
FAULT MODELING: Fault classes and models – Stuck at faults, bridging faults, transition and intermittent faults.TEST GENERATION: Fault diagnosis of Combinational circuits by conventional methods – Path Sensitizationtechnique, Boolean difference method, Kohavi algorithm.
UNIT IV
 TEST PATTERN GENERATION: D – algorithm, PODEM, Random testing, transition count testing, Signatureanalysis and testing for bridging faults.
UNIT V
FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault detection experiment. Machineidentification, Design of fault detection experiment.
UNIT VI
PROGRAMMING LOGIC ARRAYS: Design using PLA’s, PLA minimization and PLA folding.
UNIT VII
PLA TESTING: Fault models, Test generation and Testable PLA design.
UNIT VIII
ASYNCHRONOUS SEQUENTIAL MACHINE: fundamental mode model, flow table, state reduction, minimalclosed covers, races, cycles and hazards.
TEXTBOOKS
1. Z. Kohavi – “Switching & finite Automata Theory” (TMH)2. N. N. Biswas – “Logic Design Theory” (PHI)3. Nolman Balabanian, Bradley Calson – “Digital Logic Design Principles” – Wily Student Edition 2004.
REFRENCEBOOKS
1. M. Abramovici, M. A. Breues, A. D. Friedman – “Digital System Testing and Testable Design”, JaicoPublications2. Charles H. Roth Jr. “Fundamentals of Logic Design”.3. Frederick. J. Hill & Peterson – “Computer Aided Logic Design” – Wiley 4
th
Edition.
 
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABADM.Tech.(DSCE) I Semester 2005/06VLSI TECHNOLOGY & DESIGNUNIT I
REVIEW OF MICROELECTRONICS AND INTRODUCTION TO MOS TECHNOLOGIES: (MOS, CMOS, BiCMOS) Technology trends and projections.
UNIT II
BASIC ELECTRICAL PROPERTIES OF MOS, CMOS & BICOMS CIRCUITS: Ids-Vds relationships, Thresholdvoltage V
t
, G
m
, G
ds
and W
o
, Pass Transistor, MOS,CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuitmodel,Latch-up in CMOS circuits.
UNIT III
LAYOUT DESIGN AND TOOLS: Transistor structures, Wires and Vias , Scalable Design rules ,Layout Design tools.
UNIT V
 LOGIC GATES & LAYOUTS: Static complementary gates, switch logic, Alternative gate circuits , low power gates,Resistive and Inductive interconnect delays.
UNIT V
 COMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network delay, interconnect design, poweroptimization, Switch logic networks, Gate and Network testing.
UNIT VI
SEQUENTIAL SYSTEMS: Memory cells and Arrays, clocking disciplines, Design ,power optimization, Designvalidation and testing.
UNIT VII
FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods, off-chip connections, High-levelsynthesis, Architecture for low power, SOCs and Embedded CPUs, Architecture testing.
UNIT VIII
 INTRODUCTION TO CAD SYSTEMS (ALGORITHMS) AND CHIP DESIGN: Layout Synthesis and Analysis,Scheduling and printing; Hardware/Software Co-design, chip design methodologies- A simple Design example-
TEXTBOOKS
1. Essentials of VLSI Circuits and Systems, K. Eshraghian et . al( 3 authors) PHI of India Ltd.,20052. Modern VLSI Design, 3
rd
Edition, Wayne Wolf ,Pearson Education, fifth IndianReprint,2005.
REFERENCES
1. Principals of CMOS Design N.H.E Weste, K.Eshraghian, Adison Wesley, 2
nd
Edition.2. Introduction to VLSI Design – Fabricius, MGH International Edition, 1990.
3.
CMOS Circuit Design, Layout and Simulation – Baker, Li Boyce, PHI, 2004.

Activity (7)

You've already reviewed this. Edit your review.
1 hundred reads
1 thousand reads
titun8723 liked this
ramulu_492 liked this
ramulu_492 liked this

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->