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1Activity

Table Of Contents

1.0DEVICE OVERVIEW
1.1New Core Features
1.2Other Special Features
1.3Details on Individual Family Members
2.0OSCILLATOR MODULE
2.6.1 OSCTUNE REGISTER
2.11USB Operation
2.13Fail-Safe Clock Monitor
2.13.1FAIL-SAFE DETECTION
2.13.2FAIL-SAFE OPERATION
2.13.3FAIL-SAFE CONDITION CLEARING
2.13.4RESET OR WAKE-UP FROM SLEEP
3.0MEMORY ORGANIZATION
3.1.1 PROGRAM COUNTER
3.1.2 RETURN ADDRESS STACK
3.1.2.2 Return Stack Pointer (STKPTR)
3.1.2.3 PUSH and POP Instructions
3.1.3 FAST REGISTER STACK
3.2.1 CLOCKING SCHEME
3.2.2 INSTRUCTION FLOW/PIPELINING
3.3Data Memory Organization
3.3.2 BANK SELECT REGISTER (BSR)
3.3.5 SPECIAL FUNCTION REGISTERS
3.3.6 STATUS REGISTER
3.4Data Addressing Modes
3.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET
4.0FLASH PROGRAM MEMORY
4.1Table Reads and Table Writes
4.2.4 TABLE POINTER BOUNDARIES
5.0DATA EEPROM MEMORY
5.2EECON1 and EECON2 Registers
5.6Operation During Code-Protect
5.7Protection Against Spurious Write
6.08 x 8 HARDWARE MULTIPLIER
7.0INTERRUPTS
7.4INTCON Registers
7.12Context Saving During Interrupts
9.0I/O PORTS
10.0TIMER0 MODULE
10.3Prescaler
11.0TIMER1 MODULE
12.0TIMER2 MODULE
13.0TIMER3 MODULE
14.0ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE
14.1.1CCP MODULE AND TIMER RESOURCES
14.2.2TIMER1/TIMER3 MODE SELECTION
14.3.2TIMER1/TIMER3 MODE SELECTION
14.3.4SPECIAL EVENT TRIGGER
Special Event Trigger
14.4.4ENHANCED PWM AUTO-SHUTDOWN MODE
15.0MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
15.2.10BUS MODE COMPATIBILITY
15.3.4CLOCK STRETCHING
FIGURE 15-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
FIGURE 15-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
FIGURE 15-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 15-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
16.0ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
16.1.2.6Receive Overrun Error
16.2Clock Accuracy with Asynchronous Operation
16.3.1AUTO-BAUD DETECT
16.4.1.3Synchronous Master Transmission
17.0ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
17.1.4SELECTING AND CONFIGURING ACQUISITION TIME
17.2ADC Operation
18.0COMPARATOR MODULE
18.5Operation During Sleep
19.0POWER-MANAGED MODES
FIGURE 19-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q2
19.5Exiting Idle and Sleep Modes
20.0SR LATCH
21.0VOLTAGE REFERENCES
21.1Voltage Reference
21.1.5OPERATION DURING SLEEP
22.0UNIVERSAL SERIAL BUS (USB)
VUSB
22.2.2.2Internal Pull-up Resistors
22.2.2.3External Pull-up Resistors
22.2.2.4Ping-Pong Buffer Configuration
22.2.2.5Eye Pattern Test Enable
EQUATION 22-1:ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION
23.0RESET
23.5.2OSCILLATOR START-UP TIMER (OST)
5V
23.6Reset State of Registers
TABLE 23-4:INITIALIZATION CONDITIONS FOR ALL REGISTERS
24.0SPECIAL FEATURES OF THE CPU
24.7Single-Supply ICSP Programming
25.0INSTRUCTION SET SUMMARY
25.2Extended Instruction Set
25.2.1EXTENDED INSTRUCTION SYNTAX
26.0DEVELOPMENT SUPPORT
26.1MPLAB Integrated Development Environment Software
26.5MPLINK Object Linker/ MPLIB Object Librarian
26.8MPLAB REAL ICE In-Circuit Emulator System
26.12MPLAB PM3 Device Programmer
27.0ELECTRICAL SPECIFICATIONS
27.7 Timing Parameter Symbology
VR Voltage Reference Specifications
APPENDIX A:REVISION HISTORY
INDEX
THE MICROCHIP WEB SITE
CUSTOMER CHANGE NOTIFICATION SERVICE
CUSTOMER SUPPORT
READER RESPONSE
PRODUCT IDENTIFICATION SYSTEM
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