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Low-Phase-Noise, Low-Timing-Jitter Design Techniques for

Delay Cell Based VCOs and Frequency Synthesizers
by
Todd Charles Weigandt
S.B. (Massachusetts Institute of Technology) 1991

S.M. (Massachusetts Institute of Technology) 1991

A dissertation submitted in partial satisfaction of the
requirements for the degree of
Doctor of Philosophy

in
Engineering-Electrical Engineering

and Computer Sciences
in the
GRADUATE DIVISION
of the
UNIVERSITY OF CALIFORNIA, BERKELEY

Committee in charge:

Professor Paul R. Gray, Chair
Professor Robert G. Meyer
Professor Paul K. Wright

Spring 1998
Low-Phase-Noise, Low-Timing-Jitter Design Techniques for
Delay Cell Based VCOs and Frequency Synthesizers

Copyright 1998
by
Todd Charles Weigandt

1
Abstract
Low-Phase-Noise, Low-Timing-Jitter Design Techniques for Delay Cell

Based VCOs and Frequency Synthesizers
by
Todd Charles Weigandt
Doctor of Philosophy in Engineering -

Electrical Engineering and Computer Sciences
University of California, Berkeley
Professor Paul R. Gray, Chair

Timing jitter and phase noise are important design considerations in almost
every type of communications system. Yet the desire for high levels of integration in
many communications applications works against the minimization of these, and other,
sources of timing error - especially for systems which employ a phase-locked loop for
timing recovery or frequency synthesis. With the growing interest in high-integration
implementations there has been an increasing demand for fully-monolithic, on-chip
VCO and synthesizer designs. Delay cell based VCOs (ring-oscillators) and delay
chains have been used successfully in many applications, but thermal-noise induced

timing jitter and phase noise have limited their applicability to some systems. Of partic- ular interest are RF frequency synthesizers, used in wireless communications transceiv- ers, which have stringent requirements on oscillator phase noise but stand to bene\ufb01t

greatly from a highly integrated solution.
In this thesis the fundamental performance limits of ring oscillator VCOs and

delay buffers are investigated. The effects of thermal noise in transistors on timing jitter and phase noise in such these circuits is explored, with particular emphasis on source- coupled differential resistively-loaded CMOS delay cell implementations. The relation- ship between delay element design parameters and the inherent thermal noise-induced

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->