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Table Of Contents

1.2.2 Hexadecimal Representation
2.1 Gate Types and Truth Tables
2.2.1 Example: Combining Gates
2.2.2 Gate Interchangeablilty
2.2.3 DeMorgan
2.3 Symbolic Logic
2.4.1 K-map Example 2
2.4.2 K-map Example 3: Full Adder
2.4.3 Making a Multiplier from an Adder
2.5 Multiplexing
3.1 Simple Latches
3.2 Clocked Flip-flops
4.1 Divide by Two Counter
4.2 Asynchronous Counter
4.3.1 Basic Register
4.3.2 Shift Registers
5.1 A/D Resolution
5.2 D/A Conversion
5.3.1 Flash ADCs
5.3.2 Successive Approximation ADCs
5.3.3 Binary Search Example
5.3.4 Single/Dual Slope ADCs
6.1.1 Example: Up/down 2-bit Synchronous Counter
6.1.2 Example: Divide-by-Three Synchronous Counter
7.1 Memory Terminology
7.2 Memory Configuration
7.3.1 Example: Divide by 2 or 3 Counter
7.3.2 Generalization to Microprocessors
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Digital Notes

Digital Notes

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Published by Ranjani GS

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Published by: Ranjani GS on Nov 10, 2011
Copyright:Attribution Non-commercial


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