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Published by terminatory808

Noise limited computational speed

L. Gammaitoni1

1 Dipartimento di Fisica, Universit` di Perugia, I-06123 Perugia, Italy, a and Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, I-06123 Perugia, Italy (Dated: February 1, 2008)

In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold

L. Gammaitoni1

1 Dipartimento di Fisica, Universit` di Perugia, I-06123 Perugia, Italy, a and Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, I-06123 Perugia, Italy (Dated: February 1, 2008)

In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold

Noise limited computational speed

L. Gammaitoni1

1 Dipartimento di Fisica, Universit` di Perugia, I-06123 Perugia, Italy, a and Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, I-06123 Perugia, Italy (Dated: February 1, 2008)

In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold

L. Gammaitoni1

1 Dipartimento di Fisica, Universit` di Perugia, I-06123 Perugia, Italy, a and Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, I-06123 Perugia, Italy (Dated: February 1, 2008)

In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold

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04/16/2014

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Noise limited computational speed

L. Gammaitoni

1

1

Dipartimento di Fisica, Universit`a di Perugia, I-06123 Perugia, Italy,and Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, I-06123 Perugia, Italy

(Dated: February 1, 2008)In modern transistor based logic gates, the impact of noise on computation has become increas-ingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, hasincreased the probability of error due to the reduced switching threshold voltages. In this paper wediscuss the role of noise in a two state model that mimic the dynamics of standard logic gates andshow that the presence of the noise sets a fundamental limit to the computing speed. An optimal

idle time

interval that minimizes the error probability, is derived.

PACS numbers: 05.10.Gg, 89.20.Ff, 85.40.Qx

The role of noise in computation devices has becomeincreasingly relevant both in the quantum[1,2] and in
the classical[3,4] regime. With the present tendency
to scale down CMOS based devices toward the nano-meter region[5,6], the noise immunity in a low energy
dissipation scenario has become the recurring objectiveof signiﬁcant research eﬀorts in this ﬁeld[7,8]. Some au-
thors have focused their attention on the potential role of noise in nanoscale devices where noise driven dynamics[9] has been invoked to explain the experiments and tooptimize future design[10]. In order to address a non-negligible error probability a number of strategies havebeen devised where a probabilistic approach to the com-putational task has been often invoked[11]. In this letterwe focus our attention on the very basic mechanisms of the switch dynamics that are responsible of the function-ing of traditional transistor based logic gates, with theaim of clarifying the impact of noise on computation er-rors.Noise can aﬀect the functioning of computing devicesin a number of diﬀerent ways. To ﬁx our ideas let’s con-sider a simple logic gates that constitute the buildingblock of complex networks aimed at realizing comput-ing tasks in modern electronic devices. Here the noisehas two deleterious eﬀects: ﬁrst, it can interact with anunperturbed static signal causing the loss of informationcarried by the static node of the computational network;second, it can aﬀect the functioning of a switching nodeby altering its dynamical properties (e.g.: slew, delay).In this letter we deal with the second eﬀect. More pre-cisely, we focus our attention on the very basic mech-anism of the switching event in a logic gate. Reducedto the essential this mechanism can be sketched as anoutput change in response to a threshold-crossing event.For the sake of simplicity we consider here the simplerof the various switching computing elements: the LogicInverter or NOT gate. This gate is usually operated as apure switching device, governedby the following rule: theoutput logic state commutes from 1 (or HIGH) to 0 (orLOW) if the input signal crosses from below the upperswitching threshold

b

u

(transition from LOW to HIGH).As shown in Fig.1 (left hand side) a time delay betweeninput and output occurs: before the output signal is sta-ble in the desired logic state, some time is required afterthe application of the input signal. The amount of such adelay, called

propagation delay

,

t

p

, characterizes the dif-ferent

Logic Families

(TTL, CMOS, ECL,...) and rangesbetween few ns and few tens of ns. A signiﬁcant contri-bution to the propagation delay is given by the rise time

t

r

that in turn aﬀects what is usually called the

slew rate

of the device. The separation voltage between the upand down thresholds,

b

u

−

b

d

, depends on the diﬀerent

Families

and ranges from 0

.

7 V in

ECL logic

to around28 V in

relay logic

.A number of diﬀerent noise induced phenomena, rang-ing from switching delays (see e.g.

noise on timing

and

noise-on-delay

eﬀects) to

bit-ﬂip

errors, threaten the cor-rect functioning of threshold-crossing based logic gates.Main physical noise sources being power supply noise,environmental noise and also thermal noise when the de-vices dimensions hit the nanoscale. In order to modelthe dynamical eﬀects of the noise on the switching mech-anism we sketched in ﬁg.1 (right hand side) a commonscenario. Here, the time diagram shows the input andoutput time series for the case where the input signal isaﬀected by noise of intensity comparable with the thresh-old separation. For generality purpose we considered thecase of exponentially correlated, Gaussian distributed,stationary noise with correlation time

τ

and standard de-viation

σ

. This noise is added to the deterministic signalshown in the leftmost part of the ﬁgure and the resultingsignal is presented in the upper diagram. The eﬀect of the noise in the gate response (output time series, lowerdiagram) is twofold: 1) it can initially prevent the inputsignal from crossing the relevant threshold (

b

u

in the ex-ample) postponing in time this event and thus resultingin a longer propagation delay

t

p

(

delayed switching er-ror

). 2) Once the device switching is completed, it mightcause a re-crossing of the opposite threshold (

b

d

in theexample) causing a

bit-ﬂip error

.In the following we will analyze in detail the statisticsof these two events that directly reﬂects into the compu-

2

FIG. 1: Time diagram of a Logic Inverter (NOT gate). Left hand side: input (upper trace) and output (lower trace) time seriesfor the case where there is no noise present at the input. Right hand side: input (upper trace) and output (lower trace) timeseries for the case where the input signal is aﬀected by additive noise. The output time series shows two typical phenomena: 1)a delayed switching due to the trapping eﬀect[17] that introduces a wait time that adds to

t

p

2) at later time

t

r

a re-crossingphenomena resulting in a bit-ﬂip error.

tational error probability.

1)

delayed switching

. The

delayed switching error

isproduced when the NOT gate, expected to be in theLOW state is found instead still in the HIGH state dueto a delayed switch. This error is clearly time dependentand we are interested in estimating how its probabilityevolves with time. In order to have a switch delayed, twoconditions have to be met:

a

) at time

t

=

t

0

, due to the presence of noise,the input signal of amplitude

i

u

that makes the devicecommute from HIGH to LOW cannot reach the switch-ing threshold

b

u

. This happens when

i

u

+

ξ

0

< b

u

, or

ξ

0

< b

u

−

i

u

=

b

e

, where

ξ

0

=

ξ

(

t

0

) is the instantaneousvalue of the noise (a realization of the stochastic process

ξ

(

t

) sampled at

t

=

t

0

). Such an event happens withprobability:

P

1

a

= Φ

b

e

σ

=12(1 + Erf(

b

e

) (1)where Erf(

x

) indicates the

Error-function

and

b

e

=

b

e

/

(

√

2

σ

2

).

b

) At time

t > t

0

the noise is such that the condi-tion

ξ

(

t

)

< b

u

−

i

u

still holds. This second condition issatisﬁed with probability

P

1

b

that can be estimated asfollows[12]. Once the condition

a

) is satisﬁed (

ξ

0

< b

e

)it can take some time before the input signal reaches theupper threshold

b

u

. This delay can be estimated by con-sidering the so-called

First Passage Time

(FPT), i.e. thetime the stochastic process

ξ

(

t

) takes to reach

b

e

(i.e. togo from

ξ

(

t

0

)

< b

e

to

b

e

with absorbing boundary in

b

e

and reﬂecting boundary in

−∞

). This delay is a ran-dom variable

t

whose mean value

< t >

=

T

1

is calledMFPT and whose probability density function

p

1

(

t

P

1

b

coincideswith the probability that in the time interval [

t

0

,t

] therewas no crossing of

b

e

, i.e.:

P

1

b

(

t

0

,t

)

≡

1

−

tt

0

p

1

(

t

)

dt

=

e

−

(

t

−

t

0)

T

1

(2)The relevant time

T

1

T

1

(

b

e

) =

τ N

b

e

−∞

b

e

z

e

−

z

2

+

x

2

(1 + Erf(

x

))

dx dz

(3)Where

N

=

12

(1

−

Erf(

b

e

)).Finally the

delayed switching error

probability is ob-tained by the combination of the two error probabilities:

P

1

(

t

0

,t

) =

P

1

a

P

1

b

= Φ(

b

e

/σ

)

e

−

(

t

−

t

0)

T

1

.

(4)Having obtained the expression for the error probabil-ity

P

1

we can now derive a useful prediction for operatingthe NOT gate in noisy conditions. In Fig.2 the

delayed switching error

probability

P

1

is shown as a function of

t/τ

. As expected this probability decreases with timeand becomes negligible in the long time. If we ﬁx whatwe consider an acceptable error probability

ǫ

, than wecan easily compute a safe

wait time

t

w

after which the

3error probability stays below

ǫ

, i.e.

P

1

< ǫ

when

t > t

w

.The relation between

t

w

and

ǫ

t

w

=

T

1

ln

Φ(

b

e

/σ

)

ǫ

(5)where for simplicity we have assumed

t

0

= 0. Mostnotably, if we are willing to accept an error probability

ǫ

= Φ(

b

e

/σ

) or greater, the wait time

t

w

amounts to zero.

FIG. 2: (Color online) Computational error probability. The

delayed switching error

probability

P

1

is shown as a functionof

t/τ

(red online) together with the bit-ﬂip error probability

P

2

(blue online) and the resulting total error probability

P

e

(black online). Parameter values:

τ

= 10

−

9

s and

σ

= 1V,

i

u

= 4

.

2 V,

b

u

= 4

.

0 V,

b

e

= 0

.

2 V. As an example,an error probability

ǫ

= 0

.

3 line is drawn across the curves.The intercepts at

t

w

and

t

h

respectively are drawn (downarrows). Inset: normalized wait time

t

w

/τ

versus

σ/b

e

fordiﬀerent values of the error probability (from above):

ǫ

=10

−

1

(green),

ǫ

= 10

−

3

(black),

ǫ

= 10

−

5

(red),

ǫ

= 10

−

7(blue). Theoretical predictions (continuous line) are in closeagreement with digital simulation (crosses).

2)

bit-ﬂip

: Operationally, notwithstanding the

delayed switching error

, it would seem that we can still use theNOT gate with a negligible error probability, provided weare willing to wait long enough (longer than

t

w

). Unfor-tunately there is another error that comes into play if wewait too long: the

bit-ﬂip error

. As shown in Fig.1, aftera switch event (HIGH to LOW) is occurred, a new un-wanted switch can occur in the opposite direction (LOWto HIGH), if the noise assumes a value

ξ

(

t

)

< b

d

−

i

u

=

c

e

at a time

t

, while the input signal is still

i

u

. For practicalpurposes also a

bit-ﬂip error

of short duration is deleteri-ous to the signal integrity and can seriously compromisethe functioning of the logic gate. To estimate the

bit-ﬂiperror

probability

P

2

, let’s assume that at

t

=

t

0

there isa switch event (HIGH to LOW), i.e.:

ξ

(

t

0

)

≥

b

e

. We areinterested in computing the time

t

the stochastic process

ξ

(

t

) takes to reach

c

e

(i.e. to go from

ξ

(

t

0

)

≥

b

e

to

c

e

with absorbing boundary in

c

e

and reﬂecting boundaryin +

∞

). This time

t

is a random variable whose meanvalue is

T

2

(MFPT) and whose probability density func-tion

p

2

(

t

) is exponential[12]. For what we said,

P

2

(

t

0

,t

)represents the probability that there was a crossing of

c

e

in the time interval [

t

0

,t

].

P

2

(

t

0

,t

)

≡

tt

0

p

2

(

t

)

dt

= 1

−

e

−

t

−

t

0

T

2

.

(6)The relevant time

T

2

T

2

(

b

e

,c

e

) =

τ N

+

∞

b

e

zc

e

e

−

z

2

+

x

2

(1

−

Erf(

x

))

dx dz

(7)In Fig.2

P

2

is shown as a function of

t/τ

. As expectedthis probability increases with time and approaches unitywhen

t

grows to inﬁnity.For the

bit-ﬂip error

, once we ﬁx an acceptable errorprobability

ǫ

, we obtain a safe

hurry time

t

h

before whichthe error probability stays below

ǫ

. The relation between

t

h

and

ǫ

t

h

=

−

T

2

ln

(1

−

ǫ

)

,

(8)where we have assumed

t

0

= 0.Finally, if we take into account the two errors previ-ously discussed, we are now in position to express thetotal error probability:

P

e

=

P

1

+

P

2

.

P

e

is also shownin Fig.2. It is apparent that

P

e

has a minimum for

t

=

t

m

with

t

w

< t

m

< t

h

. Operatively, if we ﬁx an acceptableerror probability

ǫ

this identiﬁes an idle time interval(

t

is

,t

ie

) of amplitude ∆

T

i

=

t

ie

−

t

is

, where the totalerror probability

P

e

is smaller than

ǫ

. When

T

1

≪

T

2

we can approximate

t

ie

with

t

h

and

t

is

with

t

w

, thus∆

T

i

≃

t

h

−

t

w

. It is worth noticing that one of the con-sequences of this analysis is that

P

e

assumes a minimumvalue identiﬁed by the condition

t

is

=

t

ie

=

t

m

. This im-plies that when operating a logic gates in the presence of noise, the probability of error cannot be made arbitrarilysmall but only as small as

ǫ

m

=

P

e

(

t

m

). Remarkably

ǫ

m

does not depend on the noise correlation time but onlyon the noise intensity[18].The role of noise in computing devices however can alsobe seen from a diﬀerent perspective. Instead of being amere disturbance it can be considered as an essential partin the computing process itself. This is the case for ex-ample, when we consider sub-threshold gate driving, i.e.when

i

u

< b

u

. In the absence of noise no switch is pos-sible and the gate cannot operate. Instead, also a noiseof small intensity can bring (in due time) the input sig-nal above the threshold and thus drive the gate for the

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