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Table Of Contents

CHAPTER 1 INTRODUCTION
1.1 Motivation
1.2 Organization of Thesis
Figure 1.1: Block diagram of a typical Phase Locked Loop (PLL)
CHAPTER 2 NEGATIVE TRANSCONDUCTANCE OSCILLATOR THEORY
2.1 Overview of Oscillator Operation
Figure 2.3: One port view of an oscillator
2.2 LC Oscillator Topologies
2.2.1 Single Transistor Topology
2.2.2 Cross-Coupled Differential Topology
2.2.3 NMOS or PMOS Cross-Coupled Oscillators
2.3.1 Definition of Phase Noise
CHAPTER 3 ON-CHIP INDUCTORS
3.1 Background
3.2 Integrated Inductor Geometries
3.3 Loss Mechanisms in Inductors
3.3.1 Metal Losses
3.3.2 Substrate Losses
3.4 Inductor Model
3.4.1 Series Inductance (LS)
3.4.2 Series Resistance (RS)
3.4.3 Substrate Parasitics (Rsub, Csub)
3.5 Inductor Quality Factor
3.6 Inductor Simulation Tools
3.7 Inductor Design
3.7.1 Design of 4 nH Inductor
3.7.2 Layout of Inductors
CHAPTER 4 VARACTORS
4.1 Background
4.2 MOS Varactor
4.3 Varactor Design
4.4 Simulation of Varactor Characteristics
CHAPTER 5 OSCILLATOR DESIGN
5.1 Background
5.2 Oscillator Design
5.3 Oscillator Simulation
5.4 Layout of the Test Chip
5.5 Test Setup Measurement Configuration
5.6 1.8 GHz VCO
CHAPTER 6 CONCLUSIONS AND FUTURE WORK
BIBLIOGRAPHY
APPENDIX A MATLAB PROGRAM TO COMPUTE INDUCTANCE VALUE
APPENDIX B TECHNOLOGY FILE USED IN ASITIC
APPENDIX C INDUCTOR GEOMETRIES EXPLORED
APPENDIX E SPICE BSIM3 MOS MODEL PARAMETERS
APPENDIX F SPICE BSIM3 MOS MODEL PARAMETERS
APPENDIX G DE-EMBEDDING
APPENDIX H SPICE NETLIST INDICATING EXTRACTED PARASITICS
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ChetanSalimathThesis

ChetanSalimathThesis

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Published by Barry Wang

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Published by: Barry Wang on Nov 13, 2011
Copyright:Attribution Non-commercial

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