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Asic and Fpga Design

Asic and Fpga Design

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Published by: api-3847371 on Oct 18, 2008
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03/18/2014

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EECS 355 ASIC & FPGA Design
1
EECS 355
ASI C & FPGA Design
1
World of Integrated Circuits
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD
FPGA
PAL
PLA
PML
LUT
(Look-Up Table)
MUX Gates
EECS 355
ASI C & FPGA Design
2
Which Way to Go?

Off-the-shelf
Low development cost
Short time to market

Reconfigurability
High performance
ASICs
FPGAs
Low power
Low cost in
high volumes
EECS 355
ASI C & FPGA Design
3
Other FPGA Advantages
\u2022 Manufacturing cycle for ASI C is very costly,
lengthy and engages lots of manpower
\u2013 I t takes ~ 5M dollars to make just one chip
\u2013 I t takes ~ 5M dollars to make 1,000 chips
\u2013 Mistakes not detected at design time have large
impact on development time and cost
\u2013 FPGAs are perfect for rapid prototyping of digital
circuits
\u2022 Easy upgrades like in case of software
\u2022 Unique applications
\u2013 reconfigurable computing
EECS 355
ASI C & FPGA Design
4
FPGA Basics
EECS 355
ASI C & FPGA Design
5
SRAM Switch Technology
Read or Write
Data
Configuration Memory Cell
Routing Connections
EECS 355
ASI C & FPGA Design
6
Programmability
SRAM
SRAM
SRAM
SRAM
SRAM
16
16x1
MUX
output
inputs
Look Up Table
LUT
Programmable
Interconnect
EECS 355 ASIC & FPGA Design
2
EECS 355
ASI C & FPGA Design
7
SRAM Technology
\u2022 Logical configuration is controlled by the
state of the SRAM cell
\u2022 FPGA needs to be configured at power-
on by a separate non-volatile ROM
EECS 355
ASI C & FPGA Design
8
Examples for Connections
EECS 355
ASI C & FPGA Design
9
Programmable Switch Matrix
0/1
0/1
\u2026
\u2026
EECS 355
ASI C & FPGA Design
10
I nterconnect
\u2022Hierarchic
alRouting
Resources
EECS 355
ASI C & FPGA Design
11
Types of Lines
\u2022 Single-length: connects adjacent PSMs
\u2022 Double-length: connects every other PSM
\u2022 Quad-length: traverse four CLBs before passing through
a PSM
\u2022 Long: runs entire chip
\u2013 Using tri-state buffers within the CBLSs, long lines can be
configured as buses
\u2022 Local connections use direct interconnect or single
length lines in order to avoid to many switching points
\u2022 Global Nets: Low skew signal paths used to distribute
high fan-out signals such as clock and reset signals
EECS 355
ASI C & FPGA Design
12
I nside the CLB
\u2022 Many FPGAs look similar
\u2013 But they differ in how Configurable Logic Blocks (CLBs)
are implemented
\u2013 CLB is actually Xilinx terminology
\u2013 Main components in a CLB
\u2022 SRAM array can be used as LUT (Look Up Table) to implement
combinational logic through truth tables
\u2013 Also called Function Generators
\u2022 Fast carry logic
\u2022 D flip-flops
\u2022 Multiplexers to configure the interconnection within the CLB
EECS 355 ASIC & FPGA Design
3
EECS 355
ASI C & FPGA Design
13
Look Up Tables
EECS 355
ASI C & FPGA Design
14
Look Up Tables
SRAM
SRAM
SRAM
SRAM
16
EECS 355
ASI C & FPGA Design
15
Look Up Tables
SRAM
SRAM
SRAM
SRAM
16
16x1
MUX
inputs
EECS 355
ASI C & FPGA Design
16
CLB Organization
\u2022 A CLB can be organized as a more complex logic
block
\u2022 Xilinx FPGAs use two level hierarchy
\u2013 Slice : collection of LUT, D FF, Mux
\u2013 CLB: combination of multiple identical slices
EECS 355
ASI C & FPGA Design
17
Figure 4: 2-Slice Virtex CLB
EECS 355
ASI C & FPGA Design
18
Virtex II Slice (simplified)
Look-up tables LUT F and G can be used to
compute any Boolean function of\u2264 4 variables.
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
G
d
c
b
a
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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->