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FPGA Design Tutorial (Charles Kime & Surin Kittitornkun

FPGA Design Tutorial (Charles Kime & Surin Kittitornkun

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ECE 554 \u2013 Digital Engineering Laboratory
FPGA Design Tutorial
Version 3.1 - Fall 2001
Surin Kittitornkun and Charles R. Kime
Table of Contents
1. Introduction and Preparation\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026
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2. Design Entry\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026.
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3. Functional Simulation\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026...
7
4. Design Synthesis\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026...
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5. Post-Synthesis Simulation\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026
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6. Design Implementation\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026.
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7. Timing (Post Implementation) Simulation\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026
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8. Conclusion\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026.
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9. References\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026..
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Appendixes
A. HDL Design Wizard and Language Assistant\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026.
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B. Syntax checking for HDL Synthesis vs. HDL Simulation\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026...
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C. Incremental Design Synthesis\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026\u2026..
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Changes to V.3.0
- Post-synthesis simulation has been added.
- Flow diagrams have been added.
2
1. Introductions and Preparation
The FPGA design flow can be divided into the following stages:
1. Design Entry
a) Performing HDL coding for synthesis as the target (Xilinx HDL Editor)

b) Using Cores (Xilinx Core Generator)
2. Functional Simulation of synthesizable HDL code (MTI ModelSim)
3. Design Synthesis (FPGA Express)
4. Design Implementation (Xilinx Design Manager)
5. Timing (Post Implementation) Simulation (MTI ModelSim)

This design flow is based on the assumption that the student:
1. is familiar with HDL coding using either Verilog HDL or VHDL. See Appendix A: Design
Wizard and Language Assistant, and
2. recognizes the difference between HDL coding for synthesis and for simulation. See Appendix B:
Syntax checking for HDL Synthesis vs. HDL Simulation.

The final ECE 554 project usually contains a big/complex subsystem, which takes a long time to
synthesize (>10 min.) and is unchanged or infrequently changed during the system debugging loop. See
Appendix C: Incremental Design Synthesis for further details.

Preparation
- Log on an NT workstation (in 3628 Engineering Hall only).
- Create \u201cI:\xilinx\tutorial\mac\u201d and \u201cI:\xilinx\tutorial\cores\u201d directories
- Copy files fromhttp://www.cae.wisc.edu/~ece554/s01/mac and
http://www.cae.wisc.edu/~ece554/s01/coresrespectively.
File name
Detail
Mltring.v
The top most file contains the \u201cmltring\u201d module and other interfaces.
Memctrl.v
A simple memory controller
mac.v
The top-level file contains \u201cmac_test\u201d module. (MAC = Multiply-ACcumulate)
Mltring.ucf
User constraint file contains port names and their corresponding pin location
assignments.
force.do
Script file to simulate \u201cmac.v\u201d in ModelSim (functional)
Timing_force.do
Script file to simulate \u201cmltring.v\u201d in ModelSim (timing)
mult_4x4.*
4-by-4 bit multiplier core: .v for functional simulation, .edn for netlist
reg8b.*
8-bit register core: .v for functional simulation, .edn for netlist
3
2. Design Entry

Since you\u2019re required to do the projects in HDL (hardware description language) only, the HDL
editor is provided. All the keywords are highlighted depending on the file extension either \u201c*.vhd\u201d for
VHDL or \u201c*.v\u201d for Verilog HDL.

\u2022
Using HDL Editor
\u00a7 Open the HDL Editor by double clicking on theHDE.exe icon on the desktop.
\u00a7 Open the top-level file: \u201cmac.v\u201d in \u201cI :\xilinx\tutorial\mac\u201d and try to understand the structure of
the multiply-accumulator. You must be able to draw a simple diagram with some useful details
described by this HDL code and show it to the instructor.
\u00a7 Open \u201cmltring.v\u201d in the same directory and find where the \u201cmac_test\u201d module is instantiated at a
specific line number to the instructor.
\u2022
Using Cores from Core Generator

The pre-designed functional units such as adder/subtractor, multiplier, divider, etc. are available in such a way that they can be customized for a particular use. These functional units are called \u201ccore\u201d. They can be customized and generated using \u201cXilinx Core Generator\u201d which can be used in the following

procedure.
\u2022
Launch Core Generator:
Design Entry
Verilog Coding
HDE.exe
Cores
Core generator
Functional Sim.
ModelSim
Verilog Synthesis
FPGA Express
Implementation
Design Mgr.
Post-Syn. Sim.
ModelSim
Timing Sim.
ModelSim
FPGA Prog.
GXSLoad

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