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Table Of Contents

1.1 VLSI Design
1.2 The VLSI Design Process
1.2.2 Logic Design
1.2.3 Physical Design
1.3 Layout Styles
1.3.1 Full-custom Layout
1.3.2 Gate-array Layout
l.S.4 Macro-cell Layout
Dificulties in Physical Design 23
1.4 Difficulties in Physical Design
1.4.1 Problem Subdivision
1.5 Definitions and Notation
1.5.1 Nets and Nellists
1.5.3 Weighted Nets
1.5.4 Grids, Trees, and Distances
4.9.1 Estimation of Wirelength
4.3.2 Minimize Total Wirelength
4.3.9 Minimize Maximum Cut
4.8.5 Maximize Performance
4.3.6 Other Constraints
4.4 Approaches to Placement
4.4.1 Partition-based Methods
Limitation of the Min-cut Heuristic
4.4.9 Simulated Annealing
4.5.i Artificial Neural Networks
4.5.2 Genetic Algorithm
4.6 Conclusion
4.7 Bibliographic Notes
5.2 Problem Definition
5.3 Cost Functions and Constra~~~s
5.3.1 Placement Constraints
5.3.2 Number of Routing Layers
5.3.3 Geometrical Constraints
5.4 Maze Routing Algorithms
5.4.1 Lee Algorithm
Limitations of Lee Algorithm for Large Circuits
54.5 Further Speed Improvements
Line Search Algorithms 253
5.5 Line Search Algorithms
5.6 Other Issues
5.6.1 Multi Layer Routing
5.6.2 Ordering of Nets
5.6.9 Rip-up and Rerouting
5.6.4 Power and Ground Ro.uting
Other Approaches and Recent Work 267
5.7 Other Approaches and Recent Work
5.8 Conclusions
5.9 Bibliographic Notes
6.1 Introduction
6.2 Cost F'unctions and Constraints
6.3 Routing Regions
6.4 Sequential Global Routing
6.5 Integer Programming
6.6 Global Routing by Simulated Annealing
6.6.1 The First Stage
6.6.2 The Second Stage
Hierarchical Global Routing 313
6.7 Hierarchical Global Routing
Other Approaches and Recent Work 315
6.8 Other Approaches and Recent Work
6.9 Conclusions
7.1 Introduction
7.2 Problem Definition
'7.2.1 constrain^ Graphs
7.3 Cost function and Constraints
Approaches lo Channel Routing 333
7.4 Approaches to Channel Routing
7.4.1 The Basic Left-Edge Algorithm
7.4.2 Dogleg Algorithm
7.4.5 Switchbox Routing
7.5 Other Approaches and Recent Work
7.6 Conclusions
7.7 Bibiiographic Notes
8.1 Introduction
8.1.2 Structural Level
8.1.8 Physical Level
8.2 Layout Generation
8.2.2 Gate-matrix Methodology
8.3 S tandard-cell Generation
Optimization of Gate-Matrix Layout 397
8.4 Optimization of Gate-matrix Layout
Programmable Logic Arrays 405
8.5 Programmable Logic Arrays
8.6 Other Approaches and Recent Work
8.7 Conclusion
8.8 Bibliographic Notes
9.1 Introduction
9.1.1 Capabilities of Layout Editors
9.1.2 Inlroduction to Magic Layout System
Layout Compaction 441
9.2 Layout Compaction
9.2.1 Compaction Algorithms
9.2.2 Horizontal Virteaf Grid Compaction
9.3 Other Approaches and Recent Work
9.4 Conclusion
9.5 Bibliographic Notes
A.l Graph Theory
A.2 Complexity of Algorithms
A.2.1 Big-Omega Notalion
A.2.9 Big-Theta Notation
A.3 Hard Problems vs. Easy Problems
A.9.1 NP-complete Pyoblems and Reduction
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Vlsi Physical

Vlsi Physical

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Published by: Shaik Mohammed Naveed on Dec 02, 2011
Copyright:Attribution Non-commercial


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