4-Bit ALU

Specifications
Functionality: AND, OR , XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 m 400m

Prepared by: Christie Ma, Manjul Mishra, Ka Yung Presented to : Dr. David Parent Date: 7th May, 2003

Highlights
Introduction- How does the circuit work Approach for the design Individual blocks AND gate, OR gate, XOR gate, Full Adder, and 4-to-1 MUX Wiring of 1-bit and 4-bit ALU Verification of functionality test vectors Post extracted simulation with propagation delay Power consumption Conclusions

Circuit Functionality
S1
A0 B0 A0 B0

S0

A0 B0
A0 B0 C0

4:1 MUX

F0
Control signal S1 S0 Operation

ADD Cout0
Block diagram for 1-bit ALU

A and B

0 1 1

1 0 1

A or B A xor B A add B
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Block Diagram for 4-Bit ALU

S1 S0

A0 B0 C0
A1 B1

1-bit ALU
Cout0

F0

1-bit ALU
Cout1

F1

A2 B2

1-bit ALU
Cout2

F2

A3 B3

1-bit ALU
Cout3

F3

Design Flow
Sketch schematic according to Boolean Algebra Find Euler Path Draw stick diagram Verify functionality Calculate Wn Wp for each block Run DRC, LVS, extracted simulation for 4-bit ALU Measure power used

Measure delay time

Run Spice simulation to fix Wn, Wp

Draw schematic for each block Layout for small blocks Route four 1-bit ALUs to form a 4-bit ALU Run DRC, LVS, extracted simulation for 1-bit ALU

Run DRC, LVS, extracted simulation for small blocks Route small blocks together to form 1-bit ALU
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AND2 schematic
Wp=5.4 m

Wn=15.15 m

AND2 Layout & LVS Report

OR2 Schematic

Wp=8.4m

Wp=5.85 m

Wn=10.2 m

Wn=14.25 m

OR2 Layout & LVS Report

XOR2 Schematic

Wp=15.9m

Y = A xor B = AB + AB = (AB + AB) AOI21 = (AB + C) if C = AB C = (A+B) C = A nor B

Therefore, using one AOI21 and one NOR gate, we can implement XOR gate without using any INV.
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Wn=23.4m

XOR2 Layout & LVS

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Full Adder Schematic

Cout=AB+ACin+ BCin = AB+Cin(A+B) Sum= ABCin + (A+B+Cin)Cout

Wp=6.15m Wn=3.6m
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Full Adder Layout

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Full Adder LVS Report

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4-to-1 MUX schematic

F0= S1 S0Y00+ S1S0Y01 +S1S0Y10+S1S0Y11 F0= S0(S1Y00+S1Y10)+S0(S1Y01+S1Y11) Wp=9.9 m 2-to-1 MUX 2-to-1 MUX

2-to-1 MUX Therefore, we need three 2-to-1MUXs to build a 4-to-1 MUX

2-to-1 MUX schematic Wn=6.45 m

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4-to-1 MUX schematic (cont.)

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4-to-1 MUX Layout

One 2-to-1 MUX

Three 2-to-1 MUXs to form a 4-to-1MUX

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4-to-1 MUX LVS Report

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1-bit ALU schematic

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1-bit ALU Layout

AND

OR

XOR ADDER 4-to-1 MUX

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1-bit ALU LVS Report

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4-bit ALU Schematic

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4-bit ALU Layout

Area = 197m 347.4 m

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4-bit ALU LVS Report

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Test Vectors
Walking ones for inputs on all operations (1-8) Testing for Cout and Cin (9, 10)

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Simulation Results
A3 = 1, Ax = 0, Bx = 0

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Simulation Results
A2 = 1, Ax = 0, Bx = 0

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Simulation Results
A1 = 1, Ax = 0, Bx = 0

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Simulation Results
A0 = 1, Ax = 0, Bx = 0

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Simulation Results
B3 = 1, Ax = 0, Bx = 0

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Simulation Results
B2 = 1, Ax = 0, Bx = 0

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Simulation Results
B1 = 1, Ax = 0, Bx = 0

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Simulation Results
B0 = 1, Ax = 0, Bx = 0

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Simulation Results (Cout)

A3 = 1, B3 = 1

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Simulation Results (Cin)

C0 = 1, A0 =1, B0 =1

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Propagation Delay for AND gate

274.1ps

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Propagation Delay for OR gate

237.9 ps

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Propagation Delay for XOR gate

226.7ps

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Propagation Delay for Full Adder

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495.5 ps

Propagation Delay for 4-to-1 MUX

330.4 ps

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Propagation Delay For 4-bit ALU

(when S1=S0=0 AND Operation)

t F2 = 705.9ps

t F3 = 698.2ps

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Propagation delay For 4-bit ALU

( when S1=0, S0=1 OR Operation)

t F2 = 693.8 ps

t F3 = 673.2 ps

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Propagation Delay for 4-bit ALU

(when S1=1, S0=0 XOR Operation)

t F2 = 661.2 ps

t F3 = 678.7 ps

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Propagation Delay for 4-bit ALU

(when S1=S0=1 Add Operation)

t F0 = 987.9 ps

t F1 = 1.383 ns

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Propagation Delay for 4-bit ALU

(when S1=S0=1 Add Operation)

t F2= 1.484 ns

t F3 = 1.949 ns

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Propagation Delay for 4-bit ALU

(when S1=S0=1 Add Operation)

t Cout3 = 1.339 ns

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Power Simulation for 4-bit ALU

(when S1=S0=0 AND Operation)

Power = 26.8 mW

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Power Simulation For 4-bit ALU

( when S1=0, S0=1 OR Operation)

Power = 26.69 mW

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Power Simulation for 4-bit ALU

(when S1=1, S0=0 XOR Operation)

Power = 21.38mW

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Power Simulation for 4-bit ALU

(when S1=S0=1 Add Operation)

Power = 23.35mW

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Conclusions
We meet the specifications!
Specifications Largest Propagation delay Maximum Power Area 2.0 ns 30 mW 200 m 400m Our circuit 1.95ns 26.8 mW 197 m 347.4m

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