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Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010 Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library
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Outline & Introduction, Initial Assessment of students, Digital design methodology & design flow Combinational Logic Review + Verilog Introduction, Combinational Building Blocks in Verilog Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS), Sequential Logic in Verilog Synthesis of Blocking/Non-Blocking Statements
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Micro-Architecture
Optimizing Speed
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Optimizing Area
FIR Implementation
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CDC Issues
Fixed-Point Arithmetic
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Adders & Fast Adders Multi-Operand Addition Multiplication , Multiplication by Constants + BOOTH Multipliers CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW
DFG representation of DSP Algorithms, Iteration Bound & Retiming Unfolding Look ahead transformations Course Review & Project Presentations Project Presentations
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Suggested Reading
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Sequential Logic
Section 3.1-3.3
Storage Elements
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NOR
0 0 1 1 x 0
Feedback structure of cross coupled Nor/Nand Gates Two Stable outputs depending on S & R Note: Q & Q are not logical complements Problem
When S=R=1 Transition from 11 to 00 causes race condition (oscillations)
SR Latch
NOR 0 0 1 1 x 0 1
0 0
0
0
1 1 Prev. Values 1 0 0 0
1 0 0 0 0 1
1
1 0 1 0 0 0 0 1
0
1 0
0
0 1
1
0 0
0 0 1
Ideally the oscillations never stop Practically due to gate delays oscillations will come to halt
0 0
0 1
0 0 1
1 0 0
Q Q Assignment: Simulate the SR latch with different gate delays (2 different cases). Apply a sequence of SR values to demonstrate the race condition. Case a: Equal Gate Delays Case b: Experiment with such a value of gate that demonstrates how the oscillation may end due to different gat delays LMS + Print of timing diagrams http://www.verilogtutorial.info/chapter_2.htm
Non Transparent:
Data input
Reset input connected with inverted Data (Set) input Gate delays can still cause race condition (S=R=1) Latch is transparent to input only when Enable is set
Transparent
S D=R
En
Clock Signal
elements that can update value only at a
clock
sequential circuit (or storage element) that does not uses clock
D E
D E
D E
D E
Clk
How many D-Latches the data will pass through --- while the clock is high
Clk-A Clk-B
SR Latch
Race Conditions
Simple D-Latch
Gate delays can still cause race condition
Transparent D-Latch
Defining the length of enable signal
Register
Multiple parallel D Flip Flops
D Latch in Verilog
(Asynchronous Sequential Logic)
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module d_latch ( input E, input DATA, output reg Q, ); always @ (E or DATA) begin if (E == 1'b1) Q <= DATA; end // End Latch endmodule
module d_latch ( input E, input reset, input DATA, output reg Q, ); always @ (E or DATA or rst_n) Begin if (~rst_n) begin Q<= 1b0 end else if (E == 1'b1) begin Q <= DATA; end end // End Latch endmodule
Most logic families can sink more current than they can source, so fanout issues increases with active high resets !
module d_register
( input CLK, input DATA, output Q, reg Q ); always @ (posedge CLK) begin: Q <= DATA; end endmodule
Rule for sensitivity list: When one item in the list has an edge qualifier all items in the list must have edge qualifie as well
Clock is not a normal signal Not to be treated like a normal reg/wire Code
timescale 1ns/1ns define PERIOD 5 // 100MHz clock reg clk; initial clk = 1b0; always @ (clk) #PERIOD clk = ~clk; initial #1000 $finish;
Example : `timescale 1 ns / 10 ps
Indicates delays are in 1 nanosecond units with 2 decimal points of precision (10 ps is .01 ns).
The Verilog hardware description language, Volume 1 By Donald E. Thomas, Philip R. Moorby
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We must reset all the feedback registers in the design. Example Code
Reset
initial begin
Coding Guideline
ALWAYS RESET Feedback Registers else there shall be uncertainties in your design !
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[SHO]
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Distributed RAM
Custom Memories created using LUT (for Xilinx) Good for storing small amounts of data, making registers, shift registers, etc. Dedicated, configurable memory with address, data, and control ports. For large data storage
For larger memory; MUST use BRAM else the synthesizer will consume logic area of FPGA meant for your actual LOGIC design.
Block RAM
TIP
Consists of 16 kbits, blocks (16k single bits, 8k 2 bit words, up to 512 36-bit words) Blocks can be chained together to form large memories
Register File
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We need to have an addressable Register File May be synthesized as Flip Flops or Distributed RAM Depending standard or non-standard accessing ! Not used for mass storage because they occupy significantly more silicon area than compiled memory
Look
Accessing 3D Array
d[i1][i2][i3]
http://www.sutherland-hdl.com/papers/2000HDLCon-paper_Verilog-2000.pdf
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module blockingnonblocking ( output reg out, input clk, in1, in2, in3); reg logicfun;
always @(posedge clk) begin logicfun <= in1 & in2; out <= logicfun | in3; end endmodule
In the implementation shown in Figure 12.9,both the signals logicfun and out are ip-ops, and any changes on in1 or in2 will take two clock cycles to propagate to out.
Blocking Statement
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Future operations are blocked until current operation has been completed. Behaviour: All future operations are under the assumption that all previous operations have completed and all variables have been updated
Blocking Statement
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Future operations are blocked until current operation has been completed. Behaviour: All future operations are under the assumption that all previous operations have completed and all variables have been updated
we force the out register to be updated before logicfun, which forces a 2-clock cycle delay for the inputs in1 and in2 to propagate to out.
Posedge/negedge clk is must for generating registers Blocking statements CAN result into registers if used with edge triggered clock BUT Blocking statements SHOULD NOT be used for generating sequential logic In blocking statements order is important
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always @ (b) Begin z = b; end always @ (posedge c) Begin z = b; end always @ (posedge c) Begin r = b; s=r; z = s; end always @ (posedge c) Begin r = b; z = s; s=r; end
Use blocking assignments to model combinatorial logic Use non-blocking assignments to model sequential logic (Also Latches) Never mix blocking and non-blocking assignments in one always block Think HARDWARE
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This Lecture
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Data_in
D Q D Q D Q D Q
Data_out
clock reset
module Shift_reg4 ( output Data_out, input Data_in, input clock, input reset); reg [3: 0] Data_reg; assign Data_out = Data_reg[3]; always @ (negedge reset or posedge clock) begin if (reset == 1'b0) Data_reg <= 4'b0; else Data_reg <= {Data_reg[2:0], Data_in}; end endmodule
One to Many Test Pattern Generators / Output Response Analyzers is better over Data Encryption Many to One Considered efficient than counters High Speed Memory Addressing when order is not important !
Characteristic polynomial
Defined by
XOR positions Deg. of polynomial = No. of FF For a degree 4 LFSR with all possible connections P(x) = x4+x3+x2+x+1
Always present terms: Primary Feedback (x4) &
Principle Input (1 = x0 )
Primitive Polynomials: Ensure all possible cases <But one less >
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Registers are preloaded with an initial seed Taps Coefficients: C1, C2, C3,.., CN
C0=1
Autonomous LFSR
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LFSR Taps/Coefficients
1,2,4,5,7,8,10,11,12,16,22,23,26,32
Using LOOPs
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Useful for writing compact systematic code that is easy to be de-bugged Loops available: Repeat, While & For Loop
Syntax
Statement_for_exeecution
its a variable, the size of the loop can not be determined statically and thus the loop may not be synthesize
yOut = 8'b00000000;
case (aIn) 3'b000 : 3'b001 : 3'b010 : 3'b011 : 3'b100 : 3'b101 : 3'b110 : 3'b111 : endcase end endmodule yOut[0] = 1'b1; yOut[1] = 1'b1; yOut[2] = 1'b1; yOut[3] = 1'b1; yOut[4] = 1'b1; yOut[5] = 1'b1; yOut[6] = 1'b1; yOut[7] = 1'b1;
module CombinationalCircuit_TB; reg a,b,d,c; wire y; // Instantiate the device-under-test CombinationalCircuit DUT ( .a(a), .b(b), .c(c), .d(d), .y(y) ); // Declare loop index variable integer k; // Apply input stimulus initial begin {a,b,c,d} = 0; for (k=0; k<=16; k=k+1) #5 {a,b,c,d} = k;
module CombinationalCircuit (a,b,c,d,y); input a,b,c,d; output y; reg y; always @ (a or b or c or d) y <= (a==0) ? (a & b & c) : (a ^ b ^ c); endmodule
$finish;
Modelling Digital Machines with Repetitive Algorithms Repeat, While & For Loop
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[CIL]
Do not put a semicolon after for loop Do not use same control variable for multiple loops Use int for control variable
3 Articles related to LFSR by Clive Maxfield Good discussion on Blocking/Non Blocking Statement
Nonblocking
Assignments in Verilog Synthesis, Coding, Styles That Kill!, Clifford E. Cummings Sunburst Design, Inc.
All these shall be uploaded to LMS. Please let me know if this does not happens
Questions.