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ADSD Fall2011 06 Optimizing Area

ADSD Fall2011 06 Optimizing Area

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Published by Rehan Hafiz

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Published by: Rehan Hafiz on Dec 29, 2011
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Dr. Rehan Hafiz
Lecture # 06
Course Website for ADSD Fall 2011
Lectures: Tuesday @ 5:30-6:20 pm
Friday @ 6:30-7:20 pm
Contact: By appointment/Email Office: VISpro Lab above SEECS Library 
Acknowledgement: Material from the following sources has been consulted/used in theseslides:1.[CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti2.[SHO] Digital Design of Signal Processing System by Dr Shoab A Khan3.[STV] Advanced FPGA Design, Steve Kilts4.Some slides from : [ECEN 248 Dr Shi]
1 Introduction Outline & Introduction, Initial Assessment of students, Digital designmethodology & design flow
2 Verilog+Combinational LogicCombinational Logic Review + Verilog Introduction, Combinational BuildingBlocks in Verilog
3 Verilog + Sequential Logic Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS),Sequential Logic in Verilog
4 Synthesis in Verilog
Synthesis of Blocking/Non-Blocking Statements
5 Micro-Architecture<Micro-Coded-Machines>
Design Partitioning + RISC Microprocessor + Micro architecture Document 
6 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency, Timing]
7 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]
8 FIR Implementation
FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs
10 CDC Issues
Cross-Clock Domain Issues & RESET circuits
11 Fixed-Point Arithmetic
 Arithmetic Operations: Review Fixed Point Representation
12 Adders
 Adders & Fast Adders Multi-Operand Addition
Multiplication , Multiplication by Constants + BOOTH Multipliers
13 CORDIC CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW14 AlgorithmicTransformations forSystem Design
DFG representation of DSP Algorithms, Iteration Bound& Retiming
15 Algorithmic
Look ahead transformations
16 Project Course Review & Project Presentations17 Project Project Presentations

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