A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

AbstractA fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation technique is proposed in this paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. To verify the proposed algorithm and architecture, the ADPLL design is implemented by SMIC 0.18- m 1P6M CMOS technology. The core size of the ADPLL is 582.2 m 343 m. The frequency range of the ADPLL is from 4 to 416 MHz. The measurement results show that the ADPLL can achieve a frequency locking in two reference cycles when locking to 376 MHz. The corresponding power consumption is 11.394 mW. Index Terms All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), feed-forward compensation technique, frequency divider.

VLSI implementation of Configurable Prototyping Platform for Multi-Project System on- a-Chip Abstract This paper presents a configurable CONCORD platform for Multi-Project System-on-aChip (MP-SoC) implementation. The multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. A configurable SoC prototyping platform CONCORD is created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eight SoC projects sharing the common platform.

Design of Low Power Consumption in Cymometers Based on FPGA Abstract The design mainly focused on low power consumption concept in every digital systems .In this project we are designing digital cymometers circuit implementation plan. It is based on the most practical digital system simulation VHDL language. Compare to the other Cymometer ,it have a lot of advantages: It can measure the frequency of square wave signal, and show the frequency control with a digital display tube; By changing the program to reach the purpose of expanding measuring range; It also set up a range status display signal, when it excess the maximum range, it will alarm. Due to the power consumption or controlling module the system is capable of monitoring and detecting the required signal and make the entire device to sleep mode in case of any un desired signal or if there is no availability of signal. Designing the circuit with FPGA make the system more accuracy and reliable. The project is designed using VHDL language and the simulation is through Modelsim simulator.

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs Abstract : Power consumption is dramatically increasing for Static Random Access Memory Field Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new CAD tools are needed. Clock-gating methodologies have been applied in low power FPGA designs with only minor success in reducing the total average power consumption. In this paper, we developed a new structural clock-gating technique based on internal partial reconfiguration and topological modifications. The solution is based on the dynamic partial reconfiguration of the configuration memory frames related to the clock routing resources. For a set of design cases, figures of static and dynamic power consumption were obtained. The analyses have been performed on a synchronous FIFO and on a r-VEX VLIW processor. The experimental results shown that the efficiency in the total average power consumptions ranges from about 28% to

39% with respect to standard clock-gating approaches. Besides, the proposed method is not intrusive, and presents a very limited cost in term of area overhead.

Low-power FPGA-based display processing module for head-mounted displays Abstract: In this paper, two low-power architectures for display processing specifically for headmounted displays are presented. The proposed solutions are implemented in an FPGAbased platform and are analyzed in terms of power consumption, area, flexibility for further improvement. The results are compared with an existing hardware solution.

An Efficient Distributed Arithmetic based VLSI Architecture for Discrete cosine transform in image processing Discrete cosine transform (DCT) is widely used in image and video compression standards. This paper presents distributed arithmetic (DA) based VLSI architecture of DCT for low hardware circuit cost as well as low power consumption. Low hardware cost is achieved by exploiting redundant computational units in recent literature. A technique to reduce error introduced by sign extension is also presented. The proposed 1-D DCT architecture is implemented in both the Xilinx FPGA and Synopsys DC using TSMC CLN65GPLUS 65nm technology library. For power and hardware cost comparisons, recent DA based DCT architecture is also implemented. The comparison results indicate the considerable power as well as hardware savings in presented architecture. 2-D DCT is implemented using row column decomposition by the proposed 1-D DCT architecture.

FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression Abstract

Two dimensional DCT takes important role in JPEG image compression. Architecture and VHDL design of 2- D DCT, combined with quantization and zig-zag arrangement, is described in this paper. The architecture is used in JPEG image compression. DCT calculation used in this paper is made using scaled DCT. The output of DCT module needs to be multiplied with post-scaler value to get the real DCT coefficients. Postscaling process is done together with quantization process. 2-D DCT is computed by combining two 1-D DCT that connected by a transpose buffer. This design aimed to be implemented in cheap Spartan-3E XC3S500 FPGA. The 2-D DCT architecture uses 3174 gates, 1145 Slices, 21 I/O pins, and 11 multipliers of one Xilinx Spartan-3E XC3S500E FPGA and reaches an operating frequency of 84.81 MHz. One input block with 8 x 8 elements of 8 bits each is processed in 2470 ns and pipeline latency is 123 clock cycles