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VHDL Reference

VHDL Reference

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Published by: Islam Sehsah on Dec 31, 2011
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E&CE 327: Digital Systems EngineeringCourse Notes(with Solutions)
Mark Aagaard2011t1–WinterUniversity of WaterlooDept of Electrical and Computer Engineering
 
Contents
I Course Notes 1
1 VHDL 3
1.1 Introduction to VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.1 Levels of Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.2 VHDL Origins and History . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1.3 Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1.4 Synthesis of a Simulation-Based Language . . . . . . . . . . . . . . . . . 71.1.5 Solution to Synthesis Sanity . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.6 Standard Logic 1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2 Comparison of VHDL to Other Hardware Description Languages . . . . . . . . . 91.2.1 VHDL Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.2.2 VHDL Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.2.3 VHDL and Other Languages . . . . . . . . . . . . . . . . . . . . . . . . . 101.2.3.1 VHDL vs Verilog . . . . . . . . . . . . . . . . . . . . . . . . . 101.2.3.2 VHDL vs System Verilog . . . . . . . . . . . . . . . . . . . . . 101.2.3.3 VHDL vs SystemC . . . . . . . . . . . . . . . . . . . . . . . . 101.2.3.4 Summary of VHDL Evaluation . . . . . . . . . . . . . . . . . . 111.3 Overview of Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.3.1 Syntactic Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.3.2 Library Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.3.3 Entities and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.3.4 Concurrent Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.3.5 Component Declaration and Instantiations . . . . . . . . . . . . . . . . . . 161.3.6 Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.3.7 Sequential Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.3.8 A Few More Miscellaneous VHDL Features . . . . . . . . . . . . . . . . 181.4 Concurrent vs Sequential Statements . . . . . . . . . . . . . . . . . . . . . . . . . 181.4.1 Concurrent Assignment vs Process . . . . . . . . . . . . . . . . . . . . . . 181.4.2 Conditional Assignment vs If Statements . . . . . . . . . . . . . . . . . . 181.4.3 Selected Assignment vs Case Statement . . . . . . . . . . . . . . . . . . . 191.4.4 Coding Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.5 Overview of Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.5.1 Combinational Process vs Clocked Process . . . . . . . . . . . . . . . . . 221.5.2 Latch Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23i

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