COURSE E3-327,GROUP 2 REPORT NO.

2, NOVEMBER 2009

Fully Depleted SOI MOSFET Fabrication and Characterization

Abheek Bardhan, Arjun Shetty, Arun Mahodaya, Pradeep Dixena, Pramod M, Ramachandran R

L IST OF S YMBOLS
VGf VGb VF B VT hf VT hb NA COXf COXb Cdep
Si OX

tOXf tOXb tSi sf sb ni t qB Wdep q

Voltage applied at the front gate Voltage applied at the back gate Flat band voltage Threshold voltage of front gate Threshold voltage of back gate Acceptor doping concentration Oxide capacitance due to front oxide Oxide capacitance due to back oxide Depletion capacitance of Silicon Permittivity of silicon Permittivity of dielectric thickness of front oxide thickness of back oxide thickness of silicon Surface potential of front channel Surface potential of back channel Intrinsic carrier concentration of silicon Voltage equivalent of temperature Fermi level offset from the intrinsic level Depletion width in silicon Electron charge

Parameter SOI Thickness Doping Type Doping Concentration Doping Material Crystal Orientation Buried oxide thickness Handle wafer orientation

Thin SOI 200 P 51014 Boron <100> 1000 <100>

Thick SOI 1000 P 51014 Boron <100> 1000 <100>

Units nm cm3 nm -

TABLE I: SOI wafer parameters

I. I NTRODUCTION EVICE scaling in bulk-CMOS for long time has enabled the miniaturization as predicted by the Moores law. We have now come up to a stage where further device scaling down below 100 nm is becoming difcult to achieve and the advantages of scaling are becoming overshadowed by the disadvantages. CMOS scaling to nanometer scales has resulted in increased leakage currents, higher parasitic effects, increased process variabilities, degraded sub-threshold slopes, higher electric elds and hence its repercussions and various other issues. SOI technology is seen as a solution to most of the issues in bulk-CMOS. Silicon on insulator as the name suggests has a thin Si-layer over a substrate with an insulating layer separating the two. This feature gives SOI its various advantages like high speed, low power operation, lower threshold slopes lower electric elds, immunity to latch-up, lower parasitic to ground etc.

1) Partially Depleted : In this type of SOI MOSFET, the maximum depletion width is lesser than the thickness of SOI when the channel is inverted. The analysis of this MOSFET is similar to bulk MOSFET. It has an advantage over bulk MOSFET, that there is no leakage and latch up problems. It is shown in Fig. 1(a). 2) Fully Depleted : In this type, the doping and the thickness of the SOI is varied such that the SOI is fully depleted when the channel is inverted. The maximum depletion width is greater than the thickness of the SOI. The threshold voltage depends on the potential of the back channel. If the potential of the back channel is varied such that it follows the potential of the front channel, then the threshold voltage will be smaller than the bulk MOSFET and the sub-threshold slope will be close to ideal value as shown in Fig. 1(b). The variation of surface potential for a fully depleted MOSFET for different back gate bias is shown in Fig. 1(c)-(e). The aim of this lab experiment was to fabricate and characterize fully depleted SOI MOSFETs with different SOI thickness. This report is organised as follows. Sec. II details the fabrication steps of SOI MOSFET. Sec. III describes the different measurement techniques for characterization. I-V transfer and output characteristics of transistors are obtained for different bias conditions and are shown in Sec. IV. The results are discussed in Sec. V and Sec. VI concludes this report. II. FABRICATION S TEPS SOI MOSFETs are fabricated with SOI wafers. The parameters of starting SOI wafers are listed in Tab. I. The initial material taken are the 2 inch pieces of <100> prime quality SOI wafers. The fabrication steps for the two wafers are shown in Fig. 2. After the growth of thin oxide, (SiO2 ) are annealed as described in Sec. II-C. The nal step of fabrication involves forming gas annealing described in Sec. II-H.

A. Types of SOI MOSFETs The operation of SOI can be classied into two categories,
Abheek and Arjun are with the Department of NIS, IISc, Bangalore Arun Mahodaya, Pradeep Dixena, Pramod M, Ramachandran R are with Department of Electrical and Communication Engineering, IISc, Bangalore. e-mail: nanofabiisc@googlegroups.com

COURSE E3-327,GROUP 2 REPORT NO. 2, NOVEMBER 2009

Fig. 1: (a) Partially depleted SOI MOSFET (b) Fully depleted SOI MOSFET (c) Variation of surface potential with back channel inverted (d) Variation of surface potential with back channel depleted (e) Variation of surface potential with back channel accumulated
Process Photoresist Coating Method Intial speed Ramp speed Spin speed Softbake at 110 C UV exposure (Carl Suss MJB3 Mask Aligner) UV Intensity Developer Cleaning Drying Heating at 125 C Method/Material AZ5214E Spin coating 500 rpm 500 rpm/sec 3000 rpm 50-60 s Wavelength=350 nm 75 mJ/cm 2 MF26A DI Waer Blow drying 2 min Comment Positive photoresist For uniform thickness 1s Duration 5 s Duration 35 s Evaporate solvents in photoresist Duration : 13 s

A. Wafer Cleaning The two wafers described in Tab. I are cleaned as described by the steps shown in Tab. II [6]. The following precautions are observed during wafer cleaning. 1) All the chemicals are CMOS grade and they are taken only in Quartz beaker. 2) Above 80 C H2 O2 can dissociate and Si Wafer can get oxidized in an uncontrolled way. 3) During HF dip, the solution is always taken in teon beaker. 4) Si is hydrophobic, while SiO2 is hydrophilic. The completion of the etching of the native oxide layer is conrmed by the hydrophobic nature of the wafer on Si surface. B. Thermal Oxidation Thermal oxidation is carried out for the wafers for the growth of thick oxide (SiO2 ) layer on the cleaned Si surfaces. For thick SOI, 1000nm of oxide is grown (this consumes 454 nm of Si leaving behind 545 nm of SOI) while for the thin SOI wafer, 290 nm of oxide is grown (this consumes 131 nm of silicon leaving behind 70 nm of SOI). The oxidation is carried in 3 steps with 10 min of dry oxidation followed by wet oxidation (2 hours for thick SOI and 18 min for thin SOI) followed by 10 min of dry oxidation. Thin oxide of 30 nm is grown using at 1000 C for 30 min. C. Annealing The wafers are annealed at 1000 C in the inert atmosphere of N2 with ow rate of 3 Lts/min for about 20 min.This process decreases the lattice defects present in the sample and hence reduces the xed oxide charges.

Duration : 50 s To remove developer N2 gas Hardening of photoresist

TABLE III: Photolithography steps

D. Photolithography Photolithography is carried out four times on the wafers with different masks to obtain SOI MOSFETs of different widths and lengths. The details of photolithography are given in Tab. III E. Oxide Etching After photolithography, the oxide is removed with Buffered HF (100 gm of N H4 OH, 150 ml of DI water = V with (V/3) of HF). This gives etch rate of about 300 nm/min for a duration of 4 min. Complete removal of the oxide can be noticed when the hydrophilic oxide turn to hydrophobic nature of the underlying silicon. Wafer is dipped in acetone and agitated

COURSE E3-327,GROUP 2 REPORT NO. 2, NOVEMBER 2009

Fig. 2: Fabrication steps of SOI MOSFETs

Step No. 1 2 3 4 5 6 7 Process Name SC1 Cleaning DI rinse HF dip DI rinse SC2 Cleaning DI rinse Blow drying Chemical Composition N H4 OH:H2 O2 :DI Water=1:1:5 DI Water HF:DI Water=1:50 DI Water HCl:H2 O2 :DI Water=1:1:6 DI Water Nitrogen Condition 80 C Room Temp. Room Temp. Room Temp. 80 C Room Temp. Room Temp. Duration 10 min 30 sec 10 min Remark Organic impurities and alkali ions like F e3+ , Al3+ , M g 2+ are removed Chemicals are ushed out. Native oxide layer is removed Chemicals are ushed out. Ionic impurities with insoluble hydroxides are removed Chemicals are ushed out. Water droplets adhered to the wafer surface are removed.

TABLE II: Wafer cleaning steps

with ultrasonic vibrator for 2 min to remove the photoresist. Wafer is then dipped in DI water followed by cleaning with IPA to remove for acetone. The wafer is dried (blow drying) with N2 .

F. Diffusion

The steps carried out for n+ diffusion is shown in Tab. IV.

COURSE E3-327,GROUP 2 REPORT NO. 2, NOVEMBER 2009

Process Phosphorous diffusion Carrier gas

Method/Material P OCl3 N2 (3 L/min) and O2 (0.6 L/min) (N2 ows through P OCl3 is 0.4 liters/min 900 C and 950 C and

Comment Source of phosphorous -

Process Etchant

Method/Material H3 P O4 HN O3 DI W ater 2 nm/s DI Water Acetone and IPA : :

Comment Composition 19:1:4 by volume Depends of etchant composition To remove etchant -

Etch rate Cleaning Photoresist removal

Temperature and duration for SOI Small Temperature and duration for SOI Big Quick dip in HNO3:HF:DI water

10 min

TABLE V: Steps for Aluminium etching

30 min Parameter Small signal AC Hold time DC step Value 10 100 100 Units mVRM S ms mV

DI rinse and blow dry with N2

HN O3 : HF : DI water in the ratio of 2:3:60 by volume -

This is done to etch PSG (phosphosilicate glass) Remove all remaining contaminants

TABLE VI: LCR meter settings for capacitance measurements

TABLE IV: Diffusion steps

G. Back Contact Formation After back oxide etching as described in Sec. II-E, aluminium is deposited on the back surface of all the wafer using thermal evaporation described is Sec. II-I. The back contact will reduce the effect of contact resistance of the substrate. H. Forming Gas Annealing At Si-dielectric interface the periodicity of Si crystal terminates. The dangling bonds of Si will lead to interface states, these bonds have to be passivated. Passivation is done using forming gas (a mixture of N2 :H2 ::9:1) at 450 C for 30 min. The H atoms being light, diffuses through the dielectric and dangling bonds get passivated, thereby reducing the interface trap states. I. Thermal Evaporation Aluminium is deposited on the wafers for formation of one of the terminals of the MOSFET. Hindvac thermal evaporation unit is used to deposit thin lms of metals on the substrates. The target material is resistively heated with a tungsten lament by applying low voltage of 30 V. The metal melts and evaporates, these vapours move straight up (low pressure chamber) and deposit on the substrate. The pressure of chamber is maintained at 2105 mbar. J. Aluminium Etching After the wafers have been patterned using photolithography, the Al metallization from the unexposed area should be etched out. The process of etching is described in Tab. V III. M EASUREMENTS A. CV Measurements The C-V measurement is done using Agilent 4284 Precision LCR Meter. The capacitance is determine for different regions of operation. The meter measures the small signal current

due to a small signal voltage sitting on a DC level. Open correction is done for the LCR meter to compensate for cable impedance. The signal is given at the back terminal to mitigate the effect of parasitic impedances. The LCR meter settings for CV measurement is given in Tab. 10. The DC voltage is swept from inversion to accumulation to avoid deep depletion.

B. I-V Measurements The I-V measurement is done using 4155C Semiconductor Parameter Analyzer . The input voltage is swept from 0 V to +15 V and the gate leakage current is determined. The voltage is applied on the top terminal unlike in the case of CV measurements. The maximum power dissipation for IV measurement instrument is limited to 2 W. Hence for a DC voltage of 20 V, the current is limited to 50 mA. The results of IV measurements is shown in Sec. IV.

IV. IV M EASUREMENT R ESULTS The IV curves for different bias conditions is shown in Fig. 3 to Fig. 12. The IV measurements are taken for SOI MOSFET with width of 200 m and length of 100 m.

Fig. 3: Output characteristics for VGb = 0 and SOI is oating.

COURSE E3-327,GROUP 2 REPORT NO. 2, NOVEMBER 2009

Fig. 4: Output characteristics for VGb = 0 and SOI is grounded. IDS for a given VDS and VGS is lower here compared to when SOI is oating (Fig. 3).

Fig. 7: Output characteristics for VGb = 15 and SOI is oating. Here sb is low, thus increasing the threshold voltage of the device. This reduces the current IDS relative to when VGb =5V as shown in Fig. 5.

Fig. 5: Output characteristics for VGb = 5 V and SOI is oating.

Fig. 8: Output characteristics for VGb = 15 and SOI is grounded. Here the saturation current is smaller (2.2 mA) than the saturation current (2.7 mA) when the back channel is inverted as shown in Fig. 6.

Fig. 6: Output characteristics for VGb = 5 and SOI is grounded. The current IDS is lower than the case when SOI is oating (Fig. 5).

V. D ISCUSSION The following inferences can be drawn from the measurements. 1) Due to low doping concentration (51014 cm3 ), Wdep,max will be 1.17 m which is greater than tSi . Hence, the devices is fully depleted when the front

Fig. 9: Output characteristics for VGb oating and SOI is oating. From Fig. 11 the threshold voltage for the above biasing condition is -1 V. For VDS = 4 V, it can be observed that the current saturates beyond VGS VT H = 5 V.

channel is inverted. 2) IDS is higher when the SOI is oating compared to when SOI is grounded.

COURSE E3-327,GROUP 2 REPORT NO. 2, NOVEMBER 2009

Fig. 10: Output characteristics for VGb oating and SOI is grounded. The current increases for increase in gate voltage for a given drain voltage similar to a bulk MOSFET. Here it is observed that when VGf is 4V and Vds is small, the front oxide breaks down causing steep current increase from gate to drain.

4) The devices were fabricated on a common substrate without isolation, the breakdown of buried oxide in any of the devices will reect as degraded performance of all the devices. 5) The back gate leakage current was considerably high, due to which the control of VGb is poor. This is also reected in the output characteristics as the drain current does not change considerably as the back gate voltage is changed from -15 V to +5 V (Fig. 12). 6) When the SOI wafer undergoes phosphorous diffusion, silicon gets consumed to form PSG. Consequently this PSG is etched away. For the thin silicon is completely consumed. This leads to a loss of contact between metal and SOI. Therefore the C-V and I-V characteristics were not observed. VI. C ONCLUSION Fully depleted MOSFETs were fabricated with p-type silicon wafers. The measurement results indicate that the leakage current through back oxide is high, hence the ratio of oncurrent to off-current in the output characteristics is low. Transfer characteristics indicate large dependence of subthreshold current on the drain to source voltage. Since the MOS devices are not isolated, the damage of oxide reects as degraded performance on all the devices. In fully depleted SOI-MOSFET fabrication, the silicon gets consumed during diffusion to form phosphosilicate glass (PSG). Since the thickness of silicon is small, it is completely consumed to form PSG. After which the PSG is etched away. This leads to lack of contact between the metal and the substrate. A PPENDIX A A NALYSIS OF IV M EASUREMENTS The threshold voltage and the sub-threshold slope of the SOI MOSFET depends on the back gate bias condition. The maximum depletion width is given by Equ. 1. 4 Si ln(NA,D /ni )t Wdep,max = (1) qNA,D and B = KT NA ln( ) q ni (2)

Fig. 11: Transfer characteristics for VGb oating and SOI is oating. It can be observed that the threshold voltage is close to -1 V

Fig. 12: Transfer characteristics for VGf oating and SOI is grounded. Here, the back channel is taken from accumulation to inversion, this leads to increase in IDS for increasing back gate bias.

With NA =5101 4, B =260 mV, Wdep,max =1.174 m, (here tSi < Wdep,max , both thin SOI and thick SOI are fully depleted). The threshold voltage with back-channel accumulated is given by Equ. 3 with sf = 2B . It can be seen that the threshold voltage is higher than the bulk SOI MOSFET. For thick SOI tSi =532 nm.
A VT h = sf +

qNA tSi CSi sf + COXf 2COXf

(3)

3) ION /IOF F is small because the back channel is always in inversion due to xed oxide charges in buried oxide.

A This gives ideal VT h =0.626 V .The threshold voltage with back-channel depleted is given by Equ. 4 with sf = 2B

COURSE E3-327,GROUP 2 REPORT NO. 2, NOVEMBER 2009

D which gives ideal value of VT h as 0.556 V. It can be seen that D A VT h is lower than VT h . D VT h

sf (1 +

CSi qNA tSi )+ + (4) COXf 2COXf ( ) CS COXb CSi sf qNA tSi COXf (COXb + CSi ) COXb 2 Si

The threshold voltage with back-channel inverted is given by I Equ. 5 with sf = 2B , which gives ideal VT h as 0.538 V.
I VT h = sf +

qNA tSi 2COXf

(5)

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