Density Based Trafiic Control

DENSITY BASED TRAFFIC CONTROL SYSTEM
ABSTRACT
An adaptive traffic control system was developed where the traffic load is continuously measured by sensors connected to a microcontroller-based system which also performs all intersection control functions. Intersection controllers of an area are interconnected with a communication network through which traffic load and synchronization information is exchanged. As a result, the duration and relative phases of each traffic light cycle change dynamically. For the basic function of the system only the intersection controllers are required.
CHAPTER 1 OVERVIEW
INTRODUCTION Implementation Microcontroller based traffic control system is an application specific project, which is used to control the traffic. An embedded system is developed which consists of a microcontroller, IR transmitter and receiver, LEDs This project is implemented by placing IR transmitters, receivers and leds at the 4 way junction, the four paths are represented as R1,R2,R3,R4
Transmitters and receivers are placed at either sides of the four paths, and 4 leds at corner of the junction When there is a traffic along the paths,value of R would be 000 which are the values of IR sensors and if there is no traffic the value is 111
For instance,let the traffic at the path R1 be initially 111 ie there is no traffic , when the traffic reaches the first sensor,the value of R would be 011,if it reaches second sensor ,the value of R is 001,and then if it reaches the last sensor that is the third one,it is recognized that traffic is heavy and the led glows which indicates that vehicles can move forward,traffic is cleared, and the sensor values automatically changed to 111.the control goes to the next path wher the values of sensors contains more no of zeroes This entire embedded system is placed at that junction
Microcontroller is interfaced with leds and ir sensors The total no of IR sensors required are 12 and leds 4 Therefore these are connected to any two ports of microcontroller
BLOCK DIAGRAM :
IR TRANSMI TTER
IR RECIEVE R
AT89S52 MICRO CONTROLLER
LED
REGULAT ED POWER SUPPLY
LCD
BLOCK DIAGRAM DESCRIIPTION The block diagram consists of microcontroller interfaced to regulated power supply, led and IR receiver and IR transmitter which consists of an IR sensor The IR sensors and leds are connected to any of the port pins of microcontroller,regulated power supply is connected to the Vcc pin of microcontroller which uses an voltage regulator to get 5 v of power supply. The transmit pin of IR receiver is connected to the receive pin of microcontroller This embedded system is placed at the 4 way junction which controls the traffic electronically The system uses a compact circuitry build around flash version of AT89S52 EMBEDDED C Microcontroller with a non-volatile memory. Programs will be developed in language. FLASH MAGIC is used for loading of programs into microcontroller.
IR TRANSMITTER and receiver The purpose of the transmitter is to transform the information we want to send into a signal that can be propagated by the channel. In the case of our wired copper channel, this means we want the information to be transformed into a modulated voltage level, something like the pulse train. For a wireless channel, however, the transmitter needs to encode the information onto an EM wave that can be easily propagated. IR TRANSMITTER
The IR transmitter part consists of an Infra red light emitting diode that can capable of sending modulated data within infra red band. To match the receiver frequency the the data is modulated at 38.7 KHZ by configuring 555 timer at astable mode of operation, which generates frequency using the components R2 and C2 as
shown in above fig. This frequency can be varied over a long range just by varying the preset R1 and C1.
IR RECEIVER
The IR receiver consists of TSOP 1738 module which is a simple yet effective IR proximity sensor built around the TSOP 1738
module. The TSOP module is commonly found at the receiving end of an IR remote control system; e.g., in TVs, CD players etc. These modules require the incoming data to be modulated at a particular frequency and would ignore any other IR signals. It is also immune to ambient IR light, so one can easily use these sensors outdoors or under heavily lit 32 kHz to 42kHz. conditions. Such modules are available for different carrier frequencies from In this particular proximity sensor, we will be generating a constant stream of square wave signal using IC555 centered at 38 kHz and would use it to drive an IR led. So whenever this signal bounces off the obstacles, the receiver would detect it and change its output. Since the TSOP 1738 module works in the active-low configuration, its output would normally remain high and would go low when it detects the signal (the obstacle). Basically an ir sensor is used for detecting an obstacle, there are some areas where valuable things are placed, an IR transmitter and receiver is placed there, an infrared path is established and if any person comes into that path the buzzer gets on which gives out a long beep Similarly a fire sensor is used to detect fire The sensed data is given to the microcontroller, processing is done according to the logic in the microcontroller and then writes onto GSM which will further send sms to the mobile at the user A buzzer is interfaced to microcontroller to give out a beep sound whenever an obstacle and fire is detected
IR receiver module TSOP
Description The TSOP17.. series are miniaturized receivers for infrared remote filter. The demodulated output signal can directly be decoded by a microprocessor. TSOP17.. is the standard IR remote control receiver series, supporting all major transmission codes. control systems. PIN diode and preamplifier are assembled on lead frame, the epoxy package is designed as IR
Features Photo detector and preamplifier in one package Internal filter for PCM frequency Improved shielding against electrical field disturbance TTL and CMOS compatibility Output active low Low power consumption High immunity against ambient light Continuous data transmission possible (1200 bit/s)
Suitable burst length 10 cycles/burst
CHAPTER 2 INTRODUCTION TO MICROCONTROLLER AND EMBEDDED SYSTEM
EMBEDDED SYSTEM An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions[1], sometimes with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on use. Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale. Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure. programming. Embedded systems have become very important today as they control many of the common devices we
In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, Handheld computers share some elements with embedded systems such as the operating systems and microprocessors which power them but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected. An embedded system is some combination of computer hardware and software, either fixed in capability or programmable, that is specifically designed for a particular kind of application device. Industrial machines, automobiles, medical equipment, cameras, household appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone and PDA) are among the myriad possible hosts of an embedded system. Embedded systems that are programmable are provided with a programming interface, and embedded systems programming is a specialized occupation. Certain operating systems or language platforms are tailored for the embedded market, such as EmbeddedJava and Windows XP Embedded. However, some low-end consumer products use very inexpensive microprocessors and limited storage, with the application and operating system both part of a single program. The program is written permanently into the system's memory in this case, rather than being loaded into RAM (random access memory), as programs on a personal computer are.
INTRODUCTION TO EMBEDDED SYSTEM We are living in the Embedded World. You are surrounded with many embedded products and your daily life largely depends on the proper functioning of these gadgets. Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in your kitchen, Card readers, Access Controllers, Palm devices of your work space enable you to do many of your tasks very effectively. Apart from all these, many controllers embedded in your car take care of car operations between the bumpers and most of the times you tend to ignore all these controllers. In recent days, you are showered with variety of information about these embedded controllers in many places. All kinds of magazines and journals regularly dish out details about latest technologies, new devices, fast applications which make you believe that your basic survival is controlled by these embedded products. Now you can agree to the fact that these embedded products have successfully invaded into our world. You must be
wondering about these embedded controllers or systems. What is this Embedded System? The computer you use to compose your mails, or create a document or analyze the database is known as the standard desktop computer. These desktop computers are manufactured to serve many purposes and applications. You need to install the relevant software to get the required processing facility. So, these desktop computers can do many things. In contrast, embedded controllers carryout a specific work for which they are designed. Most of the time, engineers design these embedded controllers with a specific goal in mind. So these controllers cannot be used in any other place. Theoretically, an embedded controller is a combination of a piece of microprocessor based hardware and the suitable software to undertake a specific task. These days designers have many choices in
microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available variety really may overwhelm even an experienced designer. Selecting a right microprocessor may turn out as a most difficult first step and it is getting complicated as new devices continue to pop-up very often. In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market acceptance of this particular family has
driven many semiconductor manufacturers to develop something new based on this particular architecture. Even after 25 years of existence, semiconductor manufacturers still come out with some kind of device using this 8031 core.
MICROCONTROLLER In contrast to general-purpose CPUs, microcontrollers may not implement an external address or data bus as they integrate RAM and non-volatile memory on the same chip as the CPU. Using fewer pins, the chip can be placed in a much smaller, cheaper package. Integrating the memory and other peripherals on a single chip and testing them as a unit increases the cost of that chip, but often results in decreased net cost of the embedded system as a whole. Even if the cost of a CPU that has integrated peripherals is slightly more than the cost of a CPU + external peripherals, having fewer chips typically allows a smaller and cheaper circuit board, and reduces the labor required to assemble and test the circuit board. A microcontroller is a single integrated circuit, commonly with the following features:
central processing unit - ranging from small and simple 4-bit processors to complex 32- or 64-bit processors discrete input and output bits, allowing control or detection of the logic state of an individual package pin serial input/output such as serial ports (UARTs) other serial communications interfaces like IC, Serial Peripheral Interface and Controller Area Network for system interconnect peripherals such as timers, event counters, PWM generators, and watchdog volatile memory (RAM) for data storage ROM, EPROM, [EEPROM] or Flash memory for program and operating parameter storage clock generator - often an oscillator for a quartz timing crystal, resonator or RC circuit many include analog-to-digital converters in-circuit programming and debugging support
This integration drastically reduces the number of chips and the amount of wiring and PCB space that would be needed to produce equivalent systems using separate chips. Furthermore, and on low pin count devices in particular, each pin may interface to several internal peripherals, with the pin function selected by software. This allows a part to be used in a wider variety of applications than if pins had dedicated functions. Microcontrollers have proved to be highly popular in embedded systems since their introduction in the 1970s.
Some microcontrollers use a Harvard architecture: separate memory buses for instructions and data, allowing accesses to take place concurrently. Where a Harvard architecture is used, instruction words for the processor may be a different bit size than the length of internal memory and registers; for example: 12-bit instructions used with 8-bit data registers. The decision of which peripheral to integrate is often difficult. The microcontroller vendors often trade operating frequencies and system design flexibility against time-to-market requirements from their customers and overall lower system cost. Manufacturers have to balance the need to minimize the chip size against additional functionality. Microcontroller architectures vary widely. Some designs include general-purpose microprocessor cores, with one or more ROM, RAM, or I/O functions integrated onto the package. Other designs are purpose built for control applications. A microcontroller instruction set usually has many instructions intended for bit-wise operations to make control programs more compact. For example, a general purpose processor might require several instructions to test a bit in a register and branch if the bit is set, where a microcontroller could have a single instruction that would provide that commonly-required function. Microcontroller
A microcontroller (also MCU or C) is a computer-on-a-chip. It is a type of microprocessor emphasizing high integration, low power consumption, self-sufficiency and cost-effectiveness, in contrast to a general-purpose microprocessor (the kind used in a PC). In addition to the usual arithmetic and logic elements of a general purpose microprocessor, the microcontroller typically integrates additional elements such as read-write memory for data storage, read-only memory, such as flash for code storage, EEPROM for permanent data storage, peripheral devices, and input/output interfaces. At clock speeds of as little as a few MHz or even lower, microcontrollers often operate at very low speed compared to modern day microprocessors, but this is adequate for typical applications. They consume relatively little power (milliwatts), and will generally have the ability to sleep while waiting for an interesting peripheral event such as a button press to wake them up again to do something. Power consumption while sleeping may be just nano watts, making them ideal for low power and long lasting battery applications. Microcontrollers are frequently used in automatically controlled products and devices, such as automobile engine control systems, remote controls, office machines, appliances, power tools, and toys. By reducing the size, cost, and power consumption compared to a design using a separate microprocessor, memory, and input/output devices, microcontrollers make it economical to electronically control many more processes.
MICROCONTROLLER VERSUS MICROPROCESSOR What is the difference between a Microprocessor and
Microcontroller? By microprocessor is meant the general purpose Microprocessors such as Intel's X86 family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010, 68020, 68030, 68040, etc). These microprocessors contain no RAM, no ROM, and no I/O ports on the chip itself. For
this reason, they are commonly referred to as general-purpose Microprocessors. A system designer using a general-purpose microprocessor such as the Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more expensive, they have the advantage of versatility such that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand. This is not the case with Microcontrollers. A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip; therefore, the designer cannot add any external memory, I/O ports, or timer to it. The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical. In many applications, for example a TV remote control, there is no need for the computing power of a 486 or even an 8086 microprocessor. These applications most often require some I/O operations to read signals and turn on and off certain bits. MICROCONTROLLERS FOR EMBEDDED SYSTEMS
In the Literature discussing microprocessors, we often see the term Embedded System. Microprocessors and Microcontrollers are widely used in embedded system products. An embedded system product uses a microprocessor (or Microcontroller) to do one task only. A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it. Contrast this with a Pentium based PC. A PC can be used for any number of applications such as word processor, print-server, bank teller terminal, Video game, network server, or Internet terminal. Software for a variety of applications can be loaded and run. of course the reason a pc can perform myriad tasks is that it has RAM memory and an operating system that loads the application software into RAM memory and lets the CPU run it. In an Embedded system, there is only one application software that is typically burned into ROM. An x86 PC contains or is connected to various embedded products such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on. Each one of these peripherals has a Microcontroller inside it that performs only one task. For example, inside every mouse there is a Microcontroller to perform the task of finding the mouse position and sending it to the PC. Table 1-1 lists some embedded products. Intel's 8031 ArchitectureThe generic 8031 architecture sports a Harvard architecture, which contains two separate buses for
both program and data. So, it has two distinctive memory spaces of 64K X 8 size for both program and data. It is based on an 8 bit central processing unit with an 8 bit Accumulator and another 8 bit B register as main processing blocks. Other portions of the architecture include few 8 bit and 16 bit registers and 8 bit memory locations. Each 8031 device has some amount of data RAM built in the device for internal processing. This area is used for stack operations and temporary storage of data. This base architecture is supported with onchip peripheral functions like I/O ports, timers/counters, versatile serial communication port. So it is clear that this 8031 architecture was designed to cater many real time embedded needs. The following list gives the features of the 8031 architecture: Optimized 8 bit CPU for control applications. Extensive Boolean processing capabilities. 64K Program Memory address space. 64K Data Memory address space. 128 bytes of onchip Data Memory. 32 Bi-directional and individually addressable I/O lines. Two 16 bit timer/counters. Full Duplex UART. 6-source / 5-vector interrupt structure with priority levels.
Onchip clock oscillator.
Now you may be wondering about the non mentioning of memory space meant for the program storage, the most important part of any embedded controller. Originally this 8031 architecture was introduced with onchip, 'one time programmable' version of Program Memory of size 4K X 8. Intel delivered all these microcontrollers (8051) with user's program fused inside the device. 8051 DERIVATIVES Along the way, this 8031 architecture gained enviable market acceptance. Many semiconductor manufacturers started either manufacturing the 8031 devices as such (Intel was liberal in giving away license to whoever asked) or developing a new kind of microcontrollers based modified on the 8031 basic core 8031 architecture.Manufacturers
architecture and added many new peripheral make them attractive to the designers.
functions to
Because of the rush, electronic community started getting a variety of 8031 based devices with range of options. To beat the competition, manufacturers developed different microcontrollers with many unique features.
These parts are popularly known as '8031 Derivatives'. Almost every decent manufacturer boasted of having an 8031 based microcontroller in the line card. First major manufacturer was the Philips who brought out more than 40-50 derivatives with a variety of I/O options, memory combinations, and peripheral functions. Devices became available in regular DIP and SMD packages. With the basic 8031 core, Philips ported high capacity Program Memory (upto 32K/64K), its patented I2C interface bus, 8/10 bit Analog to Digital Converters, CAN Bus, Capture and Compare registers, Watch dog timer, PWM facilities and etc. More I/O ports (as many as eight ports), additional timer/counter, second serial port was also made available in Philips devices. Apart from all these, Philips developed many consumer devices meant for telecom, computer and TV applications. A smart card controller was also developed by incorporating a cryptographic engine. So Philips clearly established itself as the market leader in 8031 derivatives and still caters to this segment. Then came Dallas semiconductor. Dallas redesigned the 8031 architecture and eliminated waste clock cycles of original core and made all instructions executed in less clock cycles (maximum of 4) which has traditionally taken upto 12 clock cycles. So, came the birth of High speed 8031 Derivatives.
Dallas also maintained the same device pin out configurations to enable the user get upto 3X performance by replacing slower parts with a Dallas device. So, existing compiled code started running faster without any modification. These days, you can find Dallas devices giving upto 50 MIPS (Million Instructions Per Second).
Apart from this, Dallas introduced additional Serial port, Watch Dog Timer, Precision Reset Circuitry, Real Time Clock, Power Fail Monitor in the 8031 devices. Also a second data pointer, more onchip RAM space and more interrupt lines were also made available. Dallas semiconductor also has got a range of secure
microcontrollers based on 8031 core. This microcontroller family uses non volatile RAM to keep both program and data. Because of this RAM, the controller gives the In System Reprogrammability. Dallas has combined this microcontroller, SRAM and lithium cell in a single pack. This device guarantees 10+ years of data retention in the RAM area. This 8031 also boasts the tamper proof security features like Real Time Memory Encryption, user selected 48 bit Encryption key, memory contents, security lock and the facility to hide interrupt vector table. As you can agree, this particular 8031 device has found a niche market in banking and security related applications.
Atmel
Corporation
is
the
another
major
semiconductor
manufacturer who introduced many flash memory based 8031 derivatives at a competitive cost. Atmel used its expertise in flash memory technology into the basic 8031 core and brought out microcontrollers with a variety of flash memory options and few devices also carry In System Reprogramming facility. You can program/reprogram this microcontroller after soldering the device in the target board. If this programming facility is embedded in the system software, then the tasks like remote calibration, onsite system upgradation become as easy as sending your data/program in a floppy disk or by internet. Atmel devices sport security lock to its flash memory to protect the contents from the prying eyes. Meantime, Intel itself tried to cash in the popularity of this 8031 architecture and introduced improved versions of microcontrollers: 80151 and 80251 families. These devices sport 16 bit architecture using 8031 core and unfortunately these devices have not become as popular as 8031.Even after many years of introduction, 8031 core is still going strong in 8 bit arena.
PIN DIAGRAM OF GENERAL PURPOSE MICROCONTROLLER
ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, for external timing or clocking purposes, even when there are no accesses to external memory. (However, one ALE pulse is skipped during each access to external Data Memory.) This pin is also the program pulse input (PROG) during EPROM programming.
PSEN:
Program Store Enable is the read strobe to external
Program Memory. When the device is executing out of external Program Memory, PSEN is activated twice each machine cycle (except that two PSEN activations are skipped during accesses to external Data Memory). PSEN is not activated when the device is executing out of internal Program Memory. EA/VPP: When EA is held high the CPU executes out of internal Program Memory (unless the Program Counter exceeds 0FFFH in the 80C51). Holding EA low forces the CPU to execute out of external memory regardless of the Program Counter value. In the 80C31, EA must be externally wired low. In the EPROM devices, this pin also receives the programming supply voltage (VPP) during EPROM programming. XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifier. Port 0: Port 0 is an 8-bit open drain bidirectional port. As an
open drain output port, it can sink eight LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pullups when emitting 1s. Port 0 emits code bytes during program verification. In this application, external pullups are required.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, port 1 pins that are externally being pulled low will source current because of the internal pullups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 emits the high-order address byte during accesses to external memory that use 16-bit addresses. In this application, it uses the strong internal pullups when emitting 1s. Port 3: . Port 3 is an 8-bit bidirectional I/O port with internal pullups. It also serves the functions of various special features of the 80C51 Family as follows: Port Pin Alternate Function P3.0- RxD (serial input port) P3.1 -TxD (serial output port) P3.2 -INT0 (external interrupt 0) P3.3- INT1 (external interrupt 1) P3.4 -T0 (timer 0 external input) P3.5 -T1 (timer 1 external input) P3.6 -WR (external data memory write strobe)
P3.7 -RD (external data memory read strobe) VCC: -Supply voltage VSS: -Circuit ground potential All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Registers P0 through P3), an output driver, and an input buffer. The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory. In this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the P2 SFR content. All the Port 3 pins are multifunctional. They are not only port pins, but also serve the functions of various special features as listed below: Port Pin Alternate Function P3.0 RxD (serial input port) P3.1 TxD (serial output port) P3.2 INT0 (external interrupt) P3.3 INT1 (external interrupt) P3.4 T0 (Timer/Counter 0 external input)
P3.5 T1 (Timer/Counter 1 external input) P3.6 WR (external Data Memory write strobe) P3.7 RD (external Data Memory read strobe) MEMORY ORGANISATION The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin remains at 0.All 80C51 devices have separate address spaces for program and data memory, as shown in Figures 1 and 2. The logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also be generated through the DPTR register. Program memory (ROM, EPROM) can only be read, not written to. There can be up to 64k bytes of program memory. In the 80C51, the lowest 4k bytes of program are on-chip. In the ROMless versions, all program memory is external. The read strobe for external program memory is the PSEN (program store enable). Data Memory (RAM) occupies a separate address space from Program Memory. In the 80C51, the lowest 128 bytes of data memory are on-chip. Up to 64k bytes of external RAM can be addressed in the external Data Memory space. In the ROMless version, the lowest 128 bytes are on-chip. The CPU generates
read and write signals, RD and WR, as needed during external Data Memory accesses. External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data memory. BASIC REGISTERS A number of 8052 registers can be considered "basic." Very little can be done without them and a detailed explanation of each one is warranted to make sure the reader understands these registers before getting into more complicated areas of development. The Accumulator If you've worked with any other assembly language you will be familiar with the concept of an accumulator register. The Accumulator, as its name suggests, is used as a general register to accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the 8052 has due to the sheer number of instructions that make use of the accumulator. More than half of the 8052's 255 instructions manipulate or use the Accumulator in some way. For example, if you want to add the number 10 and 20, the resulting 30 will be stored in the Accumulator. Once you
have a value in the Accumulator you may continue processing the value or you may store it in another register or in memory. The "R" Registers The "R" registers are sets of eight registers that are named R0, R1, through R7. These registers are used as auxiliary registers in many operations. To continue with the above example, perhaps you are adding 10 and 20. The original number 10 may be stored in the Accumulator whereas the value 20 may be stored in, say, register R4. To process the addition you would execute the command: ADD A,R4 After executing this instruction the Accumulator will contain the value 30. You may think of the "R" registers as very important auxiliary, or "helper", registers. The Accumulator alone would not be very useful if it were not for these "R" registers. The "R" registers are also used to store values temporarily. For example, lets say you want to add the values in R1 and R2 together and then subtract the values of R3 and R4. One way to do this would be: MOV A,R3 ADD A,R4 MOV R5,A MOV A,R1 ;Move the value of R3 to accumulator ;Add the value of R4 ;Store the result in R5 ;Move the value of R1 to Acc
ADD A,R2 SUBB A,R5
;Add the value of R2 with A ;Subtract the R5 (which has R3+R4)
As you can see, we used R5 to temporarily hold the sum of R3 and R4. Of course, this isn't the most efficient way to calculate (R1+R2) - (R3 +R4) but it does illustrate the use of the "R" registers as a way to store values temporarily. As mentioned earlier, there are four sets of "R" registers-register bank 0, 1, 2, and 3. When the 8052 is first powered up, register bank 0 (addresses 00h through 07h) is used by default. In this case, for example, R4 is the same as Internal RAM address 04h. However, your program may instruct the 8052 to use one of the alternate register banks; i.e., register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address 04h. For example, if your program instructs the 8052 to use register bank 1, register R4 will now be synonymous with Internal RAM address 0Ch. If you select register bank 2, R4 is synonymous with 14h, and if you select register bank 3 it is synonymous with address 1Ch. The concept of register banks adds a great level of flexibility to the 8052, especially when dealing with interrupts (we'll talk about interrupts later). However, always remember that the register banks really reside in the first 32 bytes of Internal RAM.
The B Register The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value. The "B" register is only used implicitly by two 8052 instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by another number, you may store the other number in "B" and make use of these two instructions. Aside from the MUL and DIV instructions, the "B" register are often used as yet another temporary storage register much like a ninth "R" register. The Program Counter The Program Counter (PC) is a 2-byte address that tells the 8052 where the next instruction to execute is found in memory. When the 8052 is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC isn't always incremented by one. Since some instructions are 2 or 3 bytes in length the PC will be incremented by 2 or 3 in these cases. The Program Counter is special in that there is no way to directly modify its value. That is to say, you can't do something like PC=2430h. On the other hand, if you execute LJMP 2430h you've effectively accomplished the same thing. It is also interesting to note that while you may change the value of PC (by executing a jump instruction, etc.) there is no way to read the value of PC. That is to say, there is no way to ask the 8052 "What address are you about to execute?" As it turns out,
this is not completely true: There is one trick that may be used to determine the current value of PC. This trick will be covered in a later chapter.
The Data Pointer
The Data Pointer (DPTR) is the 8052s only
user-accessible 16-bit (2-byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte values. The PC just described is a 16-bit value but isn't directly user-accessible as a working register. DPTR, as the name suggests, is used to point to data. It is used by a number of commands that allow the 8052 to access external memory. When the 8052 accesses external memory it accesses the memory at the address indicated by DPTR. While DPTR is most often used to point to data in external memory or code memory, many developers take advantage of the fact that it's the only true 16-bit register available. It is often used to store 2-byte values that have nothing to do with memory locations. The Stack Pointer The Stack Pointer, like all registers except
DPTR and PC, may hold an 8-bit (1-byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from.
When you push a value onto the stack, the 8052 first increments the value of SP and then stores the value at the resulting memory location. When you pop a value off the stack, the 8052 returns the value from the memory location indicated by SP, and then decrements the value of SP. This order of operation is important. When the 8052 is initialized SP will be initialized to 07h. If you immediately push a value onto the stack, the value will be stored in Internal RAM address 08h. This makes sense taking into account what was mentioned two paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h) and then will store the pushed value at that memory address (08h). ADDRESSING MODES The addressing modes in the 80C51 instruction set are as follows: Direct Addressing In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs can be directly addressed. Indirect Addressing In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer. The address register for 16bit addresses can only be the 16-bit data pointer register, DPTR.
Register Instructions The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW. Register-Specific Instructions Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does that. Instructions that refer to the Accumulator as A assemble as accumulator specific opcodes. Immediate Constants The value of a constant can follow the opcode in Program Memory. \ For example, MOV A, #100 loads the Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H. Indexed Addressing Only program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program Memory A 16-bit base register
(either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer. Another type of indexed addressing is used in the case jump instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data
CHAPTER 3 AT89S52 MICROCONTROLLER
Description The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry- standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system
or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
Features Compatible with MCS-51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode)
Pin Description VCC Supply voltage. GND Ground.
Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sinkeight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the
functions of various special features of the AT89S52, as shown in the following table.
RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in Future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 6) for Timer 2. The register pair (RCAP2H,RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1 during power up. It can be set and rest under software control and is not affected by reset.
Memory Organization MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory. Data Memory The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions which use direct addressing access the SFR space. 9 1919BMICRO11/03 For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. Watchdog Timer(One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to
disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. WDT During Powerdown and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external
interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Powerdown, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE. UART The UART in the AT89S52 operates the same way as the UART in the AT89C51
and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select Products, then 8051-Architecture Flash Microcontroller, then Product Overview. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select Products, then 8051-Architecture Overview. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 5. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, Flash Microcontroller, then Product
the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1. Auto-reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit autoreload mode. This feature is invoked
by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 6). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON.
If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
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Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2s overflow rate according to the following equation.
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors.
The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Modes 1 and 3 Baud Rates= Timer 2 Overflowrate/16
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
Interrupts The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1
flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write
to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Powerdown mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits
The AT89S52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Programming the Flash Parallel Mode The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed.
The
programming
interface
needs
high-voltage
(12-volt)
program enable signal and is compatible with conventional thirdparty Flash or EPROM programmers. The AT89S52 code memory array is programmed byte-by-byte. Programming Algorithm: Before programming the AT89S52, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89S52, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89S52 features Data Polling to indicate the end of a byte write
cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (100H) = 52H indicates AT89S52 (200H) = 06H Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control
signals and by pulsing ALE/PROG low for a duration of 200 ns 500 ns. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output. Programming the Flash Serial Mode The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz. Serial Programming Algorithm
To program and verify the AT89S52 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to H.If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to33 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16. 3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write cycle is self-timed and typically takes less than 0.5 ms at 5V. 4. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6. 5. At the end of a programming session, RST can be set low to commence normal device operation. Power-off sequence (if needed): Set XTAL1 to L (if a crystal is not used).
Set RST to L. Turn VCC power off. Data Polling: The Data Polling feature is also available in the serial mode. In this mode,during a write cycle an attempted read of the last byte written will result in the complement of the MSB of the serial output byte on MISO.
Flash Programming and Verification Waveforms Serial Mode Figure 13. Serial Programming Waveforms
CHAPTER 4 INTERFACING DEVICES
RS232 (serial port).
RS-232 (Recommended Standard - 232) is a telecommunications standard for binary serial communications between devices. It supplies the roadmap for the way devices speak to each other using serial ports. The devices are commonly referred to as a DTE (data terminal equipment) and DCE (data communications equipment); for example, a computer and modem, respectively. RS232 is the most known serial port used in transmitting the data in communication and interface. Even though serial port is harder to program than the parallel port, this is the most effective method in which the data transmission requires less wires that yields to the less cost. The RS232 is the communication line which enables the data transmission by only using three wire links. The three links provides transmit, receive and common ground... The transmit and receive line on this connecter send and receive data between the computers. As the name indicates, the data is transmitted serially. The two pins are TXD & RXD. There are other lines on this port as RTS, CTS, DSR, DTR, and RTS, RI. The 1 and 0 are the data which defines a voltage level of 3V to 25V and -3V to -25V respectively. he electrical characteristics of the serial port as per the EIA (Electronics Industry Association) RS232C Standard specifies a maximum baud rate of 20,000bps, which is slow compared to todays standard speed. For this reason, we have chosen the new RS-232D Standard, which was recently released.
The RS-232D has existed in two types. i.e., D-TYPE 25 pin connector and D-TYPE 9 pin connector, which are male connectors on the back of the PC. You need a female connector on your communication from Host to Guest computer. The pin outs of both D-9 & D-25 are show below
D-Type-9 pin no. 3 2 7 8 6 5 1 4 9
D-Type-25 pin no. 2 3 4 5 6 7 8 20 22
Pin outs RD TD RTS CTS DSR SG DCD DTR RI
Function Receive Data (Serial data input) Transmit Data (Serial data output) UART is ready to exchange data Clear to send (i.e.; modem is ready to exchange data) Data ready state (UART establishes a link) Signal ground modem detects a carrier Data Terminal Ready. detects ringing signal from PSTN
Request to send (acknowledge to modem tha
Data Carrier detect (This line is active when
Ring Indicator (Becomes active when modem
Rs232
When communicating with various micro processors one needs to convert the RS232 levels down to lower levels, typically 3.3 or 5.0 Volts. Here is a cheap and simple way to do that. Serial RS-232 (V.24) communication works with voltages -15V to +15V for high and low. On the other hand, TTL logic operates between 0V and +5V . Modern low power consumption logic operates in the range of 0V and +3.3V or even lower.
RS-232 TTL Logic -15V -3V +2V +5V High +3V 0V Low +15V +0.8V Thus the RS-232 signal levels are far too high TTL electronics, and the negative RS-232 voltage for high cant be handled at all by computer logic. To receive serial data from an RS-232 interface the voltage has to be reduced. Also the low and high voltage level has to be inverted. This level converter uses a Max232 and five capacitors. The max232 is quite cheap (less than 5 dollars) or if youre lucky you can get a free sample from Maxim.The MAX232 from Maxim was the first IC which in one package contains the necessary drivers and receivers to adapt the RS-232 signal voltage levels to TTL logic. It became popular, because it just needs one voltage (+5V or +3.3V) and generates the necessary RS-232 voltage levels. +---\/---+ 1 -|C1+ Vcc|- 16 2 -|V+ gnd|- 15 3 -|C1- T1O|- 14 4 -|C2+ R1I|- 13 5 -|C2- R1O|- 12 6 -|V- T1I|- 11 7 -|T2O T2I|- 10 MAX 232 PIN DIAGRAM
8 -|R2I R2O|- 9 +--------+
RS232 INTERFACED TO MAX 232
J 9 8 7 6
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1 2
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Rs232 is 9 pin db connector,only three pins of this are used ie 2,3,5 the transmit pin of rs232 is connected to rx pin of microcontroller
Max232 interfaced to microcontroller
MAX232 is connected to the microcontroller as shown in the figure above 11, 12 pin are connected to the 10 and 11 pin ie transmit and receive pin of microcontroller
LEDS :
Fig:19 LEDs interfacing LED (light emitting diode) color is characterized by the wavelength it emits. The peak emission wavelength differs according to the energy released during recombination. This energy differs according to the LED material used. Mixed crystals of GaP & GaAs are used. By varying the mixing ratio X, different luminous colors from red to yellow are obtained. LEDs can typically draw up to 30mA.A current limiting resistor is mandatory to protect both the microcontroller & LED. Even connecting a led through a resistor is not advisable in case of 8051.A NPN or a PNP transistor may be used. This way even
higher currents can be used. Ohms law can be used to calculate the value of the current limiting resistor , i.e I=V/R. REGULATED POWER SUPPLY A variable regulated power supply, also called a variable bench power supply, is one where you can continuously adjust the output voltage to your requirements. Varying the output of the power supply is the recommended way to test a project after having double checked parts placement against circuit drawings and the parts placement guide. This type of regulation is ideal for having a simple variable bench power supply. Actually this is quite important because one of the first projects a hobbyist should undertake is the construction of a variable regulated power supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much handier to have a variable supply on hand, especially for testing. Most digital logic circuits and processors need a 5 volt power supply. To use these parts we need to build a regulated 5 volt source. Usually you start with an unregulated power To make a 5 volt power supply, we use a LM7805 voltage regulator IC (Integrated Circuit). The IC is shown below.
The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin and then when you turn on the power, you get a 5 volt supply from the Output pin.
CIRCUIT FEATURES
Brief description of operation: Gives out well regulated +5V output, output current capability of 100 mA Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot Circuit complexity: Very simple and easy to build Circuit performance: Very stable +5V output voltage, reliable operation
Availability of components: Easy to get, uses only very common basic components Design testing: Based on datasheet example circuit, I have used this circuit succesfully as part of many electronics projects Applications: Part of electronics devices, small laboratory power supply Power supply voltage: Unreglated DC 8-18V power supply Power supply current: Needed output current + 5 mA Component costs: Few dollars for the electronics components + the input transformer cost
BLOCK DIAGRAM
EXAMPLE CIRCUIT DIAGRAM:
RESET
The pin 9 of the microcontroller 8051 is the RESET pin. Upon applying a high pulse to this pin, the micro controller will reset and terminate all activities. This is often called as power-on reset. Activating a power-on reset will cause all the values in the registers to be lost. It will set program counter to all 0s. the reset can be given by either power-on reset circuit or by using a momentary switch. RESET value of some 8051 registers: Regist er PC DPTR ACC PSW SP B P0-P3 Reset value (hex) 0000 0000 00 00 07 00 FF
Table:10 Reset values table
POWER SUPPLY Power supply is an important part of operation of the Microcontroller. Microcontroller operates at +5v DC and also for other ICs and displays.
INTRODUCTION TO ORCAD(SCHEMATIC DESIGN TOOL)
OrCAD is a software tool suite used primarily for electronic design automation. The software is used mainly to create electronic prints for manufacturing of printed circuit boards, by electronic simulation. The name OrCAD is a portmanteau, reflecting the software's origins: Oregon + CAD. The OrCAD product line is fully owned by Cadence Design Systems. The latest iteration has the ability to maintain a database of available integrated circuits. This database may be updated by the user by downloading packages from component manufacturers, such as Analog Devices or Texas Instruments. design engineers and electronic technicians to manufacture electronic schematics and diagrams, and for their
The Cadence OrCAD product line includes affordable, highperformance PCB design tools that boost productivity for smaller design teams and individual PCB designers. To stay competitive in today's market, engineers must take a design from engineering through manufacturing with shorter design cycles and faster time to market. To be successful, you need a set of powerful, intuitive, and integrated tools that work seamlessly across the entire design flow. Cadence OrCAD personal productivity tools (including Cadence PSpice) have a long history of addressing these demands. Designed to boost productivity for smaller design teams and individual PCB designers, OrCAD PCB design suites grow with your needs and technology challenges. The powerful, tightly integrated PCB design suites include design capture, librarian tools, a PCB editor, an auto/interactive router, and optional analog and mixed-signal simulator. The affordable, high-performance OrCAD product line is easily scalable with the full complement of Cadence Allegro PCB solutions. The OrCAD product line is supported by a worldwide network of Cadence Channel Partners. For sales, technical support, and training inquiries please visit the global Cadence Channel Partner
listing to find a partner in your region.
CHAPTER 5 PROJECT CIRCUITRY
SCHEMATIC
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SCHEMATIC DESCRIPTION
1 7 3 8 1 7 1 3 8 1 D 3 5 3 3 0 1 0 k D 3 5 L E D L E D
4 E
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it le < T it le c o u c > m > e n e s n d t a N y u , m MS b h a e r e c e 1h t r 0 o5 f , 12 0 R < 0 e R 8 v e v C o d e > iz e D o 2 < D a t e W :
We can break the project into three parts like micro

D e d
S I T
A S E
A F F I C
L
S
controller section, power supply section, and D.C. regulated power supply section. The Circuit shows the complete diagram of the Density based traffic control system Micro controller section contains only micro controller AT89S52 and a crystal of 11.0592 MHz for oscillator. As micro controller works on the program inside the memory. As a
program generates the login therefore it does not require any logic circuits. As the controller keeps all the memory and I/O ports inside it, it contains very less components in its outer configuration. Power to the IC supplied is +5v DC The IR sensors are interfaced port 2 pins of microcontroller and LEDs to the port 0 pins of microcontroller .lcd connected to the remaining port pins of microcontroller Power supply is an important part of operation of the
Microcontroller. Microcontroller operates at +5v DC and also for other ICs and displays.
CHAPTER 7 SDCC COMPILATION TOOL
SMALL DEVICE C COMPILER SDCC is a retargettable, optimizing ANSI - C compiler that targets the Intel 8051, Maxim 80DS390, Zilog Z80 and the Motorola 68HC08 based MCUs. Work is in progress on supporting the
Microchip PIC16 and PIC18 series. SDCC is Free Open Source Software, distributed under GNU General Public License (GPL). FEATURES
ASXXXX and ASLINK, a Freeware, retargettable assembler and linker. extensive MCU specific language extensions, allowing
effective use of the underlying hardware.
a host of standard optimizations such as global sub expression elimination, loop optimizations (loop invariant, strength reversing reduction ), of induction folding variables and loop copy constant and propagation,
propagation, dead code elimination and jump tables for 'switch' statements.
MCU specific optimizations, including a global register allocator. adaptable MCU specific backend that should be well suited for other 8 bit MCUs independent rule based peep hole optimizer. a full range of data types: char (8 bits, 1 byte), short (16 bits, 2 bytes), int (16 bits, 2 bytes), long (32 bit, 4 bytes) and float (4 byte IEEE). the ability to add inline assembler code anywhere in a function. the ability to report on the complexity of a function to help decide what should be re-written in assembler.
a good selection of automated regression tests.
SDCC also comes with the source level debugger SDCDB, using the current version of Daniel's s51 simulator. SDCC was written by Sandeep Dutta and released under a GPL license. Since its initial release there have been numerous bug fixes and improvements. As of December 1999, the code was moved to SourceForge where all the "users turned developers" can access the same source tree. SDCC is constantly being updated with all the users' and developers' input. AVR and gbz80 ports are no longer maintained.
SDCC SUPPORTS FOLLOWING PLATFORMS Linux - x86, Microsoft Windows - x86 and Mac OS x - ppc are the primary, so called "officially supported" platforms. SDCC compiles natively on Linux and Mac OS X using using gcc. Windows release and snapshot builds are made by cross compiling to mingw32 on a Linux host. Windows 9x/NT/2000/XP users are recommended to use Cygwin (http://sources.redhat.com/cygwin/) or may try the unsupported Borland C compiler or Microsoft Visual C++ build scripts. SUPPORT OF SDCC
SDCC and the included support packages come with fair amounts of documentation and examples. When they aren't enough, you can find help in the places listed below. Here is a short check list of tips to greatly improve your chances of obtaining a helpful response. 1. Attach the code you are compiling with SDCC. It should compile "out of the box". Snippets must compile and must include any required header files, etc. Incomplete information will hamper your chance of a timely response. 2. Specify the exact command you use to run SDCC, or attach your Makefile. 3. Specify the SDCC version (type "sdcc -v"), your platform and operating system. 4. Provide an exact copy of any error message or incorrect output. Please attempt to include these 4 important parts, as applicable, in all requests for support or when reporting any problems or bugs with SDCC. Though this will make your message lengthy, it will greatly improve your chance that SDCC users and developers will be able to help you. Some SDCC developers are frustrated by bug reports without code provided that they can use to reproduce and ultimately fix the problem, so please be sure to provide sample code if you are reporting a bug!
USING SDCC Getting Started: Download SDCC from http://sdcc.sourceforge.net/ If you are developing on a Windows platform I strongly recommend youget http://prdownloads.sourceforge.net/sdcc/sdcc-2.5.0setup.exe (orwhatever is the latest revision) because it has an install wizard which will copy the files and will ask you if you want SDCC added to your path(HINT: I recommend you add SDCC to your path!) The most up-to-date documentation is at http://sdcc.sourceforge.net/doc/sdccman.html/. SDCC also comes with anolder revision of the same documentation which is installed in C:\Program Files\SDCC\doc\sdccman.html\index.html by default. Students have reported experiencing problems with rev 2.3.0 and rev2.4.0 of SDCC, so make sure you are using rev 2.5.0 or newer.
Download GNU make from http://ece.colorado.edu/~mcclurel/make.exe. o You can add make to your path as well. " If you are developing on Windows XP: Right click on My Computer Select the Advanced tab Click on Environment Variables Select PATH and Edit if it already exists. Otherwise click New and create a PATH variable. Add the location of make.exe to the Variable Value " If you are developing on another version of Windows you will need to investigate further because the Environment variables maynot be in the same location. For example, in Windows NT look in Start/Settings/Control Panel/System and select the Environment tab to modify the PATH variable. SDCC Memory Models SDCC basically has two memory models: Small and Large The large memory model will allocate all variables in external RAM by data or near keyword DEFAULT " Variables stored in internal RAM must be declared with the
The small memory model will allocate all variables in internal, directlyaddressable RAM by default " Variables stored in external RAM must be declared with the xdata or far keyword ! SDCC recommends the use of the small memory model for more efficient code. However, for this class, since we are using combined program and data memory spaces, I think it is safer to use the large memory model. ! Be aware that, regardless of the memory model you choose, if you do not explicitly declare a pointer as data/near or xdata/far it will be 3 bytes!
SDCC Basics
Assuming that the location of SDCC is defined in your path, you can use the following syntax for your header files: #include <stdio.h>
To use SDCC on the command line, use a command line syntax similar to the following (note: a more complete list of flags is shown in the example makefile later): sdcc --code-loc 0x6000 --xram-loc 0xB000 file.c SDCC will generate the following output files: file.asm Assembler file created by the compiler file.lst Assembler listing file created by the assembler file.rst Assembler listing file updated by the linkage editor file.sym Symbol listing created by the assembler file.rel Object file created by the assembler, Input to the linkage editor file.map Memory map for the load module created by the linker file.mem Summary of the memory usage file.ihx This is the load module in Intel hex format By default SDCC uses the small memory model The assembler is given the memory locations as .area directives instead ofORG statements. You must remember to use the --code-loc and --xram-loc directives because this tells the linker where to place things in memory! You can examine the file.rst and file.map output files to verify that
your code and data are assigned to the correct location. ! SDCC standard library routines Most standard routines are present (printf, malloc, etc) However: " printf depends on putchar() which is not implemented. You must implement putchar() This allows you to decide where printf is displayed (on a terminal via serial port, on an LCD, etc) The putchar() function must have the following format: void putchar(char c); If you need a getchar() function, the format is: char getchar(); malloc depends on having heap space created but SDCC does notautomatically create heap space for your program. You must provide heap space for malloc to allocate memory from. This can be done by: #include <malloc.h> #define HEAP_SIZE 4000
unsigned char xdata heap[HEAP_SIZE]; void main() { init_dynamic_memory((MEMHEADER xdata *)heap, HEAP_SIZE); } SDC INTERRUPT SUPPORT To write an ISR in C, create a function similar to the following format: void isr_foo() interrupt 1 { } " This format tells SDCC to generate an interrupt vector (at offset0x0B from the --code-loc address) that calls isr_foo in response tointerrupt 1. " It also tells SDCC to generate a RETI instruction instead of a RETinstruction to return from a call to isr_foo(). o The standard code generated for the interrupt is not very efficient. SDCC takes a conservative view and will save registers on the stack before executing any of your code in the ISR and it will restore those registers
before executing the RETI instruction. " You can use the keyword _naked to make your interrupt faster. This keyword will prevent SDCC from generating any entry/exit code to save registers for your ISR. WARNING: If you use the _naked keyword you must save and restore any registers that are modified by your ISR or you must guarantee that no registers are used by your ISR. I would only recommend using the _naked keyword if your ISR only contains inline assembly in which case you know explicitly which registers are used or you are setting a single bit (such as a port pin) in which case no registers are used. You can use the _naked keyword on any function, not just for ISRs. In non-ISR routines you must be aware of the calling convention used and save/restore the registers you used within your function as appropriate. ! SDCC serial port initialization o There is no support routine built into SDCC to initialize the serial port o If you want to use the serial port with your C program that you burn intoEPROM you will have to initialize the hardware first.
CHAPTER 7 FLASH MAGIC
FLASH MAGIC Flash Magic is a PC tool for programming flash based
microcontrollers from NXP using a serial protocol while in the target hardware Flash Magic is a feature-rich Windows based tool for the downloading of code into NXP flash microcontrollers. It utilises a feature of the microcontrollers called ISP, which allows the transfer of data serially between a PC and the device. Flash Magic can erase devices, program them, read data and read and set various configuration information. Rather than providing the basic features of ISP, Flash Magic adds additional features and intelligence, allowing complex operations to be performed. For
example, erasing can be any collection of pages pages, blocks, the hex file to be programmed or the entire device. Some devices store the ISP bootloader in flash memory, so Flash magic implements methods to protect this code from being erased. Additional advanced features of Flash Magic include the
automatic programming of checksums, entering ISP mode via a serial command, execution of Just In Time modules allowing endless flexibility in the data programmed, control over RS232 signals to place devices into ISP mode, and control over the timing of such signals. Flash Magic has been available for free for over six years and supports all current 8-bit (8051), 16-bit (XA) and 32-bit (ARM) flash microcontrollers from NXP. . Possible Uses Some ideas for applications built on the Flash Magic platform:
Custom ISP tool for in-house use, for example production line programming where it is essential the user interface is simplified as much as possible End user ISP tool for updating the firmware of products. You can build the hex file into the application or allow it to be fetched over the internet. Adverts for new products could be
displayed to the user. Use one tool for all your products involving potentially multiple NXP microcontrollers.
Gang programming tool. Invoke multiple instances of the Flash Magic DLL in seperate threads, each using a different COM port to allow parallel ISP programming Future-proofing products. Rather than write your own ISP tool and have to keep updating it for new NXP devices, updates to the DLL will automatically add new devices
Screenshots Main window
Hex file information
Execute from RAM or Flash (LPC2xxx)
Display flash memory
Device signature
Start bootloader
Blank check
Advanced options - timeouts
Advanced options hardware
Executing a script
Features

Straightforward and intuitive user interface Five simple steps to erasing and programming a device and setting any options desired Programs Intel Hex Files Automatic verifying after programming Fills unused Flash to increase firmware security Ability to automatically program checksums. Using the supplied checksum calculation routine your firmware can easily verify the integrity of a Flash block, ensuring no unauthorized or corrupted code can ever be executed Program security bits Check which Flash blocks are blank or in use with the ability to easily erase all blocks in use Read the device signature Read any section of Flash and save as an Intel Hex File Reprogram the Boot Vector and Status Byte with the help of confirmation features that prevent accidentally programming incorrect values
Display the contents of Flash in ASCII and Hexadecimal formats Single-click access to the manual, Flash Magic home page and NXP Microcontrollers home page Ability to use high-speed serial communications on devices that support it. Flash Magic calculates the highest baudrate that both the device and your PC can use and switches to that baudrate transparently Command Line interface allowing Flash Magic to be used in IDEs and Batch Files Manual in PDF format Supports half-duplex communications Verify Hex Files previously programmed Save and open settings Able to reset Rx2 and 66x devices (revision G or higher) Able to control the DTR and RTS RS232 signals when connected to RST and /PSEN to place the device into BootROM and Execute modes automatically. An example circuit diagram is included in the Manual. Essential for ISP with target hardware that is hard to access. Able to send commands to place the device in BootROM mode, with support for command line interfaces. The installation includes an example project for the Keil and Raisonance 8051 compilers that show how to build support for this feature into applications. Able to play any Wave file when finished programming.
Built in automated version checker - helps ensure you always have the latest version. Powerful, flexible Just In Time Code feature. Write your own JIT Modules to generate last minute code for programming. Uses include:
o o o o o o o o
Serial number generation Copy protection and copy authorization Storing program date and time - manufacture date Storing program operator and location Lookup table generation Language tables or language selection Centralized record keeping Obtaining latest firmware from the Corporate Web site or project intranet
Sponsored by NXP Semiconductors Features automatically updating Internet links including links to related technical documents, software updates, utilities and code examples, using EmbeddedHints technology Displays information about the selected Hex File, including the creation and modification dates, flash memory used, percentage of the current device used Completely free! Flash Magic works on any versions of Windows, except Windows 95. 10Mb of disk space is required
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DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

AT89S52 MICRO CONTROLLER

REGULAT ED POWER SUPPLY

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

IR receiver module TSOP

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

Suitable burst length 10 cycles/burst

CHAPTER 2 INTRODUCTION TO MICROCONTROLLER AND EMBEDDED SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

MICROCONTROLLER VERSUS MICROPROCESSOR What is the difference between a Microprocessor and

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

Onchip clock oscillator.

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

PIN DIAGRAM OF GENERAL PURPOSE MICROCONTROLLER

DENSITY BASED TRAFFIC CONTROL SYSTEM

Program Store Enable is the read strobe to external

DENSITY BASED TRAFFIC CONTROL SYSTEM

Port 1 is an 8-bit bidirectional I/O port with internal

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

ADD A,R2 SUBB A,R5

;Add the value of R2 with A ;Subtract the R5 (which has R3+R4)

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

The Data Pointer

The Data Pointer (DPTR) is the 8052s only

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

CHAPTER 3 AT89S52 MICROCONTROLLER

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM

DENSITY BASED TRAFFIC CONTROL SYSTEM