technology developed by IC manufacturers, who became their customers.Some memory circuits now sell for less than 20nanodollars/transistor. Today, implanters and other fab-rication hardware must meet aggressive productivity tar-gets to achieve this minuscule cost. A large wafer fabri-cator may process up to 50,000 wafers/month, witheach wafer requiring 20 to 30 implants. This outputrequires the use of about 20 implanters, each with thecapacity to implant more than 200 wafers/h. In practice,maximum implanter throughput typically ranges from250 to 270 wafers/h, including placing the wafers intoand removing them from sealed cassettes used by auto-mated material-handling systems. This throughput isachieved for wafer sizes of 150, 200, and 300 mm.Depending on the configuration of the beam line and theend station (the wafer-processing chamber), an implanter occupies an area of 16 to 28 m
. Thus, fabrication spaceposes almost as significant a barrier as capital costagainst compensating for poor throughput by installingadditional implanters.
Among semiconductor-processing techniques, ionimplantation is nearly unique in that process parameters,such as concentration and depth of the desired dopant,are specified directly in the equipment settings for implant dose and energy, respectively (Figure 1). This dif-fers from chemical vapor deposition, in which desiredparameters such as film thickness and density are complex func-tions of the tun-able-equipmentsettings, whichinclude tempera-ture and gas-flowrate. The number of implants need-ed to complete anIC has increasedas the complexity of the chips hasgrown. Whereasprocessing a sim-ple n-type metaloxide semiconduc-tor during the1970s may haverequired 6 to 8 implants, a modern complementary-metal-oxide-semiconductor (CMOS) IC with embeddedmemory may contain up to 35 implants. The technique’s applications require doses and ener-gies spanning several orders of magnitude. Mostimplants fall within one of the boxes in Figure 2. The boundaries of each box are approximate; individualprocesses vary because of differences in design trade-offs. Energy requirements for many applications havefallen with increased device scaling. A shallower dopantprofile helps keep aspect ratios roughly constant as later-al device dimensions shrink. As energies drop, ion dosesusually, but not always, decline as well. The width of thestatistical distribution of the implanted ions decreases with energy, and this reduces the dose required to pro-duce a given peak dopant concentration. The result is
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Bonded wafer splittingfor silicon on insulator (H, He)
Polysilicondoping (As, B)Source–draincontact(As, BF
D O S E ( a t o m s / c m
, B)Preamorphization(Ge, Si)Bipolar buriedsubcollector (P, As)Latch-up/electrostaticdischargeprotection(B)CMOSretrograde wells(P, B, As)Channel engineering(As, BF
, P, B, In, Sb)Threshold voltage adjust(As, BF
, B, P, In) Antipunch-through(As, B, In, Sb)Noise isolation wells (P, B)Charge-coupleddevice wells (B)
Dual-slit extractionelectrodeElectron confinementbeam guide Analyzer magnetedge focusingElectronconfinementbeam tunnelFlag Faraday SelectableresolvinghousingDeceleration groundextentionPlasmaelectronflood(xenon) Wafer
Figure 2. Dose andenergy require-ments of majorimplantation appli-cations (speciesshown roughly inorder of decreasingusage).Figure 3.Schematic of theelectron confine-ment technologynecessary totransport severalmilliamperes of beam at energiesbelow 10 keV in amodern high-cur-rent beam line.