JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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Compare Performance of 2D and 3D Mesh Architectures in Network-On-Chip

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract The 3Dimentional Network on chip (NoCs) architectures is capable of achieving higher throughput, lower latency, and lower energy dissipation at the cost of small silicon area overhead. In this paper, we survey the 2d-mesh and 3d-mesh of NOCs to showing their intrinsic advantages related to each other. These topologies compared with average of propagation delay, average of hop count and impact of fault in bandwidth utilization. Index Terms 3D-NoC (Three-dimensional Network on chip), 3D-IC (Three-dimensional integrated- circuit), MPSoC (Multiprocessor Systems-on-Chip), IP (intellectual property).

1 INTRODUCTION
Moore's law predicts that by 2008, it will be possible to integrate over a billion transistors on a single chip. Current core based on SOC methodologies will not respond to the needs of the billion transistor era. Network on Chip (NOC), a new chip design paradigm concurrently proposed by many research groups[1],[2],[3] is expected to be an important architectural choice for future SOCs. The proposed NOC architectures offer a general but fixed communication platform which can be reused for a large number of SOC designs. A concept of computer network in layers based on the classical OSI reference model is used by all of proposed NOC architectures. We predict that NOC architecture would facilitate reuse at various levels of system design, thus reducing the time to design and test. However, NOC research is still in its infancy. A higher-level modelling will give us the insight of knowing more about its architecture. We would use the tool, Network Simulator ns-2 [4],[5] which has been extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol, routing algorithms. This paper reports some experimental results based on the simulation of NOC using ns-2. In the following, we give a brief overview of our NOC architecture and introduction to ns-2. In section II, we describe how various aspects of our NOC architecture was modelled using ns-2. As semiconductor technology improves, the number of processing cores integrated on a single chip has continually increased. To connect many cores on a chip, Network-on-Chips (NoCs) [6, 7, 8] that introduce a packetswitched network structure have been widely employed instead of traditional bus-based on-chip interconnects. The performance bottleneck imposed by on-chip interconnects in the deep submicron regime of process technology has been widely documented [9], as have the benefits of standardization of on-chip communication [10]. Implementing a standardized communication architecture such as a packet-switched NoC for massively integrated multiprocessor systems provides an abstraction of the global interconnection link and can greatly reduce design effort, potentially at the cost of some area and possibly power and performance penalties. The suitability of the NoC as a communication architecture depends on the overall system; i.e. the number of autonomous functioning blocks, the degree of parallelism, and area and performance requirements dictate its usefulness [12].

2 BACKGROUND
On-chip interconnection is a widely studied research field and good overviews are presented [12],[13], which illustrate the various interconnection schemes available for present ICs and emerging Multiprocessor Systems-onChip (MPSoC) architectures. A NoC-based interconnection is able to provide an efficient and scalable infrastructure, which is able to handle the increased communication needs. The network architecture, or topology, describes the physical organization of the interconnections network. A network topology can be classified as being either direct or indirect. A node in a network can be a terminal node, which acts as a source and sink for data, a switch that routes data, or both. In a direct network, every node acts as a terminal node. In an indirect network, a node is either a terminal or a switch node. The networks shown in Figure 2.7 are direct networks. A direct network can be redrawn as indirect by redrawing each node as two nodes and showing the switch and terminal nodes separately. Designers of large-scale SoCs must be aware of the advantages and disadvantages of each architecture in order to select an appropriate candidate for their implementations. The metrics that are of interest can be broadly categorized as [14]: performance (latency, throughput, cross-section bandwidth),

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energy consumption, reliability (error detection and/or correction), scalability, implementation cost (area).

2.1 Why 3D NoC?

Three-dimensional integrated circuits (3D-ICs) are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, networks-on-chip (NoCs) are an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain [15]. Technology scaling is causing the energy consumption of the on-chip network to become an increasingly important design criteria. The goal of macronetworks is to maximize performance without regard for energy consumption, especially for large scale parallel computers where throughput and latency are of primary importance. It therefore stands to reason that a straightforward adaptation of macronetwork implementations for network-onchip is not appropriate. The problem faced by chip designers is that the design criteria run contrary to one another: Minimizing the energy consumption and maximizing performance are usually conflicting goals. Increased reliability usually means higher complexity, which results in larger area, degraded performance, and higher energy consumption. Therefore, designing a NoC interconnect requires searching through a vast multidimensional design space. There are many design parameters that can affect system performance and cost, but the design decision that has the largest impact is the choice of topology. The remainder of this section will briefly discuss the basic network topologies that other topologies are derived from.

tions are needed to make sure the erroneous results will not contaminate the application environment. In the case that a fault occurs in the communication path, such as link failure and scrambled messages, a fault-tolerant communication protocol suite, including error-resilient coding schemes, are needed to ensure the reliable delivery of on-chip messages on top of an unreliable on-chip communication substrate. Time to Failure Faults, can occur throughout the lifetime of an IC. Using the point when the chip is packaged and tested as the watershed event, we distinguish between before-shelf faults and after-shelf faults. Currently, chips with before shelf faults, i.e., defects which are discovered during testing, are invariably discarded. Only dies with no discovered defects are shipped out as products. With the shrinking feature size, it is becoming increasingly difficult to achieve decent yield with reasonable cost. The low yield problem will become more acute for the 90nm technology and beyond. On the other hand, the potential yield of the manufacturing process can increase tremendously if some defects on the die can be tolerated in the ICs after-shelf life. Static fault masking and isolation techniques, both hardware and software based, can be used to use these previously deemed Bad chips in commercial products, such as Pico Chip [18]. For after-shelf faults, dynamic fault detection and recovery means are needed to ensure the correct function of the chip as long as possible. Furthermore, graceful degradation of system performance is necessary for some mission-critical Applications.

2.3 Related Work

Up to now NoC designs were limited to two dimensions. But emerging 3D integration technology exhibits two major advantages, namely, higher performance and smaller energy consumption [19]. A survey of the existing 3D fabrication technologies is presented by Beyne [20]. The survey shows the available 3D interconnection architectures and illustrates the main research issues in current and future 3D technologies. Through process/integration technology advances, it is feasible to design and manufacture NoCs that will expand in the third dimension (3DNoCs). Thus, it is expected that 3D integration will satisfy the demands of the emerging systems for scaling, performance, and functionality. A considerable reduction in the number and length of global interconnect using 3D integration is expected [21].

2.2 Fault Model

There exist several dimensions in classifying the possible fault occurrences during the life cycle of an MPSoC. We list the classification as follows: Duration In terms of duration, the faults can be classified into transient faults and permanent faults [16]. In the case of the MPSoC, both types of fault can occur in the chip life cycle. Crash failures are permanent faults which occur when a tile halts prematurely or a link disconnects, after having behaved correctly until the failure. Transient faults can be either omission failures, when links lose some messages and tiles intermittently omit to send or receive, or arbitrary failures (also called Byzantine or malicious), when links and tiles deviate arbitrarily from their specification, corrupting or even generating spurious messages. [17] Location In general, MPSoC designs consist of two integrated parts, the Processing Elements (PEs) and Networkon-Chip (NoC). Faults can occur in both parts. In the case that a fault occurs in the PEs, the computation results will be erroneous. Dynamic fault detecting and masking ac-

3 NETWORK AND SYSTEM ARCHITECTURE

One of the widely used NoC topologies is the Mesh architecture. We analyse the performance of a Mesh-based NoC in presence of permanent faults With IP routing adopted.

3.1 Topology and Hardware Architectures

Our NOC is a scalable packet switched communication platform for single chip design. The NOC architecture consists of a mesh of switches with some resources. Re-

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sources Are Heterogeneous or can be homogeneously. A resource can be intellectual properties (IPs). Two different network topologies have simulated namely the 2D mesh and 3D mesh. 2D topology is of size 8x8 while the 3D Mesh topology built from 4x4x4 routers.

cores communicate with each other through switches. We assume the buffer size in each resource is infinite but finite in switches. This implies the packet being dropped cannot happen in resources but only take place in switches [23].

SIMULATION FRAMEWORK

The mesh-based 2D and 3D NoCs simulated by NS2 (a network simulator). We reduce all parameters as multiply of 1000 to support the simulation time. To compare of these architectures in term of packet forwarding we consider the bandwidth between switches is one Megabit/Sec. The bandwidth between resources and switches is ten times bigger than the bandwidth of switches to switches. We consider the traffic source for each communicated core was UDP, and the bandwidth of cores that needs was equal to one Megabit/Sec and the delay of switch-to-switch or resource to switch is equal to 10 milliseconds.

EVALUATIONS AND SIMULATION RESULTS

Fig . 1. Two-Dimensional mesh 8*8 Noc.

Four parameters communication load, Fault-Tolerant, End-to-End Delay and Hop count consumption are defined for evaluation performance of our architectures.

5.1 Throughput and communication load In this section, the proposed scheme evaluated through simulations in terms of performance. We consider that two resources 0 and 126 are communicating together that have the maximum distance. A fault between switches 5 and 7 has occurred at time 1.2. This permanent fault occurs in places that we have communication, as shown in fig .3, the communication load has reduced.

Fig . 2. . Three-Dimensional Mesh 4*4*4 Noc.

We use nostrum Mesh architecture of 2-dimension 8x8 architecture [22], with equal link delay that implemented in real world that shown in Fig .1 and fig .2. The square nodes stand for IPs and the circle nodes stand for switches. This topology easily scaled to different sizes. The 3D router used here has a 7x7 crossbar switch, whereas the 2D router uses a 5x5 crossbar switch. Also, each router has a routing table And based on the source or destination address, the routing table decides which link the outgoing packet should use. The common characteristic of NoC architectures is the constituent IP

Fig . 3. supported bandwidth in 2D and 3D NoC Mesh

5.2 Fault-Tolerant The faults that occur in NoC have two types as below: Permanent Faults. Transient Faults.

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Depend of the nature of fault that was when and where tacked place, we consider a permanent fault that occurs in time 1.0, with three hops distance from the source switch and transient fault was negligible.

Fig . 6. Average hop count in two architecture.

As shown in fig.6, the 3D-mesh has fewer hop count related 2D-mesh architecture. These hop count has not effect on fault or bandwidth.
Fig . 4. Lost packets in two architecture.

As shown in fig .4, when a permanent fault occurs in communication path, the number of lost packets in mentioned architectures was equal to each other.

CONCLUSIONS AND FUTURE WORK

5.3 End to End Delay

End to end delay is another parameter that we consider for evaluation performance of these architectures.

Through detailed simulation-based analysis of the reliability and network performance, we can demonstrate the 3D-NoC proposed in this paper could empower high throughput of data transmission with dramatic hopCount reduction.

Table 1-Comparison 2D AND 3D NOC

Parameter Avg propagation delay Avg hop count NOC 2d-mesh 3d-mesh 0/220 s 16.00 0/150s 11.00 Improvement per cent 31/81% 31/25%

REFERENCES
[1] M. Sgroi, et al, "Addressing the System-on-a-Chip Interconnect Woes Through Communication-based Design", 38th Design Automation Conference, June, 2001. Luca Benini, Giovanni De Micheli, "Network on Chips: A new SoC Paradigm", IEEE computer, Jan., 2002. Shashi Kumar, et. al, "A Network on Chip Architecture and Design Methodology", IEEE Computer Society Annual Symposium on VLSI, Pittsburgh,Pennsylvania, USA, April 2002. LBNL Network Simulator, http://www-nrg.ee.lbl.gov/ns/ The network simulator - ns-2, available at http://www.isi W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. Proceedings of the Design Automation Conference, pages 684689, June 2001. L. Benini and G. D. Micheli. Networks on Chips: Technology And Tools. Morgan Kaufmann Publishers, USA, 2006. S. Vangal et al. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. Proceedings of the International Solid-State Circuits Conference, Feb. 2007.

[2] Fig . 5. Average end to end delay in two architecture. [3]

As shown in fig .5, the average end to end delay between of mentioned cores in 3D-mesh is fewer than 2D-mesh architecture. This means the transfer rate in 3D-mesh is faster than 2D-mesh, with equal switches and resources.

5.4 Hop count

In the worst case, which the source and destination nodes have the maximum distance, for transferring packets in 2D topology 16 hops needed while in 3D topology packets are transferring only by 11-hop count. The difference of average hop count in both architectures has shown in fig.6.

[4] [5] [6]

[7] [8]

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[9] [10] [11]

[12]

[13] [14]

[15]

[16] [17] [18] [19]

[20]

[21]

[22] [23]

D. Sylvester and K. Keutzer. Getting to the bottom of deep submicron. In Proc. ICCAD, pages 203211, 1998. W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. DAC, pages 684689, 2001. A. Y. Weldezion, M. Grange, D. Pamunuwa, Zhonghai Lu, A. Jantsch, R. Weerasekera, H. Tenhunen, "Scalability of Networkon-Chip Communication Architecture for 3-D Meshes," Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09), San Diego, pp. 114-123, May 2009. J.Duato, S. Yalamanchili, andN. Lionel, InterconnectionNetworks:An Engineering Approach. San Francisco, CA: Morgan Kaufmann Publishers Inc., 2002. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann Publishers Inc, 2003. D. Bertozzi, Network architecture: Principles and examples, in Networks on Chips: Technology and Tools, ser. The Morgan Kaufmann Series in Systems on Silicon, G. D. Micheli and L. Benini, Eds. Morgan Kaufmann, Jul. 2006, ch. 5, pp. 147202. B. Feero and P. Pande, Performance evaluation for threedimensional networks-on-chip, in IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI07, pp. 305310, 2007. [10] D. K. Pradhan. Fault-Tolerant Computer System Design. Prentice-Hall, Inc., 1996. [11] T. Dumitras, "On-Chip Stochastic Communication", Electrical and Computer Engineering, May 1st, 2003. [12] W. Robbins. Redundancy and binning of picoChip processors. Fall Processor Forum, 2004, San Jose, CA. E. Beyne, 3D system integration technologies, In International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, April 2006, 19. E. Beyne, The rise of the 3rd dimension for system integration, In Proc. of International Interconnect Technology Conference, Burlingame, CA 57 June, 2006, 15. J. Joyner, R. Venkatesan, P. Zarkesh-Ha, J.Davis, and J.Meindl, Impact of three dimensional architectures on interconnects in gig scale integration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9 (Dec. 2001) (6): 922928. Nostrum, http://www.imit.kth.se/info/FOFU/Nostrum. Y-R. Sun, S. Kumar, and A. Jantsch, "Simulation and evaluation of a network on chip architecture using ns-2", In Proceedings of the IEEE NorChip Conference, November 2002.