JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

ORG

113

A Model Of Exponential Relationship To Estimate Leakage With Verilog Codes

M. mohammadian , N. Mozayani, A.F. nejad Abstract-Leakage current is becoming a very important factor today in determining the feasibility of designs. One of the problems that always exists in design is to find the leak using software tools. It is important to know the amount of leakage of your design components in advance, so that necessary changes can be made to the plan. Nevertheless the fundamental problem remains with implementation of the plan for the synthesis of the leak with simulation tools. In the method presented in this paper, using mathematical relationship and knowing the number of gates, well calculate the amount of leakage of the circuit within a very short time with less than 10% error and without utilizing any specialized software. And at last we present a small algorithm that work by our purpose. Keywords: potency of leakage, current of leakage, calculation error, exponential formula ,verilog codes

INTRODUCTION: The demand for higher speed in processors has forced designers to place more transistors on a chip to get better performance. The increasing demand for smaller and more portable computing and wireless communication devices makes power dissipation a major concern in low power circuit designs. As a result, designers have been forced to reduce the dimension of devices[1][4]. Nowadays finding the value of potency and the leakage current is one of the main requirements in the design of a circuit which requires precise stimulation equipments. Such equipments are expensive and using them requires substantial time .In this paper Without a clear algorithm to calculate potency and leakage current, designers were determined to find a way to solve this problem without utilizing specialized software. Based on a number of experiments previously conducted on circuits, pointing out that error is within acceptable level, the relation we got is that considering the total number of gates used in each circuit, we can calculate the leakage in the real time. We can point to the composition: P=aN+B for calculating

method of wastes caused by leakage[4][5]. This composition does not have enough accuracy because it depends on estimating the two parameters i.e. a and b, which is other thing done for applying the special algorithm for calculating the potency of leakage in a circuit [3][6]. Using the algorithm itself requires special programming language in relation to the special situation of the design and also requires time and money .In this paper the value of leakage potency of several benchmark samples were calculated with a wide range of different gates, using the Electronic design automation and hspice software and then with empirical method. The leakage of the circuits was estimated with an acceptable percentage of error in real time and the results were compared, presented and the percentage of the errors compared to the simulator was calculated. The value of leakage current and later the leakage potency were calculated because the idea generated in the mind needs to estimate the potential leakage value according to this idea and make the necessary changes to reduce the leakage. Another benefit of this method is that it frees up the designer from

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

114

focusing on the use of the software during the initial design phase[2]. 2-The Proposed Method: By considering 11 models of different benchmarks and designing them with the help of appropriate software we intend to calculate the potency of the leakage for each of them. You should keep in mindthatthedesignofacircuit which contains a wide range of gates and level of synthesis is a very difficult thing to do, because there is no specific pattern for calculating the potency of leakage. Representing mathematical logics and relations, we can give an exponential term using which we can calculate the value of leakage in the real time mood considering the number of gates, but while performing we should consider the following 2 points: 1) Disregard the type of gates used in each model that are tested 2) The formula that represented is usable in the circuits with a great number of gates and the outcome will be close to the outcome of the software. The linear formula represented is as follow: (1) P=ln(N)*vdd

TABLE 1: A flow rate of current and power leakages, With the number of gates used, Samples of each circuit is calculated by the Hspice software

Bench #Gates Leakage mark current(

C880 C499 C1355 S1488 C1908 S5378 C3540 C7552 S9234 C5315 C6288 383 202 546 550 880 1004 1669 1916 2027 2307 2388 5.40 6.5 7.21 7.25 6.57 7.4 26.4 29.38 25.63 29.18 26.6

Leakage power(nw)
16.20 19.5 21.63 21.75 19.71 22.2 79.2 88.14 76.9 87.54 79.8

By using equation #1, we could observe leak and leak flow rate in real time. If the number of gates used in our circuit design were more than 1500 we must use equation #2. It is a method is helpful in achieving a lower error rate in a huge circuit. (REF)Table (2) shows a number of survey results that have been done on a number of benchmarks.
TABLE 2: A flow rate of current and power leakages, With the number of gates used, Samples of each circuit is calculated by the Equations.

In this equation (N) is the number of gates. Based on mathematical logic, well obtain an accurate approximation, if we get a (LN) from the number of gates per circuit. As well show in the rest of this paper, the results gained in a higher number of benchmarks, have an acceptable proximity to the results gained by the synthesis the HSPICE simulation. As mentioned earlier in the (REF)Table(1), a flow rate of current and power leakages, with the number of gates used, samples of per circuit is calculated by the software[7][8].

Bench #Gates mark

C499 C880 C1355 S1488 C1908 S5378 C3540 C7552 S9234 C5315 C6288 202 383 546 550 880 1004 1669 1916 2027 2307 2388

Leakage Estimation Leakage power(nw) current(

5.3 5.9 6.3 6.3 6.7 6.9 25.96 26.4 23.3 27.1 27.2 15.9 17.7 18.9 18.9 19.2 20.7 77.9 79.2 69.9 81.3 81.6

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

115

In additional about 3.5 in second formula is for last three benchmarks and useable for all of the test bed that include are more than 1500 gates are used. So, in the last three benchmarks should have been referred to this point, after the sum of the gates and (LN) it must be multiplied by the number of 3.5, so this method with relation (2) introduced. This relation was found by having been tested on the 20 test bed with different gates from 2000 up to 6000 gates. (2) P=ln(N)(3.5)*vdd

{a, b, } = gate [7:0]; #10 $display ("a=%b, b=%b, , sum=%b", a, b, sum); end end //instantiate the module into the test bench .a(a), .b(b), .sum(sum)// means all of the gates that use in our ic ); End module

3-Simulation Results And Comparison Error by Real Result: In the (REF)Table 3 we will show a percent of error, between the results achieved by HSPICE Simulation and the results of linear relationship presented each of the benchmarks of case study[8].for counting of gates we developed a verilog codes . in this initially we run the convert program for convert test bed circuits description to a suitable text for verilog codes . this codes shown as follow
module input gates and results (a, b, sum); input a, b; //list inputs gates a and b are two model gates user can define many parameter for gates output sum; assign { sum} = a + b; endmodule //test bench for a model ics module gates counter reg [n:0] a, b;//gates and save all of the gates number //apply stimulus initial begin : apply_stimulus reg [7:0] gate; for (gate = 1; gate < 9000; gate = gate + 1)// gate number in one model begin

TABLE3:
percent of error, between the results achieved by like instrument and the results of linear relationship presented each of the benchmark test we will study..

Bench #Gates mark

C499 C880 C1355 S1488 C1908 C5378 C3540 C7552 S9234 C5315 C6288 202 383 546 550 880 1004 1669 1916 2027 2307 2388

Estimationerror Leakage
20% 9% 12% 12% 1% 6% 1% 9% 9% 6% 6%

According to the results and comparison with results of the simulation curves are plotted below. First, based on the results of model calculations with numbers less than 1500 gates and a second computation with more than 1500 gates. At finally for final check and fine good result we give LN from input some vector to different gates in several ics in test bed and check coefficient leakage. We found that my formula is better in several test for give

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

116

leakage .error of this method in several useful case was1%. In other word we test our method by valid input vector and found leakage by 1% error in real fact. TABLE4:
test of result by input valid vector in Some useful ics. This result found by chosen some input vector

always @ (p) begin if (n<1500!z=1 ); else ; if (n<9000 !z=3.5); else; if (9000<n<1000000 !z=4.5); then

Inputvector

Gatesused coefficient
if (n<=1500); input [x:0] n; while (count)

00/01/10/11 And2 3.2121 000/001/010 And3 0.445 0000/0001/0010 And4 0.672 00/01/10/11 Or2 0.8771 000/001/010 Or3 1.024 0000/0001/0010 Or4 0.6332 00/01/10/11 Nand2 0.540 000/001/010 Nand3 1.650 0000/0001/0010 Nand4 0.9275 00/01/10/11 Nor2 0.094 000/001/010 Nor3 1.4077 0000/0001/0010 Nor4 0.427 In this algorithm who made by verilog we simulate some vector by our purpose and calculate leakage some of the ICs gate.
module power (vdd ,n ,p, sum , cout, parameter); // x and y are big number

begin p= ln(n)*(z)*input [x:0] vdd;

initial begin //addition #0 #10 #10 #10 #10

//apply input vectors

a = 0000_0000; a = 0000_0110; a = 0000_0101; a = 1000_0000; a = 1110_1101; a = 1111_1111;

input [x:0] vdd ; #10 input [4:0] vector; //voltage input //gates [x:0] n; End End

input [x:1] parameter; End module output [7:0] p; // output reg [GATES:0] //define internal ICs reg[3:0]count; ICs reg [4:0] sum; // Counter gats of

4-CONCLUSION: In this paper we have presented a method to estimate leakage current using exponential model in real time. In other words, this method is useful for large benchmark and real circuit. We can predict current and power leakages within an

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

117

average of 8% accuracy in experiments using general simulation such as HSPICE or similar tools. We recommend designers to use this method for testing circuit leakage before implementation. This method is very simple and quick and it is not necessary to know about hard code simulation and spend a long time to implement tools code. You can find leakage using the two methods that were introduced at the beginning. This idea is useful for finding leakage before implementing your design using industry standard tools. Although this method is used with a fewer gates in meridians but due to the lack of proper care in using this method. Perhaps a weak point of this research is in paying attention to meridians with a fewer number of gates. As we know the leakage power is highly dependent on input vector but this method is very useful in finding the initial leakage in real time without the use of software, codes or algorithm which we successfully simulated on several benchmark circuits in the lab. At finally we want shown that if we use this method in some circuit design is very useful and simple. This formula is tested on benchmark who present this paper. We simulate our purpose by our algorithm. I think this solution are good for calculate circuit that used medium rang number of GATES. References [1] M. C. Lee and H. Chiueh, "An Implementation of Integrable Low Power Techniques for Modern Cell-Based VLSI Designs," IEEE DESIGN&TEST OF COMPUTERS pp. 890-893. December 13, 2006. [2] srinath R. Naidu " Minimizing standby leakage power in static CMOS circuits" ,IEEE International conference on computer- aided- design,2001. [3] Shengqi Yang, Wayne Wolf, N. Vijaykrishnan, Yuan Xie, Wenping Wang, "Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits,"

vlsid, 18th International Conference on (VLSID'05), pp.165-170, 2005. [4] J. Derakhshandeh, et al., "A precise model for leakage power estimation in VLSI circuits," Proceedings of the 9th (IDEAS05). 1098-8068/05 IEEE. [5] H. J. Jeon, et al., "A novel technique to minimize standby leakage power in nanoscale CMOS VLSI," pp. 1372-1375. 14244-0395-2/06/2006 IEEE. [6] Yongjun Xu, Zuqing Luo, Minimum leakage Pattern Generation Using Stack Effect, In proceeding of ASICON03,Page(s)1239-1242, Oct. 2003. [7] Feng Gao, John P. Hayes, Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction, ComputerAided Design, ICCAD-2004, Page(s)527-532, Nov. 2004. [8] Tadahiro Kuroda, Kojiro Suzuki, et al., Variable Supply-Voltage Scheme for LowPower High Speed CMOS DegitalDesign, IEEE J.Solid-State Circuit, Vol.33, NO.3, Mar.1998.