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Table Of Contents

1.1 Motivation and Prior Work
1.3 Organization Of Thesis
An Overview of our Verification Methodology
2.1 Choice of Representation
3.0.1 Example Term Rewriting System
Equivalence of Term Rewriting Systems
4.1 Definition of theory of equivalence of TRSs
4.2 Alternative Definition and Proof for Equivalence of TRSs
4.3 Computing Comparison points
Verifire : A fully automated proof generator
6.1 Adders
6.2 Shifters and Comparators
7.1 Booth Multiplier
7.2 BISMUL
7.3 Wallace Tree Multiplier
8.1 Results
8.2 Discussion
9.1 Future Work
Appendices
A.1 Project Description
A.2 Verification of the 74181 ALU in ACL2
A.2.1 Using ACL2
A.2.2 The 74181 ALU
A.3 Applying the technique to 16 bit adder operation of 74181 in ACL2
A.4 Verification of a RISC pipeline using our technique
Verilog Code for the Shift-and-Add Multiplier
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Masters Thesis

Masters Thesis

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Published by Nayeem Mohammad

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Published by: Nayeem Mohammad on Feb 11, 2012
Copyright:Attribution Non-commercial

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03/13/2013

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