Y


Y
 
 


 

 
// Module Name:
Andgate
module Andgate(i1, i2,
out);
input i1;
input i2;
output out;
and (out,i1,i2);
endmodule

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AND Gate
------------------------------------------------------Input1
Input2
Output
------------------------------------------------------0
0
0
0
1
0
1
0
0
1
1
1
-------------------------------------------------------

= 


m

// Module Name:
Orgate
module Orgate(i1,
i2, out);
input i1;
input i2;
output out;
or(out,i1,i2);
endmodule

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OR Gate
--------------------------------------------------Input1
Input2
Output
--------------------------------------------------0
0
0
0
1
1
1
0
1
1
1
1
--------------------------------------------------

= 


 
// Module Name:
Nandgate
module Nandgate(i1, i2,
out);
input i1;
input i2;
output out;
nand(out,i1,i2);
endmodule

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NAND Gate
--------------------------------------------------------Input1
Input2
Output
--------------------------------------------------------0
0
1
0
1
1
1
0
1
1
1
0
----------------------------------------------------

= 


m

// Module Name:
Norgate
module Norgate(i1, i2,
out);
input i1;
input i2;
output out;
nor(out,i1,i2);
endmodule

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NOR Gate
------------------------------------------------------Input1
Input2
Output
------------------------------------------------------0
0
1
0
1
0
1
0
0
1
1
0
------------------------------------------------------

= 


m

// Module Name:
Xorgate
module Xorgate(i1, i2,
out);
input i1;
input i2;
output out;
xor(out,i1,i2);
endmodule

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XOR Gate
------------------------------------------------------Input1
Input2
Output
------------------------------------------------------0
0
0
0
1
1
1
0
1
1
1
0
------------------------------------------------------

= 


 m

// Module Name:
Xnorgate
module Xnorgate(i1,
i2, out);
input i1;
input i2;
output out;
xnor(out,i1,i2);
endmodule

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XNOR Gate
-----------------------------------------------------Input1
Input2
Output
------------------------------------------------------0
0
1
0
1
0
1
0
0
1
1
1
------------------------------------------------------

= 


m
// Module Name:
Notgate
module
Notgate(in, out);
input in;
output out;
not(out,in);
endmodule

m  
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NOT Gate
-------------------------------Input
Output
-------------------------------0
1
1
0
--------------------------------

= 


 

// Module Name:
Buffer
module Buffer(in, out);
input in;
output out;
buf(out,in);
endmodule

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BUFFER
--------------------------Input
Output
--------------------------0
0
1
1
---------------------------

= 








// Module Name: HalfAddr
module HalfAddr(sum,
c_out, i1, i2);
output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule

m  
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Half Adder
-------------------------------------------------------------------Input1
Input2
Carry
Sum
-------------------------------------------------------------------0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
--------------------------------------------------------------------

= 


 



module FullAddr(i1, i2, c_in,
c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule

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Full Adder
---------------------------------------------------------------------i1
i2
Cin Cout
Sum
--------------------------------------------------------------------0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
---------------------------------------------------------------------

= 



  

 


// Module Name:
HalfSub
module HalfSub(i0, i1,
bor, dif);
input i0;
input i1;
output bor;
output dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule

m  
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Half Subtractor
--------------------------------------------------------------------Input1
Input2
Borrow Difference
--------------------------------------------------------------------0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
---------------------------------------------------------------------

= 


 
 


// Module Name: FullSub
module FullSub(b_in, i1, i0, b_out, dif);
input b_in;
input i1;
input i0;
output b_out;
output dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule

m  
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Full Subtractor
---------------------------------------------------------------------------------B_in
I1
i0
B_out Difference
---------------------------------------------------------------------------------0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
----------------------------------------------------------------------------------

= 


4


// Module Name: Encd2to4
module Encd2to4(i0, i1, i2, i3, out0,
out1);
input i0;
input i1;
input i2;
input i3;
output out0;
output out1;
reg out0,out1;
always@(i0,i1,i2,i3)
case({i0,i1,i2,i3})
4'b1000:{out0,out1}=2'b00;
4'b0100:{out0,out1}=2'b01;
4'b0010:{out0,out1}=2'b10;
4'b0001:{out0,out1}=2'b11;
default: $display("Invalid");
endcase
endmodule

m  
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4to2 Encoder
-------------------------------------------Input
Output
-------------------------------------------1000
00
0100
01
0010
10
0001
11
-------------------------------------------

= 


 


// Module Name: Decd2to4
module Decd2to4(i0, i1, out0, out1, out2,
out3);
input i0;
input i1;
output out0;
output out1;
output out2;
output out3;
reg out0,out1,out2,out3;
always@(i0,i1)
case({i0,i1})
2'b00:
{out0,out1,out2,out3}=4'b1000;
2'b01:
{out0,out1,out2,out3}=4'b0100;
2'b10:
{out0,out1,out2,out3}=4'b0010;
2'b11:
{out0,out1,out2,out3}=4'b0001;
default: $display("Invalid");
endcase

endmodule

m  
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2to4 Decoder
------------------------------------------Input
Output
------------------------------------------00
1000
01
0100
10
0010
11
0001
------------------------------------------

= 


u  

// Module Name: Mux4to1
module Mux4to1(i0, i1, i2, i3, s0, s1, out);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule

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4to1 Multiplexer
-------------------------------------------------------Input=1011
-------------------------------------------------------Selector
Output
-------------------------------------------------------{0,0}
1
{1,0}
0
{0,1}
1
{1,1}
1
-------------------------------------------------------

= 


   

// Module Name: Dux1to4
module Dux1to4(in, s0, s1, out0, out1,
out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule

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1to4 Demultiplexer
-----------------------------------------------------Input=1
-----------------------------------------------------Status
Output
-----------------------------------------------------{0,0}
1000
{0,1}
0100
{1,0}
0010
{1,1}
0001
------------------------------------------------------

= 


 




 
 
// Module Name:
DFF
module DFF(Clock,
Reset, d, q);
input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge
Clock or negedge
Reset)
if (~Reset)
q=1'b0;
else q=d;
endmodule

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D FipFlop
---------------------------------------------------------------------------------Clock
Reset
Input (d) Output q(~q)
---------------------------------------------------------------------------------0
0
0
0(1)
1
0
0
0(1)
0
0
1
0(1)
1
0
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
1
0
1(0)
1
1
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
0
0
0(1)
1
0
0
0(1)
0
0
0
0(1)
----------------------------------------------------------------------------------

= 


 
 
// Module Name: TFF
module TFF(Clock, Reset, t, q);
input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock ,
negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule

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T FipFlop
---------------------------------------------------------------------------------------------Clock
Reset Input (t)
Output q(~q)
---------------------------------------------------------------------------------------------0
0
0
0(1)
1
0
0
0(1)
0
0
1
0(1)
1
0
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
1
0
1(0)
1
1
0
1(0)
0
1
1
1(0)
1
1
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
0
0
0(1)
-----------------------------------------------------------------------------------------------

= 


  
 
// Module Name: JKFF
module JKFF(Clock, Reset, j, k, q);
input Clock;
input Reset;
input j;
input k;
output q;
reg q;
always@(posedge Clock,
negedge Reset)
if(~Reset)q=0;
else
begin
case({j,k})
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;
endcase
end
endmodule

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JK FipFlop
---------------------------------------------------------------------------------Clock
Reset Input (j,k)
Output q(~q)
---------------------------------------------------------------------------------0
0
(0,0)
0(1)
1
0
(0,0)
0(1)
0
0
(0,1)
0(1)
1
0
(0,1)
0(1)
0
0
(1,0)
0(1)
1
0
(1,0)
0(1)
0
0
(1,1)
0(1)
1
0
(1,1)
0(1)
0
1
(0,0)
0(1)
1
1
(0,0)
0(1)
0
1
(0,1)
0(1)
1
1
(0,1)
0(1)
0
1
(1,0)
0(1)
1
1
(1,0)
1(0)
0
1
(1,1)
1(0)
1
1
(1,1)
0(1)
0
0
(0,0)
0(1)
1
0
(0,0)
0(1)
0
0
(0,0)
0(1)
----------------------------------------------------------------------------------------------

= 


_ 

// Module Name: Count2Bit
module Count2Bit(Clock, Clear,
out);
input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge
Clear)
if((~Clear) || (out>=4))out=2'b00;
else out=out+1;
endmodule

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2 Bit Counter
------------------------------------------------------------------------------Clock
Clear
Output[2]
------------------------------------------------------------------------------0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
1
00
1
1
01
0
1
01
1
1
10
0
1
10
1
1
11
0
1
11
1
1
00
0
1
00
1
1
01
0
1
01
1
1
10
0
1
10
1
1
11
0
1
11
1
1
00
0
0
00
1
0
00
------------------------------------------------------------------------------

= 






// Module Name:
Reg2Bit
module Reg2Bit(Clock,
Clear, in, out);
input Clock;
input Clear;
input [0:1] in;
output [0:1] out;
reg [0:1] out;
always@(posedge
Clock, negedge Clear)
if(~Clear)
out=2'b00;
else out=in;
endmodule

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2 Bit Register
--------------------------------------------------------------------------------------------------Clock
Clear
Input[2]
Output[2]
--------------------------------------------------------------------------------------------------0
0
00
00
1
0
00
00
0
0
01
00
1
0
01
00
0
0
10
00
1
0
10
00
0
0
11
00
1
0
11
00
0
1
00
00
1
1
00
00
0
1
01
00
1
1
01
01
0
1
10
01
1
1
10
10
0
1
11
10
1
1
11
11
0
0
11
00
1
0
11
00
0
0
11
00
---------------------------------------------------------------------------------------------------

=